N74F126D ,Quad buffers 3-StateINTEGRATED CIRCUITS74F125, 74F126Quad buffers (3-State)Product specification 1989 March 28IC15 Data ..
N74F126D ,Quad buffers 3-StateINTEGRATED CIRCUITS74F125, 74F126Quad buffers (3-State)Product specification 1989 March 28IC15 Data ..
N74F126D ,Quad buffers 3-StateFeatures and benefits High impedance NPN base inputs for reduced loading(20 A in HIGH and LOW sta ..
N74F126D ,Quad buffers 3-StatePIN CONFIGURATIONS74F125 74F126OE0 1 14OE0 1 14 V VCCCCD0 2 13 OE3 D0 2 13 OE3Q0 3 12 D3 Q0 3 12 D3 ..
N74F126N ,Quad buffers; 3-StatePIN CONFIGURATIONS74F125 74F126OE0 1 14OE0 1 14 V VCCCCD0 2 13 OE3 D0 2 13 OE3Q0 3 12 D3 Q0 3 12 D3 ..
N74F132D ,Quad 2-input NAND Schmitt triggerPIN CONFIGURATIONThe 74F132 contains four 2-input NAND gates which acceptstandard TTL input signals ..
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N74F126D
Quad buffers; 3-State
1. General descriptionThe 74F126 provides four non-inverting buffer/line drivers with 3-state outputs. The
3-state outputs (nY) are controlled by the output enable input (nOE). A LOW at nOE
causes the outputs to assume a high-impedance OFF-state.
2. Features and benefits High impedance NPN base inputs for reduced loading
(20 A in HIGH and LOW states)
3. Ordering information
74F126
Quad buffers; 3-State
Rev. 4 — 23 January 2013 Product data sheet
Table 1. Ordering informationN74F126N 0 C to +70C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
N74F126D 0 C to +70 C SO14 plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
NXP Semiconductors 74F126
Quad buffers; 3-state
4. Functional diagram
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description1OE to 4OE 1, 4, 10, 13 output enable input (active HIGH) 1.0/0.033 20 A/20A
1A to 4A 2, 5, 9, 12 data input 1.0/0.033 20 A/20A
1Y to 4Y 3, 6, 8, 11 data output 750/106.7 15 mA/64 mA
GND 7 ground (0V) - -
VCC 14 supply voltage - -
NXP Semiconductors 74F126
Quad buffers; 3-state[1] One FAST Unit Load (UL) is defined as 20 A in HIGH state, 0.6 A in LOW state.
6. Functional description[1] H= HIGH voltage level; L= LOW voltage level; X= don’t care; Z= high-impedance OFF-state.
7. Limiting values[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
8. Recommended operating conditions
Table 3. Function table[1] L Z
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VCC supply voltage 0.5 +7.0 V input voltage [1] 0.5 +7.0 V output voltage output in HIGH-state [1] 0.5 VCC V
IIK input clamping current VI < 0 V 30 +5 mA output current output in LOW-state - 128 mA
Tamb ambient temperature in free air [2] 070 C
Tstg storage temperature 65 +150 C
Table 5. Recommended operating conditionsVCC supply voltage 4.5 5.0 5.5 V
VIH HIGH-level input voltage 2.0 - - V
VIL LOW-level input voltage - - 0.8 V
IIK input clamping current 18 --mA
IOH HIGH-level output current 15 --mA
IOL LOW-level output current - - 64 mA
Tamb ambient temperature 0 70 C
NXP Semiconductors 74F126
Quad buffers; 3-state
9. Static characteristics[1] All typical values are measured at VCC =5V.
[2] No more than one output should be tested at a time, and the duration of the test should not exceed one second.
10. Dynamic characteristics
Table 6. Static characteristicsVIK input clamping voltage VCC = 4.5 V; IIK= 18 mA 1.2 0.73 - 1.2 - V
VOH HIGH-level output
voltage
VCC = 4.5 V; VIL = 0.8 V; VIH = 2.0V
IOH= 3mA
VCC = 10% - - - 2.4 - V
VCC = 5% - 3.3 - 2.7 - V
IOH= 15 mA
VCC = 10% - - - 2.0 - V
VOL LOW-level output
voltage
VCC = 4.5 V; VIL = 0.8 V; VIH = 2.0V
IOL =64 mA
VCC = 10% - - - - 0.55 V
VCC = 5% - 0.42 - - 0.55 V input leakage current VCC =0V; VI =7.0V - - - - 100 A
IIH HIGH-level input current VCC = 5.5 V; VI = 2.7V - - - - 20 A
IIL LOW-level input current VCC = 5.5 V; VI =0.5V - - - 20 - A
IOZ OFF-state output current VCC = 5.5 V
VO = 2.7V - - - - 50 A
VO = 0.5V - - - 50 - A output current VCC = 5.5 V [2] -- - 225 100 mA
ICC supply current VCC = 5.5 V; VI = GND or VCC
outputs HIGH-state - 20 - - 30 mA
outputs LOW-state - 32 - - 48 mA
outputs OFF-state - 26 - - 39 mA
Table 7. Dynamic characteristicsGND = 0 V. Test circuit is shown in Figure6.
tPLH LOW to HIGH
propagation delay
nA to nY, see Figure4 2.0 4.0 6.5 2.0 7.0 ns
tPHL HIGH to LOW
propagation delay
nA to nY; see Figure4 3.0 5.5 8.0 3.0 8.5 ns
tPZH OFF-state to HIGH
propagation delay
nOE to nY; see Figure5 4.0 6.0 7.5 3.5 8.5 ns
NXP Semiconductors 74F126
Quad buffers; 3-state
11. WaveformstPZL OFF-state to LOW
propagation delay
nOE to nY; see Figure5 4.0 6.0 8.0 3.5 8.5 ns
tPHZ HIGH to OFF-state
propagation delay
nOE to nY; see Figure5 2.0 4.5 6.5 2.0 7.5 ns
tPLZ LOW to OFF-state
propagation delay
nOE to nY; see Figure5 3.0 5.5 7.5 3.0 8.0 ns
Table 7. Dynamic characteristics …continuedGND = 0 V. Test circuit is shown in Figure6.
NXP Semiconductors 74F126
Quad buffers; 3-state
Table 8. Test data3.0 V 1 MHz 500 ns 2.5 ns 50 pF 500 open open 7.0V
