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P80C592FFA
8-bit microcontroller with on-chip CAN
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
CONTENTS FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION MEMORY ORGANIZATION
7.1 Program Memory
7.2 Internal Data Memory
7.3 External Data Memory I/O PORT STRUCTURE PULSE WIDTH MODULATED OUTPUTS
(PWM)
9.1 Prescaler frequency control register (PWMP)
9.2 Pulse Width Register 0 (PWM0)
9.3 Pulse Width Register 1 (PWM1) ANALOG-TO-DIGITAL CONVERTER (ADC)
10.1 ADC Control register (ADCON) TIMERS/COUNTERS
11.1 Timer 0 and Timer 1
11.2 Timer T2 Capture and Compare Logic
11.3 Watchdog Timer (T3) SERIAL I/O PORT: SIO0 (UART) SERIAL I/O PORT: SIO1 (CAN)
13.1 On-chip CAN-controller
13.2 CAN Features
13.3 Interface between CPU and CAN
13.4 Hardware blocks of the CAN-controller
13.5 Control Segment and Message Buffer
description
13.6 CAN 2.0A Protocol description INTERRUPT SYSTEM
14.1 Interrupt Enable and Priority Registers
14.2 Interrupt Vectors
14.3 Interrupt Priority POWER REDUCTION MODES
15.1 Power Control Register (PCON)
15.2 CAN Sleep Mode
15.3 Idle Mode
15.4 Power-down Mode OSCILLATOR CIRCUITRY RESET CIRCUITRY
17.1 Power-on Reset INSTRUCTION SET
18.1 Addressing Modes
18.2 Instruction Set ABSOLUTE MAXIMUM RATINGS (note 1) DC CHARACTERISTICS AC CHARACTERISTICS CAN APPLICATION INFORMATION
22.1 Latency time requirements
22.2 Connecting a P8xC592 to a bus line
(physical layer) PACKAGE OUTLINES SOLDERING
24.1 Introduction
24.2 Reflow soldering
24.3 Wave soldering
24.4 Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
FEATURES 80C51 central processing unit (CPU) 16 kbytes on-chip ROM,
externally expandible to 64 kbytes2× 256 bytes on-chip RAM,
externally expandible to 64 kbytes Two standard 16-bit timers/counters One additional 16-bit timer/counter coupled to four
capture and three compare registers 10-bit ADC with 8 multiplexed analog inputs Two 8-bit resolution Pulse Width Modulated outputs 15 interrupt sources with 2 priority levelsto 6 external interrupt sources possible) Five 8-bit I/O ports, plus one 8-bit input port shared
with analog inputs CAN-controller (CAN= Controller Area Network)
with DMA data transfer facility to internal RAM1 Mbit/s CAN-controller with bus failure
management facility1 ⁄2AVDD reference voltage Full-duplex UART compatible with the standard 80C51 On-chip Watchdog Timer (WDT) 1.2to16 MHz clock frequency.
GENERAL DESCRIPTIONThe P8xC592 is a single-chip 8-bit high-performance
microcontroller with on-chip CAN-controller, derived from
the 80C51 microcontroller family.
It uses the powerful 80C51 instruction set.
Figure 1 shows a block diagram of the P8xC592.
The P8xC592 is manufactured in an advanced CMOS
process, and is designed for use in automotive and
general industrial applications. In addition to the 80C51
standard features, the device provides a number of
dedicated hardware functions for these applications.
Two versions of the P8xC592 will be offered: P80C592 (without ROM) P83C592 (with ROM).
Hereafter these versions will be referred to as P8xC592.
The temperature range includes (max. fCLK=16 MHz):
•−40to +85 °C version, for general applications
•−40to +125 °C version for automotive applications.
The P8xC592 combines the functions of the P8xC552
(microcontroller) and the PCA82C200 (Philips
CAN-controller) with the following enhanced features: 16 kbytes Program Memory2× 256 bytes Data Memory DMA between CAN Transmit/Receive Buffer and
internal RAM.
The main differences between P8xC592 and P8xC552
are: 16 kbytes programmable ROM (P8xC552 has 8 kbytes) Additional 256 bytes RAM A CAN-controller instead of the I2C-serial interface.
ORDERING INFORMATION
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
BLOCK DIAGRAM
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
PINNING
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
Table 1 Pin description for single function pins (SOT188-2; see note 1)
Notes To avoid a ‘latch up’ effect at power-on: VSS− 0.5V < ‘voltageon any pinat any time’< VDD+ 0.5V. Triggered by a rising edge. ADC operation can also be started by software. RST also provides a reset pulse as output when timer T3 overflows or after a CAN wake-up from Power-down. ALE is activated every six oscillator periods. During an external data memory access one ALE pulse is skipped. See Section 7.1, T able 3 for EA operation. For P83Cxxx microcontrollers specified with the option ‘ROM-code
protection’, the EA pin is latched during reset and is ‘don't care’ after reset, regardless of whether the ROM-code
protection is selected or not.
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592 Pin 55, REF: Selection of input resp. output dependent of CAN Control Register bit 5 (CR.5; see Section 13.5.3 Table 32). If the internal reference is used, then REF should be connected to AVSS via a capacitor with a value of ≥10 nF. After an external reset (RST= HIGH) the internal1 ⁄2AVDD source is activated and, REF is a reference output. If the CAN-controller is in the reset state, e.g. after an external reset, then the1 ⁄2AVDD source is switched off
during Power-down mode. CAN-bus line: CRX0 level> CRX1 level is interpreted as a logic 1 (recessive). CRX0 level< CRX1 level is interpreted as a logic 0 (dominant). The level of AVREF+ must be higher than that of AVREF−.
Table 2 Pin description for pins with
alternative functions (SOT188-2 and NO330; see note 1)
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
Notes To avoid a ‘latch up’ effect at power-on: VSS− 0.5V < ‘voltageon any pinat any time’< VDD+ 0.5V. If the CAN-controller is in the reset state (e.g. after a power-up reset; CAN Control Register bit CR.0; see
Section 13.5.3 Table 32), the CAN transmitter outputs are floating and the pins P1.6 and P1.7 can be used as
open-drain port pins. After a power-up reset the port data is HIGH, leaving the pins P1.6 and P1.7 floating.
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592 FUNCTIONAL DESCRIPTION
The P8xC592 functions will be described as shown in the
following overview: Memory organization I/O Port structure Pulse Width Modulated outputs Analog-to-digital Converter Timers/Counters Serial I/O Ports Interrupt system Power reduction modes Oscillator circuitry Reset circuitry Instruction Set. MEMORY ORGANIZATION
The Central Processing Unit (CPU) manipulates operands
in three memory spaces (see Fig.4) as follows: 16 kbytes internal resp. 64 kbytes external Program
Memory 512 bytes internal Data Memory MAIN- and AUXILIARY
RAM up to 64 kbytes external Data Memory
(with 256 bytes residing in the internal AUXILIARY
RAM).
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
7.1 Program Memory
The Program Memory of the P8xC592 consists of 16 kbytes ROM on-chip, externally expandible up to 64 kbytes.
Table 3 Instruction fetch controlled by EA
Notes This implementation prevents reading of the internal program code by switching from external Program Memory
during a MOVC instruction. By setting a security bit the internal Program Memory content is protected, which means it cannot be read out.
If the security bit has been set to LOW there are no restrictions for the MOVC instruction.
7.2 Internal Data Memory
The internal Data Memory is physically built-up and accessible as shown in Table 4 (see Fig.5).
Table 4 Internal Data Memory size and address mode
Notes MAIN RAM can be addressed directly and indirectly as in the 80C51. AUXILIARY RAM (0to 255): Is indirectly addressable in the same way as the external Data Memory with MOVX instructions. Access will not affect the ports P0, P2, P3.6 and P3.7 during internal program execution. SFRs= Special Function Registers.
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
7.2.1 MAIN RAM
Four 8-bit register banks occupy the lower RAM area, BANK 0: location 0to7 BANK 1: location 8to15 BANK 2: location 16to23 BANK 4: location 24to 31.
Only one of these banks may be enabled at the same time.
The next 16 bytes, locations 32 through 45, contains
128 directly addressable bit locations.
The stack can be located anywhere in the internal MAIN
RAM address space. The stack depth is only limited by the
internal RAM space available. All registers except the
program counter and the four 8-bit register banks reside in
the SFR address space.
7.3 External Data Memory
An access to external Data Memory locations higher than
255 will be performed with the MOVX @DPTR instructions
in the same way as in the 80C51 structure,
i.e. with P0 and P2 as data/address bus and P3.6 and P3.7
as Write and Read strobe signals.
Note that these external Data Memory locations cannot be
accessed with R0 or R1 as address pointer.
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592 I/O PORT STRUCTURE
The P8xC592 has six 8-bit parallel ports: Port0to Port 5. In addition to the standard 8-bit parallel ports, the I/O facilities
also include a number of special I/O lines. The use of a Port 1, Port 3 or Port 4 pins as an alternative function is carried
out automatically provided the associated SFR bit is set HIGH.
Table 5 Default Port functions
Table 6 Alternative Port functions
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
Notes to the alternative Port functions Port lines P1.6 and P1.7 may be selected as CTX0 and CTX1 outputs of the serial port SIO1 (CAN).
After reset P1.6 and P1.7 may be used as normal I/O ports, if the CAN interface is not used. Unused analog inputs can be used as digital inputs. As Port 5 lines may be used as inputs to the ADC, these digital
inputs have an inherent hysteresis to prevent the input logic from drawing too much current from the power lines
when driven by analog signals.
Channel-to-channel crosstalk should be taken into consideration when both digital and analog signals are
simultaneously input to Port 5 (see Chapter 20). PULSE WIDTH MODULATED OUTPUTS (PWM)
Two Pulse Width Modulated (PWM) output channels are
available with the P8xC592. These channels provide
output pulses of programmable length and interval.
The repetition frequency is defined by an 8-bit prescaler
PWMP which generates the clock for the counter.
Both the prescaler and counter are common to both PWM
channels. The 8-bit counter counts modulo 255 i.e. fromto 254 inclusive. The value of the 8-bit counter is
compared to the contents of two registers:
PWM0 and PWM1.
Provided the contents of either of these registers is greater
than the counter value, the output of PWM0 or PWM1 is
set LOW. If the contents of these register are equal to, or
less than the counter value, the output will be HIGH. The
pulse-width-ratio is therefore defined by the contents of the
register PWM0 and PWM1. The pulse-width-ratio is in the
range of 0to 255 ⁄255 and may be programmed in
increments of1 ⁄255.
The repetition frequency fPWM, at the PWMn outputs is
given by:
When using an oscillator frequency of 16 MHz, for
example, the above formula would give a repetition
frequency range of 123Hzto 31.4 kHz.
By loading the PWM registers with either 00H or FFH, the
PWM outputs can be retained at a constant HIGH or LOW
level respectively. When loading FFH to the PWM
registers, the 8-bit counter will never actually reach this
(FFH) value.
Both output pins PWMn are driven by push-pull drivers,
and are not shared with any other function. PWM CLK PWMP 1+()× 255× --------------------------------------------------------------=
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
9.1 Prescaler frequency control register (PWMP)
Table 7 Prescaler frequency control register (address FEH)
Table 8 Description of PWMP bits
9.2 Pulse Width Register 0 (PWM0)
Table 9 Pulse Width Register (address FCH)
Table 10 Description of PWM0 bits
9.3 Pulse Width Register 1 (PWM1)
Table 11 Pulse width register (address FDH)
Table 12 Description of PWM1 bits
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Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592 ANALOG-TO-DIGITAL CONVERTER (ADC)
The analog input circuitry consists of an 8-input analog
multiplexer and an ADC with 10-bit resolution. The analog
reference voltage and analog power supplies are
connected via separate input pins. The conversion takes
50 machine cycles i.e. 37.5 μs at 16 MHz oscillator
frequency. The input voltage swing is from 0Vto AVDD.
The ADC is controlled using the ADCON control register.
Register bits ADCON.0to ADCON.2 select the input
channels of the analog multiplexer (see Fig.10).
The completion of the 10-bit analog-to-digital conversion is
flagged by ADCI in the ADCON register and the result is
stored in the SFR ADCH (upper 8-bits) and the 2 lower bits
(ADC.1 and ADC.0) in register ADCON.
An analog-to-digital conversion in progress is unaffected
by an external or software ADC start. The result of a
completed conversion remains unchanged provided
ADCI= HIGH. While ADCI or ADCS are HIGH, a new ADC
START will be blocked and consequently lost. An
analog-to-digital conversion already in progress is aborted
when the Idle or Power-down mode is entered.
The result of a completed conversion (ADCI= HIGH)
remains unaffected during the Idle mode.
The LOW-to-HIGH transition of STADC is recognized at
the end of a machine cycle and the conversion
commences at the beginning of the next cycle. When a
conversion is initiated by software, the conversion starts at
the beginning of the machine cycle following the
instruction that sets ADCS.
The next two machine cycles are used to initiate the
converter. At the end of this first cycle, the ADCS status
flag is set to HIGH while the conversion is in progress.
Sampling of the analog input commences at the end of the
second cycle.
During the next eight machine cycles, the voltage at the
previously selected pin of Port 5 is sampled and this input
voltage should be stable in order to obtain a useful sample.
In any case, the input voltage slew rate must be less than V/ms (5 V conversion range) in order to prevent an
undefined result. The conversion takes four machine
cycles per bit.
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
10.1 ADC Control register (ADCON)
Table 13 ADC Control register (address C5H)
Table 14 Description of the ADCON bits
Table 15 ADCI and ADCS operating modes
If ADCI is cleared by software while ADCS is set at the same time a new analog-to-digital conversion with the same
channel-number may be started. It is recommended to reset ADCI before ADCS is set.
Note Start of a new conversion requires ADCI=0.
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Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592 TIMERS/COUNTERS
The P8xC592 contains: Three 16-bit timer/event counters:
Timer 0, Timer 1 and TimerT2 One 8-bit timer, T3 (Watchdog WDT).
11.1 Timer 0 and Timer 1
Timer 0 and Timer 1 may be programmed to carry out the
following functions: Measure time intervals and pulse durations Count events Generate interrupt requests.
Timer 0 and Timer 1 can be programmed independently to
operate in 3 modes:
Mode 0 8-bit timer or 8-bit counter each with divide-by-32
prescaler.
Mode 1 16-bit timer-interval or event counter.
Mode 2 8-bit timer-interval or event counter with
automatic reload upon overflow.
Timer 0 can be programmed to operate in an additional
mode as follows:
Mode 3 one 8-bit time-interval or event counter and one
8-bit timer-interval counter.
When Timer 0 is in Mode 3, Timer 1 can be programmed
to operate in Modes 0, 1 or 2 but cannot set an interrupt
flag or generate an interrupt. However, the overflow from
Timer 1 can be used to pulse the Serial Port baud-rate
generator.
The frequency handling range of these counters with a MHz crystal is as follows: In the timer function, the timer is incremented at a
frequency of 1.33 MHz (1 ⁄12 of the oscillator frequency)0 Hz to an upper limit of 0.66 MHz (1 ⁄24 of the oscillator
frequency) when programmed for external inputs.
Both internal and external inputs can be gated to the
counter by a second external source for directly measuring
pulse durations. When configured as a counter, the
register is incremented on every falling edge on the
corresponding input pin, T0 or T1.
The earliest moment, when the incremented register value
can be read is during the second machine cycle following
the machine cycle within which the incrementing pulse
occurred.The counters are started and stopped under
software control. Each one sets its interrupt request flag
when it overflows from all HIGHs to all LOWs
(or automatic reload value), with the exception of Mode 3
as previously described.
11.2 Timer T2 Capture and Compare Logic
Timer T2 is a 16-bit timer/counter which has capture and
compare facilities (see Fig.11).
The 16-bit timer/counter is clocked via a prescaler with a
programmable division factor of 1, 2, 4 or 8. The input of
the prescaler is clocked with1 ⁄12 of the oscillator
frequency, or by an external source connected to the T2
input, or it is switched off. The maximum repetition rate of
the external clock source is1 ⁄12fCLK, twice that of Timer 0
and Timer 1. The prescaler is incremented on a rising
edge. It is cleared if its division factor or its input source is
changed, or if the timer/counter is reset.
T2 is readable ‘on the fly’, without any extra read latches;
this means that software precautions have to be taken
against misinterpretation at overflow from least to most
significant byte while T2 is being read. T2 is not loadable
and is reset by the RST signal or at the positive edge of the
input signal RT2, if enabled. In the Idle mode the
timer/counter and prescaler are reset and halted.
T2 is connected to four 16-bit Capture Registers: CT0,
CT1, CT2 and CT3. A rising or falling edge on the inputs
CT0I, CT1I, CT2I or CT3I (alternative function of Port1)
results in loading the contents of T2 into the respective
Capture Registers and an interrupt request.
Using the Capture Register CTCON, these inputs may
invoke capture and interrupt request on a positive edge, a
negative edge or on both edges. If neither a positive nor a
negative edge is selected for capture input, no capture or
interrupt request can be generated by this input.
The contents of the Compare Registers CM0, CM1 and
CM2 are continually compared with the counter value of
Timer T2. When a match occurs, an interrupt may be
invoked. A match of CM0 sets the bits 0to 5 of Port 4, a
CM1 match resets these bits and a CM2 match toggles bits
6 and 7 of Port 4, provided these functions are enabled by
the STE/RTE registers. A match of CM0 and CM1 at the
same time results in resetting bits 0to 5 of Port 4. CM0,
CM1 and CM2 are reset by the RST signal.
Port 4 can be read and written by software without
affecting the toggle, set and reset signals. At a byte
overflow of the least significant byte, or at a 16-bit overflow
of the timer/counter, an interrupt sharing the same
interrupt vector is requested. Either one or both of these
overflows can be programmed to request an interrupt.
All interrupt flags must be reset by software.
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
11.2.1 COUNTER CONTROL REGISTER (TM2CON)
Table 16 Counter Control register (address EAH)
Table 17 Description of the TM2CON bits
Table 18 Timer 2 prescaler select
Table 19 Timer 2 mode select
11.2.2 CAPTURE CONTROL REGISTER (CTCON)
Table 20 Capture Control register (address EBH)
Table 21 Description of the CTCON bits
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Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
11.2.3 TIMER INTERRUPT FLAG REGISTER (TM2IR)
Table 22 Timer Interrupt Flag register (address C8H)
Table 23 Description of the TM2IR bits (see notes 1 and 2)
Notes Interrupt Enable IEN1 is used to enable/disable Timer 2 interrupts (see Section 14.1.2). Interrupt Priority Register IP1 is used to determine the Timer 2 interrupt priority (see Section 14.1.4).
11.2.4 SET ENABLE REGISTER (STE)
Table 24 Set Enable register (address EEH)
Table 25 Description of the STE bits (see notes 1 and 2)
Notes If STE.n is LOW then P4.n is not affected by a match of CM0 and T2 (n=0,1,2,3,4,5). STE.6 and STE.7 are read only.
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Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
11.2.5 RESET/TOGGLE ENABLE REGISTER (RTE)
Table 26 Reset/Toggle Enable register (address EFH)
Table 27 Description of the RTE bits (note 1)
Note If RTE.n is LOW then P4.n is not affected by a match of CM1 and T2 or CM2 and T2.
For more information, refer to the 8051-based “8-bit Microcontrollers Data Handbook IC20”.
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Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
11.3 Watchdog Timer (T3)
In addition to Timer T2 and the standard timers (Timer0
and Timer 1), a Watchdog Timer (WDT) comprising an
11-bit prescaler and an 8-bit timer (T3) is also provided
(see Fig.12).
The timer T3 is incremented every 1.5 ms, derived from
the oscillator frequency of 16 MHz by the following
formula:
When a timer T3 overflow occurs, the microcontroller is
reset and a reset-output-pulse is generated at pin RST.
This short output pulse (3 machine cycles) may be
suppressed if the RST pin is connected to a capacitor.
To prevent a system reset (by an overflow of the WDT), the
user program has to reload T3 within periods that are
shorter than the programmed Watchdog time interval.
If the processor suffers a hardware/software malfunction,
the software will fail to reload the timer. This failure will
produce a reset upon overflow thus preventing the
processor running out of control. timer CLK 2048× --------------------------=
The Watchdog Timer can only be reloaded if the condition
flag WLE= PCON.4 has been previously set by software.
At the moment the counter is loaded the condition flag is
automatically cleared.
The timer interval between the timer's reloading and the
occurrence of a reset depends on the reloaded value. For
example, this may range from 1.5 msto 0.375 s when
using an oscillator frequency of 16 MHz.
In the Idle state the Watchdog Timer and reset circuitry
remain active.
The Watchdog Timer (WDT) is controlled by the Enable
Watchdog pin (EW) (see Table 28).
Table 28 EW controlling WDT and Power-down mode
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592 SERIAL I/O PORT: SIO0 (UART)
The Serial Port SIO0 is a full duplex (UART) serial I/O port
i.e. it can transmit and receive simultaneously. This Serial
Port is also receive-buffered. It can commence reception
of a second byte before the previously received byte has
been read from the receive register. However, if the first
byte has still not been read by the time reception of the
second byte is complete, one of these (first or second)
bytes will be lost. The SIO0 receive and transmit registers
are both accessed via the S0BUF SFR. Writing to S0BUF
loads the transmit register, and reading S0BUF accesses
to a physically separate receive register. SIO0 can operate
in 4 modes:
Mode 0 Serial data is transmitted and received through
RXD. TXD outputs the shift clock. 8 data bits are
transmitted/received (LSB first). The baud rate is
fixed at1 ⁄12 of the oscillator frequency.
Mode 1 10 bits are transmitted via TXD or received
through RXD: a start bit (0), 8 data bits (LSB first),
and a stop bit (1). On receive, the stop bit is put
into RB8 of the S0CON SFR. The baud rate is
variable.
Mode 2 11 bits are transmitted through TXD or received
through RXD: a start bit (0), 8 data bits (LSB first),
a programmable 9th data bit, and a stop bit (1).
On transmit, the 9th data bit (TB8 in S0CON) can
be assigned the value of 0 or 1. With nominal
software, TB8 can be the parity bit (P in PSW).
During a receive, the 9th data bit is stored in RB8
(S0CON), and the stop bit is ignored. The baud
rate is programmable to either1 ⁄32 or1 ⁄64 of the
oscillator frequency.
Mode 3 11 bits are transmitted through TXD or received
through RXD: a start bit (0), 8 data bits (LSB first),
a programmable 9th data bit, and a stop bit (1).
Mode 3 is the same as Mode 2 except for the
baud rate which is variable in Mode3.
In all four modes, transmission is initiated by any
instruction that writes to the S0BUF SFR.
Reception is initiated in Mode 0 when RI= 0 and REN=1.
In the other three modes, reception is initiated by the
incoming start bit provided that REN=1.
Modes 2 and 3 are provided for multiprocessor
communications. In these modes, 9 data bits are received
with the 9th bit written to RB8 (S0CON). The 9th bit is
followed by the stop bit. The port can be programmed so
that with receiving the stop bit, the Serial Port interrupt will
be activated if, and only if RB8=1.
This feature is enabled by setting bit SM2 in S0CON. This
feature may be used in multiprocessor systems.
For more information about how to use the UART in
combination with the registers S0CON, PCON, IE, SBUF
and the Timer register, refer to the 8051-based
“8-bit Microcontrollers Data Handbook IC20”. SERIAL I/O PORT: SIO1 (CAN)
SIO1 (CAN) provides the CAN (Controller Area Network)
serial-bus data communication interface. SIO1 (CAN)
replaces the SIO1 (I2 C) serial interface as provided in the
microcontroller derivative P8xC552.
13.1 On-chip CAN-controller
CAN is the definition of a high performance
communication protocol for serial data communication.
The P8xC592 on-chip CAN-controller is a full
implementation of the CAN 2.0A protocol. With the
P8xC592 powerful local networks can be built, both for
automotive and general industrial environments. This
results in a much reduced wiring harness and enhanced
diagnostic and supervisory capabilities.
13.2 CAN Features Multi-master architecture Bus access priority determined by the message
identifier 2032 message identifier (211 standard frame CAN 2.0A) Guaranteed latency time for high priority messages Powerful error handling capability Data length from 0upto8 bytes Multicast and broadcast message facility Non destructive bit-wise arbitration Non-return-to-zero (NRZ) coding/decoding with
bit-stuffing Programmable transfer rate (up to 1 Mbit/s) Programmable output driver configuration Suitable for use in a wide range of networks including
the SAE's network classes A, B and C DMA providing high-speed on-chip data exchange Bus failure management facility1 ⁄2AVDD reference voltage.
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
13.3 Interface between CPU and CAN
The internal interface between the P8xC592's CPU and
on-chip CAN-controller is achieved via the following four
SFRs (see Fig.13): CANADR, to point to a register of the CAN-controller CANDAT, to read or write data CANCON, to read interrupt flags and to write commands CANSTA, to read status information and to write DMA
pointer.
Additionally, the DMA-logic allows a high-speed data
exchange between the CAN-controller and the CPU's
on-chip MAIN RAM. For more information, see
Section 13.5.15 “Handling of the CPU-CAN interface”.
13.4 Hardware blocks of the CAN-controller
The P8xC592 CAN-controller contains all necessary
hardware for high performance serial network
communications (see Fig.14 and Table 29).
It controls the communication flow through the area
network using the CAN-protocol. The CAN-controller
meets the following automotive requirements: Short message length Bus access priority, determined by the message
identifier Powerful error handling capability Configuration flexibility to allow area network expansion Guaranteed latency time for urgent messages; The latency time defines the period between the
initiation (Transmission Request) and the start of the
transmission on the bus. The latency time strongly
depends on a large variety of bus-related conditions.
In the case of a message being transmitted on the
bus and one distortion, the latency time can be up to
149 bit times (worst case). For more information see
Chapter 22 “CAN application information”.
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
Table 29 Hardware blocks of the CAN-controller (see Fig.14)
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
13.5 Control Segment and Message Buffer
description
The CAN-controller appears to the CPU as a
memory-mapped peripheral, guaranteeing the
independent operation of both parts.
13.5.1 ADDRESS ALLOCATION
The address area of the CAN-controller consists of the
Control Segment and the message buffers. The Control
Segment is programmed during an initialization down-load
in order to configure communication parameters (e.g. bit
timing). The communication over the CAN-bus is also
controlled via this segment by the CPU. A message which
is to be transmitted, must be written to the Transmit Buffer.
After a successful reception the CPU may read the
message from the Receive Buffer and then release it for
further use.
13.5.2 CONTROL SEGMENT LAYOUT
The exchange of status, control and command signals
between the CPU and the CAN-controller is performed in
the control segment. The layout of this segment is shown
in Fig.15. After an initial down-load, the contents of the
registers Acceptance Code, Acceptance Mask,
Bus Timing 0, Bus Timing 1 and Output Control should not
be changed. These registers may only be accessed when
the Reset Request bit in the Control Register is set HIGH
(see Tables 30, 31 and 32).
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
Table 30 CPU/CAN Register map
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
Note The Test Register is used for production testing only.
13.5.3 CONTROL REGISTER (CR)
The contents of the Control Register are used to change the behaviour of the CAN-controller. Control bits may be set or
reset by the CPU which uses the Control Register as a read/write memory.
Table 31 Control Register (address0)
Table 32 Description of the CR bits
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8-bit microcontroller with on-chip CAN P8xC592
Notes to the description of the CR bits The test mode is intended for factory testing and not for customer use. A modification of the bits Reference Active and Sync is only possible with Reset Request= HIGH (present). It is
allowed to set these bits while Reset Request is changed from a HIGH level to a LOW level. After an external reset
(pin RST= HIGH) the Reference Active bit is set HIGH (output), the Sync bit is undefined. During an external reset (RST= HIGH) or when the Bus Status bit is set HIGH (Bus-OFF), the IML forces the
Reset Request HIGH (present). After the Reset Request bit is set LOW (absent) the CAN-controller will wait for: One occurrence of the Bus-Free signal (11 recessive bits, see Section 13.6.9.6), if the preceding reset (Reset
Request= HIGH) has been caused by an external reset or a CPU initiated reset. 128 occurrences of Bus-Free, if the preceding reset (Reset Request= HIGH) has been caused by a
CAN-controller initiated Bus-OFF, before re-entering the Bus-On mode, see Section 13.6.9. When Reset Request is set HIGH (present), for whatever reason, the Control, Command, Status and Interrupt
bits are affected, see Table 40. The registers at addresses 4to 8 are only accessible when the Reset Request is
set HIGH (present).
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
13.5.4 COMMAND REGISTER (CMR)
A command bit initiates an action within the transfer layer of the CAN-controller. The Command Register appears to the
CPU as a read/write memory, except for the bits CMR.0 (TR)to CMR.3 (COS), which return a HIGH if being read.
Table 33 Command Register (address1)
Table 34 Description of the CMR bits
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Notes to the description of the CMR bits The RX0/RX1 Active bits, if being read, reflect the status of the respective switches (see Fig.16). It is recommended
to change the switches only during the reset state (Reset Request= HIGH). The Wake-Up Mode bit should be set at the same time as the Sleep bit. The differential wake up mode is useful if
both bus wires are fully functioning; it minimizes the amount of wake ups due to noise. The single ended wake up
mode is recommended if a wake up must be possible even if one bus wire is already or may become disturbed
(see Fig.16). The CAN-controller will enter sleep mode, if the Sleep bit is set HIGH (sleep) there is no bus activity and no interrupt
is pending. The CAN-controller will wake up after the Sleep bit is set LOW (wake up) or when there is bus activity.
On wake up, a Wake-Up Interrupt (see Section 13.5.6) is generated (see also Chapter 15). A CAN-controller which
is sleeping and then awaken by bus activity will not be able to receive this message until it detects a Bus-Free signal
(see Section 13.6.9.6). The Sleep bit, if read, reflects the status of the CAN-controller. This command bit is used to acknowledge the Data Overrun condition signalled by the Data Overrun status bit.
Command is given only after releasing both receive buffers. The stored messages have to be rejected. The
command bit is set simultaneously with setting of the Release Receive Buffer command bit the second time. After reading the contents of the Receive Buffer (RBF0 or RBF1) the CPU must release this buffer by setting Release
Receive Buffer bit HIGH (released). This may result in another message becoming immediately available.
To prevent the RRB command being executed only once, the minimum wait time between two successive RRB
commands is 3 system clock cycles (tSCL, see Section 13.5.9). The Abort Transmission bit is used when the CPU requires the suspension of the previously requested transmission,
e.g. to transmit an urgent message. A transmission already in progress is not stopped. In order to see if the original
message had been either transmitted successfully or aborted, the Transmission Complete Status bit should be
checked. This should be done after the Transmit Buffer Access bit has been set HIGH (released) or a Transmit
Interrupt has been generated (see Section 13.5.6). If the Transmission Request bit was set HIGH in a previous command, it cannot be cancelled by setting the
Transmission Request bit LOW (absent). Cancellation of the requested transmission may be performed by setting
the Abort Transmission bit HIGH (present).
Table 35 Combination of bits RX0A and RX1A (see Fig.16)
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
13.5.5 STATUS REGISTER (SR)
The contents of the Status Register reflects the status of the CAN-controller. The Status Register appears to the CPU
as a read only memory.
Table 36 Status Register (address2)
Table 37 Description of the SR bits
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8-bit microcontroller with on-chip CAN P8xC592
Notes to the description of the SR bits When the Bus Status bit is set HIGH (Bus-OFF), the CAN-controller will set the Reset Request bit HIGH (present).
It will stay in this state until the CPU sets the Reset Request bit LOW (absent). Once this is completed the
CAN-controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) before setting
the Bus Status bit LOW (Bus-ON), the Error Status bit LOW (ok) and resetting the Error Counters. During Bus-OFF
the output drivers are switched off (floating); external transceiver circuits should output a recessive level in this case. If both the Receive Status and Transmit Status bits are LOW (idle) the CAN-bus is idle. If the CPU tries to write to the Transmit Buffer when the Transmit Buffer Access bit is LOW (locked), the written bytes
will not be accepted and will be lost without this being signalled. The Transmission Complete Status bit is set LOW
(incomplete) whenever the Transmission Request bit is set HIGH (present). If an Abort Transmission command is
issued, the Transmit Buffer will be released. If the message, which was requested and then aborted, was not
transmitted, the Transmission Complete Status bit will remain LOW. If Data Overrun= HIGH (overrun) is detected, the currently received message is dropped. A transmitted message,
granted acceptance, is also stored in a Receive Buffer. This occurs because it is not known if the CAN-controller will
lose arbitration and so become a receiver of the message. If no Receive Buffer is available, Data Overrun is
signalled. However, this transmitted and accepted message does neither cause a Receive Interrupt nor set the
Receive Buffer Status bit to HIGH (full). Also, a Data Overrun does not cause the transmission of an Overload Frame
(see Sections 13.6.1 and 13.6.5). If the command bit Release Receive Buffer is set HIGH (released) by the CPU, the Receive Buffer Status bit is set
LOW (empty) by IML. When a new message is stored in any of the receive buffers, the Receive Buffer Status bit is
set HIGH (full) again.
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
13.5.6 INTERRUPT REGISTER (IR)
The Interrupt Register allows the identification of an interrupt source. When one or more bits of this register are set, a
CAN interrupt (SI01) will be indicated to the CPU. All bits are reset by the CAN-controller after this register is read by the
CPU. This register appears to the CPU as a read only memory.
Table 38 Interrupt Register (address3)
Table 39 Description of the IR bits
Notes Overrun Interrupt bit (if enabled) and Data Overrun bit (see Section 13.5.5) are set at the same time. Receive Interrupt bit (if enabled) and Receive Buffer Status bit (see Section 13.5.5) are set at the same time.
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Table 40 Effects of setting the Reset Request bit HIGH (present)
Note Only after an external reset; see note5to Table 37 “Description of the SR bits”.
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
13.5.7 ACCEPTANCE CODE REGISTER (ACR)
The Acceptance Code Register is part of the acceptance
filter of the CAN-controller. This register can be accessed
(read/write), if the Reset Request bit is set HIGH (present).
When a message is received which passes the
acceptance test and if there is an empty Receive Buffer,
then the respective Descriptor and Data Field
(see Fig.15) are sequentially stored in this empty buffer.
In the event that there is no empty Receive Buffer, the
Data Overrun bit is set HIGH (overrun); see
Sections 13.5.5 and 13.5.6.
When the complete message has been correctly received
the following occurs: The Receive Buffer Status bit is set HIGH (full) If the Receive Interrupt Enable bit is set HIGH (enabled),
the Receive Interrupt is set HIGH (set).
During transmission of a message which passes the
acceptance test, the message is also written to its own
Receive Buffer. If no Receiver Buffer is available, Data
Overrun is signalled because it is not known at the start of
a message whether the CAN-controller will lose arbitration
and so become a receiver of the message.
Table 41 Acceptance Code Register (address4)
Table 42 Description of the ACR bits
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13.5.8 ACCEPTANCE MASK REGISTER (AMR)
The Acceptance Mask Register is part of the acceptance
filter of the CAN-controller.
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present).
The Acceptance Mask Register qualifies which of the
corresponding bits of the acceptance code are ‘relevant’ or
‘don't care’ for acceptance filtering.
Table 43 Acceptance Mask Register (address5)
Table 44 Description of the AMR bits
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13.5.9 BUS TIMING REGISTER0 (BTR0)
The contents of Bus Timing Register 0 defines the values
of the Baud Rate Prescaler (BRP) and the Synchronization
Jump Width (SJW).
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present).
For further information on bus timing, see
Sections 13.5.10 and 13.5.18.
Table 45 Bus Timing Register 0 (address6)
Table 46 Description of the BTR0 bits
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13.5.10 BUS TIMING REGISTER 1(BTR1)
The contents of Bus Timing Register 1 defines the length
of the bit period, the location of the sample point and the
number of samples to be taken at each sample point.
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present).For further information
on bus timing, see Sections 13.5.9 and 13.5.18.
Table 47 Bus Timing Register 1 (address7)
Table 48 Description of the BTR1 bits
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13.5.11 OUTPUT CONTROL REGISTER (OCR)
The Output Control Register allows, under software
control, the set-up of different output driver configurations.
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present). If the CAN-controller is
in the sleep mode (Sleep= HIGH) a recessive level is
output on the CTX0 and CTX1 pins. If the CAN-controller
is in the reset state (Reset Request= HIGH) the output
drivers are floating.
Tables 50 and 51, show the relationship between the bits
of the Output Control Register and the two serial output
pins CTX0 and CTX1 of the P8xC592 CAN-controller,
connected to the serial bus (see Fig.14).
Table 49 Output Control Register (address8)
Table 50 Description of the OCR bits
Table 51 Description of the Output Mode bits
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Table 52 Output pin set-up
Notes TPx is the on-chip output transistor x, connected to VDD; x=0or1. TNx is the on-chip output transistor x, connected to CVSS; x=0or1. CTXx is the serial output level on CTX0 or CTX1. It is required that the output level on the CAN-bus is dominant with
TXD= 0 and recessive with TXD= 1, see Section 13.6.1.1 “Bit representation”.
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
13.5.12 TEST REGISTER (TR)
The Test Register is used for production testing only.
Table 53 Test Register (address9)
13.5.13 TRANSMIT BUFFER LAYOUT
The global layout of the Transmit Buffer is shown in Fig.15. This buffer serves to store a message from the CPU to be
transmitted by the CAN-controller. It is subdivided into Descriptor and Data Field. The Transmit Buffer can be written to
and read from by the CPU.
13.5.13.1 Descriptor
Table 54 Descriptor Byte 1 Register (DSCR1, address 10)
Table 55 Descriptor Byte 2 Register (DSCR2, address 11)
Table 56 Description of the ID.n bits in DSCR1 and DSCR2
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Table 57 Description of the other DSCR2 bits
13.5.13.2 Data Field
The number of transferred data bytes is determined by the
Data Length Code. The first bit transmitted is the most
significant bit of data byte 1 at address 12.
13.5.14 RECEIVE BUFFER LAYOUT
The layout of the Receive Buffer and the individual bytes
correspond to the definitions given for the Transmit Buffer
layout, except that the addresses start at 20 instead of 10
(see Fig.15).
13.5.15 HANDLINGOF THE CPU-CAN INTERFACE
Via the four special registers CANADR, CANDAT,
CANCON and CANSTA the CPU has access to the
CAN-controller and also to the DMA-logic. Note that
CANCON and CANSTA have different meanings for a
Read and Write access.
Table 58 The SFRs between CPU and CAN
Reserved bits are read as HIGH. R = Read; W= Write; R/W= Read/Write.
Philips Semiconductors Product specification
8-bit microcontroller with on-chip CAN P8xC592
13.5.15.1 Special Function Register CANADR
CANADR is implemented as a read/write register.
Table 59 SFR CANADR (address DBH)
Table 60 Description of the CANADR bits
13.5.15.2 Special Function Register CANDAT
CANDAT is implemented as a read/write register.
Table 61 SFR CANDAT (address DAH)
Table 62 Description of the CANADR bits
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13.5.15.3 Special Function Register CANCON
Table 63 SFR CANCON in Read access (address D9H)
Table 64 Description of the CANCON bits in Read access
When reading CANCON the Interrupt Register of the CAN-controller is accessed.
Table 65 SFR CANCON in Write access (address D9H)
Table 66 Description of the CANCON bits in Write access
When writing to CANCON then the Command Register of the CAN-controller is accessed.
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8-bit microcontroller with on-chip CAN P8xC592
13.5.15.4 Special Function Register CANSTA
CANSTA is implemented as a bit-addressable read/write register.
The bit addresses of CANSTA (7to 0) are DFHto D8H.
Table 67 SFR CANCON in Read access (address DFHto D8H)
Table 68 Description of the CANCON bits in Read access
When reading CANSTA the Status Register of the CAN-controller is accessed.
Table 69 SFR CANCON in Write access (address DFHto D8H)
Table 70 Description of the CANSTA bits in Write access
Writing to CANSTA sets the address of the on-chip MAIN RAM (internal Data Memory) for a subsequent DMA transfer.
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13.5.16 AUTO ADDRESS INCREMENT
With the Auto Address Increment mode a fast stack-like
reading and writing of CAN-controller internal registers is
provided. If the bit CANADR.5 (AutoInc) is HIGH, the
content of CANADR is incremented automatically after any
read or write access to CANDAT. For instance, loading a
message into the Transmit Buffer can be done by writing
2AH into CANADR and then moving byte by byte of the
message to CANDAT. Incrementing CANADR beyond
XX111111B resets the bit CANADR.5 (AutoInc)
automatically (CANADR= XX000000B).
13.5.17 HIGH SPEED DMA
The DMA-logic allows you to transfer a complete message
(up to 10 bytes) between CAN-controller and MAIN RAM
in 2 instruction cycles at maximum; up to 4 bytes are
transferred in 1 instruction cycle. The performance of the
CPU is strongly enhanced because this very fast transfer
is carried out in the background.
A DMA transfer is achieved by first writing the RAM
address (00Hto FFH) into CANSTA and then setting the
TX-or RX-Buffer address in CANDR and the bit
CANADR.7 (DMA) simultaneously; the RAM address
points to the location of the first byte to be transferred.
Setting the DMA bit causes an automatic evaluation of the
Data Length Code and then the transfer; for a TX-DMA
transfer the Data Length Code is expected at the location
‘RAM address +1’.
In order to program a TX-DMA transfer the value 8AH
(address 10) has to be written into CANADR. Then a
complete message, consisting of the 2-byte Descriptor
and the Data Field (0to8 bytes), starting at location
‘RAM address’ is transferred to the TX-Buffer.
The RX-DMA transfer is very versatile. By writing a value
in the range of 94H (address 20) up to 9DH (address 29)
into CANADR the whole or a part of the received message,
starting at the specified address, is transferred to the
internal Data Memory. This allows e.g. to transfer the bytes
of the Data Field only.
After a successful DMA transfer the DMA-bit is reset.
During a DMA transfer the CPU can process the next
instruction. However, an access to the Data Memory,
CANADR, CANDAT, CANCON or CANSTA is not allowed.
After having set the DMA-bit, every interrupt is disabled
until the end of the transfer. Note, that disadvantageous
programming may lead to an interrupt response time of at
most 10 instruction cycles. The shortest interrupt response
time is achieved by using 2 consecutive 1-cycle
instructions directly after setting the DMA-bit.
During the reset state (bit Reset Request is HIGH) a DMA
transfer is not possible.
13.5.18 BUS TIMING/SYNCHRONIZATION
The Bus Timing Logic (BTL) monitors the serial bus-line
via the on-chip input comparator and performs the
following functions (see Section 13.4): Monitors the serial bus-line level Adjusts the sample point, within a bit period
(programmable) Samples the bus-line level using majority logic
(programmable, 1 or 3 samples) Synchronization to the bit stream: hard synchronization at the start of a message resynchronization during transfer of a message.
The configuration of the BTL is performed during the
initialization of the CAN-controller. The BTL uses the
following three registers: Control Register (Sync) Bus Timing Register 0 Bus Timing Register 1.
13.5.19 BIT TIMING
A bit period is built up from a number of system clock
cycles (tSCL), see Section 13.5.9.
One bit period is the result of the addition of the
programmable segments TSEG1 and TSEG2 and the
general segment SYNCSEG.
13.5.19.1 Synchronization Segment (SYNCSEG)
The incoming edge of a bit is expected during this state;
this state corresponds to one system clock cycle (1× tSCL).
Philips Semiconductors Product specification
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13.5.19.2 Time Segment 1 (TSEG1)
This segment determines the location of the sampling
point within a bit period, which is at the end of TSEG1.
TSEG1 is programmable from 1to 16 system clock cycles
(see Section 13.5.10).
The correct location of the sample point is essential for the
correct functioning of a transmission. The following points
must be taken into consideration: A Start-Of-Frame (see Section 13.6.2) causes all
CAN-controllers to perform a ‘hard synchronization’
(see Section 13.5.20) on the first recessive-to-dominant
edge.
During arbitration, however, several CAN-controllers
may simultaneously transmit. Therefore it may require
twice the sum of bus-line, input comparator and the
output driver delay times until the bus is stable.
This is the propagation delay time. To avoid sampling at an incorrect position, it is
necessary to include an additional synchronization
buffer on both sides of the sample point.
The main reasons for incorrect sampling are: Incorrect synchronization due to spikes on the
bus-line Slight variations in the oscillator frequency of each
CAN-controller in the network, which results in a
phase error. Time Segment 1 consists of the segment for
compensation of propagation delays and the
synchronization buffer segment directly before the
sample point (see Fig.18).
Philips Semiconductors Product specification
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13.5.19.3 Time Segment 2 (TSEG2)
This time segment provides: Additional time at the sample point for calculation of the
subsequent bit levels (e.g. arbitration) Synchronization buffer segment directly after the
sample point.
TSEG2 is programmable from 1to 8 system clock cycles
(see Section 13.5.10).
13.5.19.4 Synchronisation Jump Width (SJW)
SJW defines the maximum number of clock cycles (tSCL) a
period may be reduced or increased by one
resynchronization. SJW is programmable from 1to4
system clock cycles, see Section 13.5.2.
13.5.19.5 Propagation Delay Time (tprop)
The Propagation Delay Time is:
tprop is rounded up to the nearest multiple of tSCL.
13.5.19.6 Bit Timing Restrictions
Restrictions on the configuration of the bit timing are based
on internal processing. The restrictions are: tTSEG2 ≥ 2tSCL tTSEG2 ≥ tSJW tTSEG1 ≥ tSEG2 tTSEG1 ≥ tSJW + tprop.
The three sample mode (SAM= HIGH) has the effect of
introducing a delay of one system clock cycle on the
bus-line. This must be taken into account for the correct
calculation of TSEG1 and TSEG2: tTSEG1 ≥ tSJW + tprop + 2tSCL tTSEG2 ≥ 3tSCL.
13.5.20 SYNCHRONIZATION
Synchronization is performed by a state machine which
compares the incoming edge with its actual bit timing and
adapts the bit timing by hard synchronization or
resynchronization. prop 2 physical bus delay
input comparator delay
output driver delay
This type of synchronization occurs only at the beginning
of a message.
The CAN-controller synchronizes on the first incoming
recessive-to-dominant edge of a message (being the
leading edge of a message's Start-Of-Frame bit;
see Section 13.6.2.
Resynchronization occurs during the transmission of a
message's bit stream to compensate for: Variations in individual CAN-controller oscillator
frequencies Changes introduced by switching from one transmitter
to another (e.g. during arbitration).
As a result of resynchronization either tTSEG1 may be
increased by up to a maximum of tSJW or tTSEG2 may be
decreased by up to a maximum of tSJW: tTSEG1 ≤ tSCL [(TSEG1 + 1) + (SJW + 1)] tTSEG2 ≥ tSCL [(TSEG2 + 1) − (SJW + 1)].
TSEG1, TSEG2 and SJW are the programmed numerical
values.
The phase error (e) of an edge is given by the position of
the edge relative to SYNCSEG, measured in system clock
cycles (tSCL).
The value of the phase error is defined as:e= 0, if the edge occurs within SYNCSEGe> 0, if the edge occurs within TSEG1e< 0, if the edge occurs within TSEG2.
The effect of resynchronization is: The same as that of a hard synchronization, if the
magnitude of the phase error (e) is less or equal to the
programmed value of tSJW To increase a bit period by the amount of tSJW, if the
phase error is positive and the magnitude of the phase
error is larger than tSJW To decrease a bit period by the amount of tSJW, if the
phase error is negative and the magnitude of the phase
error is larger than tSJW.
Philips Semiconductors Product specification
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13.5.20.1 Synchronization Rules
The synchronization rules are as follows: Only one synchronization within one bit time is used. An edge is used for synchronization only if the value
detected at the previous sample point differs from the
bus value immediately after the edge. Hard synchronization is performed whenever there is a
recessive-to-dominant edge during Bus-Idle
(see Section 13.6.6). All other edges (recessive-to-dominant and optionally
dominant-to recessive edges if the Sync bit is set HIGH
(see Section 13.5.3) which are candidates for
resynchronization will be used with the following
exception: A transmitting CAN-controller will not perform a
resynchronization as a result of a
recessive-to-dominant edge with positive phase
error, if only these edges are used for
resynchronization. This ensures that the delay times
of the output driver and input comparator do not
cause a permanent increase in the bit time.
13.6 CAN 2.0A Protocol description
13.6.1 FRAME TYPES
The P8xC592's CAN-controller supports the four different
CAN-protocol frame types for communication: Data Frame, to transfer data Remote Frame, request for data Error Frame, globally signal a (locally) detected error
condition Overload Frame, to extend delay time of subsequent
frames (an Overload Frame is not initiated by the
P8xC592 CAN-controller).
13.6.1.1 Bit representation
There are two logical bit representations used in the
CAN-protocol: A recessive bit on the bus-line appears only if all
connected CAN-controllers send a recessive bit at that
moment. Dominant bits always overwrite recessive bits i.e. the
resulting bit level on the bus-line is dominant.
13.6.2 DATA FRAME
A Data Frame carries data from a transmitting
CAN-controller to one or more receiving ones.
A Data Frame is composed of seven different bit-fields: Start-Of-Frame Arbitration Field Control Field Data Field (may have a length of zero) CRC Field (CRC= Cyclic Redundancy Code) Acknowledge Field End-Of-Frame.
13.6.2.1 Start-Of-Frame bit
Signals the start of a Data Frame or Remote Frame.
It consists of a single dominant bit use for hard
synchronization of a CAN-controller in receive mode.
13.6.2.2 Arbitration Field
Consists of the message Identifier and the RTR bit. In the
case of simultaneous message transmissions by two or
more CAN-controllers the bus access conflict is solved by
bit-wise arbitration, which is active during the transmission
of the Arbitration Field.
13.6.2.3 Identifier
This 11-bit field is used to provide information about the
message, as well as the bus access priority. It is
transmitted in the order ID.10to ID.0 (LSB). The situation
that the seven most significant bits (ID.10to ID.4) are all
recessive must not occur.
An Identifier does not define which particular
CAN-controller will receive the frame because a CAN
based communication network does not differentiate
between a point-to-point, multicast or broadcast
communication.
