P87C660X2FA ,80C51 8-bit microcontroller family 16KB OTP/ROM, 512B RAM low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHZ), two 400KB I2C interfacesINTEGRATED CIRCUITSP83C660X2, P87C660X2P83C661X2, P87C661X280C51 8-bit microcontroller family16KB O ..
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P87C660X2FA
80C51 8-bit microcontroller family 16KB OTP/ROM, 512B RAM low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHZ), two 400KB I2C interfaces
Product data
Supersedes data of 2003 Jun 19 2003 Oct 02
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM,
512B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz), two 400KB I2 C interfaces
DESCRIPTIONThe devices are Single-Chip 8-Bit Microcontrollers manufactured in
an advanced CMOS process and are derivatives of the 80C51
microcontroller family. The instruction set is 100% compatible with
the 80C51 instruction set.
The devices support 6-clock/12-clock mode selection by
programming an OTP bit (OX2) using parallel programming. In
addition, an SFR bit (X2) in the clock control register (CKCON)
also selects between 6-clock/12-clock mode.
These devices have either one or two I2C interfaces, capable of
handling speeds up to 400 kbits/s (Fast I2C). They also have four
8-bit I/O ports, three 16-bit timer/event counters, a multi-source,
four-priority-level, nested interrupt structure, an enhanced UART and
on-chip oscillator and timing circuits.
The added features of the P8xC66xX2 make it a powerful
microcontroller for applications that require pulse width modulation,
high-speed I/O, I2C communication, and up/down counting
capabilities such as motor control.
FEATURES 80C51 Central Processing Unit
16 kbytes OTP (87C660X2, 87C661X2)
16 kbytes ROM (83C660X2, 83C661X2)
512 byte RAM
Boolean processor
Fully static operation
Low voltage (2.7 V to 5.5 V at 16 MHz) operation 12-clock operation with selectable 6-clock operation (via software
or via parallel programmer) Memory addressing capability
Up to 64 kbytes ROM and 64 kbytes RAM Power control modes:
Clock can be stopped and resumed
Idle mode
Power-down mode CMOS and TTL compatible Two speed ranges at VCC = 5 V
0 to 30 MHz with 6-clock operation
0 to 33 MHz with 12-clock operation Parallel programming with 87C51 compatible hardware interface
to programmer RAM expandable externally to 64 kbytes Programmable Counter Array (PCA)
PWM
Capture/compare PLCC and LQFP packages Extended temperature ranges Dual Data Pointers Security bits (3 bits) Encryption array - 64 bytes 8/9 interrupt sources Four interrupt priority levels Four 8-bit I/O ports One I2C serial port interface has a selectable data transfer mode,
either 400 kB/sec Fast-mode or 100 kB/sec Standard-mode
(8xC660X2 and 8xC661X2) A second I2C serial port interface has the 400 kB/sec Fast
data-transfer mode only and selectable slew rate control of the
output pins (8xC661X2) Full-duplex enhanced UART
Framing error detection
Automatic address recognition Three 16-bit timers/counters T0, T1 (standard 80C51) and
additional T2 (capture and compare) Programmable clock-out pin Asynchronous port reset Low EMI (inhibit ALE, slew rate controlled outputs, and 6-clock
mode) Wake-up from Power Down by an external interrupt
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
SELECTION TABLE
ORDERING INFORMATION
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
BLOCK DIAGRAM 1 2nd I2C on P8xC661X2 only.
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
BLOCK DIAGRAM (CPU-ORIENTED)
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
LOGIC SYMBOL
PINNING
Plastic Leaded Chip Carrier No internal connection May be left open, but it is recommended to connect VSS2 and
VSS3 to GND to improve EMC performance P8xC661X2 devices only, these pins are open-drain and have
the same electrical characteristics as P1.6 and P1.7
Plastic Quad Flat Pack No internal connection May be left open, but it is recommended to connect VSS2 and
VSS3 to GND to improve EMC performance P8xC661X2 devices only
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
PIN DESCRIPTIONS
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin (other than EA) must not be higher than VCC + 0.5 V or less than VSS – 0.5 V. The pins are designed for test mode also.
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
SPECIAL FUNCTION REGISTERS SFRs are bit addressable. SFRs are modified from or added to the 80C51 SFRs. Reserved bits.
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
SPECIAL FUNCTION REGISTERS (Continued) SFRs are bit addressable. SFRs are modified from or added to the 80C51 SFRs. Reserved bits. Reset value depends on reset source. 8xC661X2 only.
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
CLOCK CONTROL REGISTER (CKCON)This device allows control of the 6-clock/12-clock mode by means of
both an SFR bit (X2) and an OTP bit. The OTP clock control bit
OX2, when programmed by a parallel programmer (6-clock mode),
supersedes the X2 bit (CKCON.0). The CKCON register is shown
below in Figure 1.
Figure 1. Clock control (CKCON) registerAlso please note that the clock divider applies to the serial port for
modes 0 & 2 (fixed baud rate modes). This is because modes 1 & 3
(variable baud rate modes) use either Timer 1 or Timer 2.
Below is the truth table for the CPU clock mode.
Table 1.
RESETA reset is accomplished by holding the RST pin HIGH for at least
two machine cycles (12 oscillator periods in 6-clock mode, or
24 oscillator periods in 12-clock mode), while the oscillator is running.
To ensure a good power-on reset, the RST pin must be HIGH long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
VCC and RST must come up at the same time for a proper start-up.
Ports 1, 2, and 3 will asynchronously be driven to their reset
condition when a voltage above VIH1 (min.) is applied to RST.
The value on the EA pin is latched when RST is deasserted and has
no further effect.
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
LOW POWER MODES
Stop Clock ModeThe static design enables the clock speed to be reduced down to
0 MHz (stopped). When the oscillator is stopped, the RAM and
Special Function Registers retain their values. This mode allows
step-by-step utilization and permits reduced system power
consumption by lowering the clock frequency down to any value. For
lowest power consumption the Power Down mode is suggested.
Idle ModeIn the idle mode (see Table 2), the CPU puts itself to sleep while all
of the on-chip peripherals stay active. The instruction to invoke the
idle mode is the last instruction executed in the normal operating
mode before the idle mode is activated. The CPU contents, the
on-chip RAM, and all of the special function registers remain intact
during this mode. The idle mode can be terminated either by any
enabled interrupt (at which time the process is picked up at the
interrupt service routine and continued), or by a hardware reset
which starts the processor in the same manner as a power-on reset.
Power-Down ModeTo save even more power, a Power Down mode (see Table 2) can
be invoked by software. In this mode, the oscillator is stopped and
the instruction that invoked Power Down is the last instruction
executed. The on-chip RAM and Special Function Registers retain
their values down to 2 V and care must be taken to return VCC to the
minimum specified operating voltages before the Power Down Mode
is terminated.
Either a hardware reset or external interrupt can be used to exit from
Power Down. Reset redefines all the SFRs but does not change the
on-chip RAM. An external interrupt allows both the SFRs and the
on-chip RAM to retain their values.
To properly terminate Power Down, the reset or external interrupt
should not be executed before VCC is restored to its normal
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10 ms).
With an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin LOW restarts the
oscillator but bringing the pin back HIGH completes the exit. Once
the interrupt is serviced, the next instruction to be executed after
RETI will be the one following the instruction that put the device into
Power Down.
LPEPThe EPROM array contains some analog circuits that are not
required when VCC is less than 3.6 V but are required for a VCC
greater than 3.6 V. The LPEP bit (AUXR.4), when set, will
powerdown these analog circuits resulting in a reduced supply
current. This bit should be set ONLY for applications that operate at
a VCC less than 4 V.
POWER-ON FLAGThe Power-On Flag (POF) is set by on-chip circuitry when the VCC
level on the P8xC66xX2 rises from 0 to 5 V. The POF bit can be set
or cleared by software allowing a user to determine if the reset is the
result of a power-on or a warm start after powerdown. The VCC level
must remain above 3 V for the POF to remain unaffected by the VCC
level.
Design ConsiderationWhen the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal reset algorithm takes control.
On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of
an unexpected write when Idle is terminated by reset, the instruction
following the one that invokes Idle should not be one that writes to a
port pin or to external memory.
ONCE ModeThe ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE Mode is invoked by: Pull ALE LOW while the device is in reset and PSEN is HIGH; Hold ALE LOW as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
HIGH. The oscillator circuit remains active. While the device is in
this mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
Programmable Clock-OutA 50% duty cycle clock can be programmed to come out on P1.0.
This pin, besides being a regular I/O pin, has two alternate
functions. It can be programmed: to input the external clock for Timer/Counter 2, or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a
16 MHz operating frequency in 12-clock mode (122 Hz to 8 MHz in
6-clock mode).
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit
TR2 (T2CON.2) also must be set to start the timer.
The Clock-Out frequency depends on the oscillator frequency and
the reload value of Timer 2 capture registers (RCAP2H, RCAP2L)
as shown in this equation:
Oscillator Frequency (65536� RCAP2H,RCAP2L)
n = 2 in 6-clock mode
4 in 12-clock mode
Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L
taken as a 16-bit unsigned integer.
In the Clock-Out mode Timer 2 roll-overs will not generate an
interrupt. This is similar to when it is used as a baud-rate generator.
It is possible to use Timer 2 as a baud-rate generator and a clock
generator simultaneously. Note, however, that the baud-rate and the
Clock-Out frequency will be the same.
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
Table 2. External Pin Status During Idle and Power-Down Mode
TIMER 0 AND TIMER 1 OPERATION
Timer 0 and Timer 1The “Timer” or “Counter” function is selected by control bits C/T in
the Special Function Register TMOD. These two Timer/Counters
have four operating modes, which are selected by bit-pairs (M1, M0)
in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters.
Mode 3 is different. The four operating modes are described in the
following text.
Mode 0Putting either Timer into Mode 0 makes it look like an 8048 Timer,
which is an 8-bit Counter with a divide-by-32 prescaler. Figure 3
shows the Mode 0 operation.
In this mode, the Timer register is configured as a 13-bit register. As
the count rolls over from all 1s to all 0s, it sets the Timer interrupt
flag TFn. The counted input is enabled to the Timer when TRn = 1
and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the
Timer to be controlled by external input INTn, to facilitate pulse width
measurements). TRn is a control bit in the Special Function Register
TCON (Figure 4).
The 13-bit register consists of all 8 bits of THn and the lower 5 bits
of TLn. The upper 3 bits of TLn are indeterminate and should be
ignored. Setting the run flag (TRn) does not clear the registers.
Mode 0 operation is the same for Timer 0 as for Timer 1. There are
two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer
0 (TMOD.3).
Mode 1Mode 1 is the same as Mode 0, except that the Timer register is
being run with all 16 bits.
Mode 2Mode 2 configures the Timer register as an 8-bit Counter (TLn) with
automatic reload, as shown in Figure 5. Overflow from TLn not only
sets TFn, but also reloads TLn with the contents of THn, which is
preset by software. The reload leaves THn unchanged.
Mode 2 operation is the same for Timer 0 as for Timer 1.
Mode 3Timer 1 in Mode 3 simply holds its count. The effect is the same as
setting TR1 = 0.
Timer 0 in Mode 3 establishes TL0 and TH0 as two separate
counters. The logic for Mode 3 on Timer 0 is shown in Figure 6. TL0
uses the Timer 0 control bits: C/T, GATE, TR0, and TF0 as well as
pin INT0. TH0 is locked into a timer function (counting machine
cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus,
TH0 now controls the “Timer 1” interrupt.
Mode 3 is provided for applications requiring an extra 8-bit timer on
the counter. With Timer 0 in Mode 3, an 80C51 can look like it has
three Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be
turned on and off by switching it out of and into its own Mode 3, or
can still be used by the serial port as a baud rate generator, or in
fact, in any application not requiring an interrupt.
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
Figure 2. Timer/Counter 0/1 Mode Control (TMOD) Register
Figure 3. Timer/Counter 0/1 Mode 0: 13-Bit Timer/Counter
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
Figure 4. Timer/Counter 0/1 Control (TCON) Register
Figure 5. Timer/Counter 0/1 Mode 2: 8-Bit Auto-Reload
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
Figure 6. Timer/Counter 0 Mode 3: Two 8-Bit Counters
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
TIMER 2 OPERATION
Timer 2Timer 2 is a 16-bit Timer/Counter which can operate as either an
event timer or an event counter, as selected by C/T2 in the special
function register T2CON (see Figure 1). Timer 2 has three operating
modes: Capture, Auto-reload (up or down counting), and Baud Rate
Generator, which are selected by bits in the T2CON as shown in
Table 3.
Capture ModeIn the capture mode there are two options which are selected by bit
EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or
counter (as selected by C/T2 in T2CON) which, upon overflowing
sets bit TF2, the timer 2 overflow bit. This bit can be used to
generate an interrupt (by enabling the Timer 2 interrupt bit in the
IE register). If EXEN2= 1, Timer 2 operates as described above, but
with the added feature that a 1- to -0 transition at external input
T2EX causes the current value in the Timer 2 registers, TL2 and
TH2, to be captured into registers RCAP2L and RCAP2H,
respectively. In addition, the transition at T2EX causes bit EXF2 in
T2CON to be set, and EXF2 like TF2 can generate an interrupt
(which vectors to the same location as Timer 2 overflow interrupt.
The Timer 2 interrupt service routine can interrogate TF2 and EXF2
to determine which event caused the interrupt). The capture mode is
illustrated in Figure 2 (There is no reload value for TL2 and TH2 in
this mode. Even when a capture event occurs from T2EX, the
counter keeps on counting T2EX pin transitions or osc/6 pulses
(osc/12 in 12-clock mode).).
Auto-Reload Mode (Up or Down Counter)In the 16-bit auto-reload mode, Timer 2 can be configured (as either
a timer or counter [C/T2 in T2CON]) then programmed to count up
or down. The counting direction is determined by bit DCEN (Down
Counter Enable) which is located in the T2MOD register (see
Figure 3). When reset is applied the DCEN=0 which means Timer 2
will default to counting up. If DCEN bit is set, Timer 2 can count up
or down depending on the value of the T2EX pin.
Figure 4 shows Timer 2 which will count up automatically since
DCEN=0. In this mode there are two options selected by bit EXEN2
in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH
and sets the TF2 (Overflow Flag) bit upon overflow. This causes the
Timer 2 registers to be reloaded with the 16-bit value in RCAP2L
and RCAP2H. The values in RCAP2L and RCAP2H are preset by
software means.
If EXEN2=1, then a 16-bit reload can be triggered either by an
overflow or by a 1-to-0 transition at input T2EX. This transition also
sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be
generated when either TF2 or EXF2 are 1.
In Figure 5 DCEN=1 which enables Timer 2 to count up or down.
This mode allows pin T2EX to control the direction of count. When a
logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will
overflow at 0FFFFH and set the TF2 flag, which can then generate
an interrupt, if the interrupt is enabled. This timer overflow also
causes the 16-bit value in RCAP2L and RCAP2H to be reloaded
into the timer registers TL2 and TH2.
When a logic 0 is applied at pin T2EX this causes Timer 2 to count
down. The timer will underflow when TL2 and TH2 become equal to
the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets
the TF2 flag and causes 0FFFFH to be reloaded into the timer
registers TL2 and TH2.
The external flag EXF2 toggles when Timer 2 underflows or overflows.
This EXF2 bit can be used as a 17th bit of resolution if needed. The
EXF2 flag does not generate an interrupt in this mode of operation.
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
Table 3. Timer 2 Operating Modes
Figure 2. Timer 2 in Capture Mode
Figure 3. Timer 2 Mode (T2MOD) Control Register
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0)
Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
Figure 6. Timer 2 in Baud Rate Generator Mode
Table 4. Timer 2 Generated Commonly Used
Baud Rates
Baud Rate Generator ModeBits TCLK and/or RCLK in T2CON (Table 4) allow the serial port
transmit and receive baud rates to be derived from either Timer 1 or
Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit
baud rate generator. When TCLK= 1, Timer 2 is used as the serial
port transmit baud rate generator. RCLK has the same effect for the
serial port receive baud rate. With these two bits, the serial port can
have different receive and transmit baud rates – one generated by
Timer 1, the other by Timer 2.
Figure 6 shows the Timer 2 in baud rate generation mode. The baud
rate generation mode is like the auto-reload mode,in that a rollover in
The baud rates in modes 1 and 3 are determined by Timer 2’s
overflow rate given below:
Modes1 and3 Baud Rates� Timer2 Overflow Rate
The timer can be configured for either “timer” or “counter” operation.
In many applications, it is configured for “timer” operation (C/T2=0).
Timer operation is different for Timer 2 when it is being used as a
baud rate generator.
Usually, as a timer it would increment every machine cycle (i.e., /6 the oscillator frequency in 6-clock mode, 1 /12 the oscillator
frequency in 12-clock mode). As a baud rate generator, it
increments at the oscillator frequency in 6-clock mode (OSC/2 in
12-clock mode). Thus the baud rate formula is as follows:
Oscillator Frequency
[n*� [65536� (RCAP2H,RCAP2L)]]
Modes 1 and 3 Baud Rates =
* n = 16 in 6-clock mode
32 in 12-clock mode
Where: (RCAP2H, RCAP2L)= The content of RCAP2H and
RCAP2L taken as a 16-bit unsigned integer.
The Timer 2 as a baud rate generator mode shown in Figure 6, is
valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a
rollover in TH2 does not set TF2, and will not generate an interrupt.
Thus, the Timer 2 interrupt does not have to be disabled when
Timer 2 is in the baud rate generator mode. Also if the EXEN2
(T2 external enable flag) is set, a 1-to-0 transition in T2EX
(Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
When Timer 2 is in the baud rate generator mode, one should not try
to read or write TH2 and TL2. As a baud rate generator, Timer 2 is
incremented every state time (osc/2) or asynchronously from pin T2;
under these conditions, a read or write of TH2 or TL2 may not be
accurate. The RCAP2 registers may be read, but should not be
written to, because a write might overlap a reload and cause write
and/or reload errors. The timer should be turned off (clear TR2)
before accessing the Timer 2 or RCAP2 registers.
Table 4 shows commonly used baud rates and how they can be
obtained from Timer 2.
Summary of Baud Rate EquationsTimer 2 is in baud rate generating mode. If Timer 2 is being clocked
through pin T2 (P1.0) the baud rate is:
Baud Rate� Timer2 Overflow Rate
If Timer 2 is being clocked internally, the baud rate is:
Baud Rate� fOSC* �[65536 �(RCAP2H,RCAP2L)]]
* n = 16 in 6-clock mode
32 in 12-clock mode
Where fOSC= Oscillator Frequency
To obtain the reload value for RCAP2H and RCAP2L, the above
equation can be rewritten as:
RCAP2H,RCAP2L� 65536�� fOSC� Baud Rate�
Timer/Counter 2 Set-upExcept for the baud rate generator mode, the values given for T2CON
do not include the setting of the TR2 bit. Therefore, bit TR2 must be
set, separately, to turn the timer on. see Table 5 for set-up of Timer 2
as a timer. Also see Table 6 for set-up of Timer 2 as a counter.
Table 5. Timer 2 as a Timer
Table 6. Timer 2 as a Counter
NOTES: Capture/reload occurs only on timer/counter overflow. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate
generator mode.
Philips Semiconductors Product data
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FULL-DUPLEX ENHANCED UART
Standard UART operationThe serial port is full duplex, meaning it can transmit and receive
simultaneously. It is also receive-buffered, meaning it can
commence reception of a second byte before a previously received
byte has been read from the register. (However, if the first byte still
hasn’t been read by the time reception of the second byte is
complete, one of the bytes will be lost.) The serial port receive and
transmit registers are both accessed at Special Function Register
SBUF. Writing to SBUF loads the transmit register, and reading
SBUF accesses a physically separate receive register.
The serial port can operate in 4 modes:
Mode 0: Serial data enters and exits through RxD. TxD outputs
the shift clock. 8 bits are transmitted/received (LSB first).
The baud rate is fixed at 1/12 the oscillator frequency in
12-clock mode or 1/6 the oscillator frequency in 6-clock
mode.
Mode 1: 10 bits are transmitted (through TxD) or received
(through RxD): a start bit (0), 8 data bits (LSB first), and
a stop bit (1). On receive, the stop bit goes into RB8 in
Special Function Register SCON. The baud rate is
variable.
Mode 2: 11 bits are transmitted (through TxD) or received
(through RxD): start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On
Transmit, the 9th data bit (TB8 in SCON) can be
assigned the value of 0 or 1. Or, for example, the parity
bit (P, in the PSW) could be moved into TB8. On receive,
the 9th data bit goes into RB8 in Special Function
Register SCON, while the stop bit is ignored. The baud
rate is programmable to either 1/32 or 1/64 the oscillator
frequency in 12-clock mode or 1/16 or 1/32 the oscillator
frequency in 6-clock mode.
Mode 3: 11 bits are transmitted (through TxD) or received
(through RxD): a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). In fact,
Mode 3 is the same as Mode 2 in all respects except
baud rate. The baud rate in Mode 3 is variable.
In all four modes, transmission is initiated by any instruction that
uses SBUF as a destination register. Reception is initiated in Mode 0
by the condition RI = 0 and REN = 1. Reception is initiated in the
other modes by the incoming start bit if REN = 1.
Multiprocessor CommunicationsModes 2 and 3 have a special provision for multiprocessor
communications. In these modes, 9 data bits are received. The 9th
one goes into RB8. Then comes a stop bit. The port can be
programmed such that when the stop bit is received, the serial port
interrupt will be activated only if RB8 = 1. This feature is enabled by
setting bit SM2 in SCON. A way to use this feature in multiprocessor
systems is as follows:
When the master processor wants to transmit a block of data to one
of several slaves, it first sends out an address byte which identifies
the target slave. An address byte differs from a data byte in that the
9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no
The slaves that weren’t being addressed leave their SM2s set and
go on about their business, ignoring the coming data bytes.
SM2 has no effect in Mode 0, and in Mode 1 can be used to check
the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the
receive interrupt will not be activated unless a valid stop bit is
received.
Serial Port Control RegisterThe serial port control and status register is the Special Function
Register SCON, shown in Figure 7. This register contains not only
the mode selection bits, but also the 9th data bit for transmit and
receive (TB8 and RB8), and the serial port interrupt bits (TI and RI).
Baud RatesThe baud rate in Mode 0 is fixed: Mode 0 Baud Rate = Oscillator
Frequency / 12 (12-clock mode) or / 6 (6-clock mode). The baud
rate in Mode 2 depends on the value of bit SMOD in Special
Function Register PCON. If SMOD = 0 (which is the value on reset),
and the port pins in 12-clock mode, the baud rate is 1/64 the
oscillator frequency. If SMOD = 1, the baud rate is 1/32 the oscillator
frequency. In 6-clock mode, the baud rate is 1/32 or 1/16 the
oscillator frequency, respectively.
Mode 2 Baud Rate =
2SMODn � (Oscillator Frequency)
Where:
n = 64 in 12-clock mode, 32 in 6-clock mode
The baud rates in Modes 1 and 3 are determined by the Timer 1 or
Timer 2 overflow rate.
Using Timer 1 to Generate Baud RatesWhen Timer 1 is used as the baud rate generator (T2CON.RCLK
= 0, T2CON.TCLK = 0), the baud rates in Modes 1 and 3 are
determined by the Timer 1 overflow rate and the value of SMOD as
follows:
Mode 1, 3 Baud Rate =
2SMOD � (Timer1 Overflow Rate)
Where:
n = 32 in 12-clock mode, 16 in 6-clock mode
The Timer 1 interrupt should be disabled in this application. The
Timer itself can be configured for either “timer” or “counter”
operation, and in any of its 3 running modes. In the most typical
applications, it is configured for “timer” operation, in the auto-reload
mode (high nibble of TMOD = 0010B). In that case the baud rate is
given by the formula:
Mode 1, 3 Baud Rate =
2SMODn � Oscillator Frequency� [256–(TH1)]
Where:
n = 32 in 12-clock mode, 16 in 6-clock mode
One can achieve very low baud rates with Timer 1 by leaving the
Timer 1 interrupt enabled, and configuring the Timer to run as a
16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1
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Figure 7. Serial Port Control (SCON) Register
Figure 8. Timer 1 Generated Commonly Used Baud Rates
More About Mode 0Serial data enters and exits through RxD. TxD outputs the shift
clock. 8 bits are transmitted/received: 8 data bits (LSB first). The
baud rate is fixed a 1/12 the oscillator frequency (12-clock mode) or
1/6 the oscillator frequency (6-clock mode).
Figure 9 shows a simplified functional diagram of the serial port in
Mode 0, and associated timing.
Transmission is initiated by any instruction that uses SBUF as a
destination register. The “write to SBUF” signal at S6P2 also loads a
1 into the 9th position of the transmit shift register and tells the TX
Control block to commence a transmission. The internal timing is
such that one full machine cycle will elapse between “write to SBUF”
and activation of SEND.
S6P2 of every machine cycle in which SEND is active, the contents
of the transmit shift are shifted to the right one position.
As data bits shift out to the right, zeros come in from the left. When
the MSB of the data byte is at the output position of the shift register,
then the 1 that was initially loaded into the 9th position, is just to the
left of the MSB, and all positions to the left of that contain zeros.
This condition flags the TX Control block to do one last shift and
then deactivate SEND and set T1. Both of these actions occur at
S1P1 of the 10th machine cycle after “write to SBUF.”
Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2
of the next machine cycle, the RX Control unit writes the bits
11111110 to the receive shift register, and in the next clock phase
activates RECEIVE.
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MHz), two 400KB I2 C interfaces
shifted to the left one position. The value that comes in from the right
is the value that was sampled at the P3.0 pin at S5P2 of the same
machine cycle.
As data bits come in from the right, 1s shift out to the left. When the
0 that was initially loaded into the rightmost position arrives at the
leftmost position in the shift register, it flags the RX Control block to
do one last shift and load SBUF. At S1P1 of the 10th machine cycle
after the write to SCON that cleared RI, RECEIVE is cleared as RI is
set.
More About Mode 1Ten bits are transmitted (through TxD), or received (through RxD): a
start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the
stop bit goes into RB8 in SCON. In the 80C51 the baud rate is
determined by the Timer 1 or Timer 2 overflow rate.
Figure 10 shows a simplified functional diagram of the serial port in
Mode 1, and associated timings for transmit receive.
Transmission is initiated by any instruction that uses SBUF as a
destination register. The “write to SBUF” signal also loads a 1 into
the 9th bit position of the transmit shift register and flags the TX
Control unit that a transmission is requested. Transmission actually
commences at S1P1 of the machine cycle following the next rollover
in the divide-by-16 counter. (Thus, the bit times are synchronized to
the divide-by-16 counter, not to the “write to SBUF” signal.)
The transmission begins with activation of SEND which puts the
start bit at TxD. One bit time later, DATA is activated, which enables
the output bit of the transmit shift register to TxD. The first shift pulse
occurs one bit time after that.
As data bits shift out to the right, zeros are clocked in from the left.
When the MSB of the data byte is at the output position of the shift
register, then the 1 that was initially loaded into the 9th position is
just to the left of the MSB, and all positions to the left of that contain
zeros. This condition flags the TX Control unit to do one last shift
and then deactivate SEND and set TI. This occurs at the 10th
divide-by-16 rollover after “write to SBUF.”
Reception is initiated by a detected 1-to-0 transition at RxD. For this
purpose RxD is sampled at a rate of 16 times whatever baud rate
has been established. When a transition is detected, the
divide-by-16 counter is immediately reset, and 1FFH is written into
the input shift register. Resetting the divide-by-16 counter aligns its
rollovers with the boundaries of the incoming bit times.
The 16 states of the counter divide each bit time into 16ths. At the
7th, 8th, and 9th counter states of each bit time, the bit detector
samples the value of RxD. The value accepted is the value that was
seen in at least 2 of the 3 samples. This is done for noise rejection.
If the value accepted during the first bit time is not 0, the receive
circuits are reset and the unit goes back to looking for another 1-to-0
transition. This is to provide rejection of false start bits. If the start bit
proves valid, it is shifted into the input shift register, and reception of
the rest of the frame will proceed.
As data bits come in from the right, 1s shift out to the left. When the
start bit arrives at the leftmost position in the shift register (which in
mode 1 is a 9-bit register), it flags the RX Control block to do one
last shift, load SBUF and RB8, and set RI. The signal to load SBUF
and RB8, and to set RI, will be generated if, and only if, the following
conditions are met at the time the final shift pulse is generated.: R1 = 0, and Either SM2 = 0, or the received stop bit = 1.
whether the above conditions are met or not, the unit goes back to
looking for a 1-to-0 transition in RxD.
More About Modes 2 and 3Eleven bits are transmitted (through TxD), or received (through
RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data
bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be
assigned the value of 0 or 1. On receive, the 9the data bit goes into
RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64
(12-clock mode) or 1/16 or 1/32 the oscillator frequency (6-clock
mode) the oscillator frequency in Mode 2. Mode 3 may have a
variable baud rate generated from Timer 1 or Timer 2.
Figures 11 and 12 show a functional diagram of the serial port in
Modes 2 and 3. The receive portion is exactly the same as in Mode
1. The transmit portion differs from Mode 1 only in the 9th bit of the
transmit shift register.
Transmission is initiated by any instruction that uses SBUF as a
destination register. The “write to SBUF” signal also loads TB8 into
the 9th bit position of the transmit shift register and flags the TX
Control unit that a transmission is requested. Transmission
commences at S1P1 of the machine cycle following the next rollover
in the divide-by-16 counter. (Thus, the bit times are synchronized to
the divide-by-16 counter, not to the “write to SBUF” signal.)
The transmission begins with activation of SEND, which puts the
start bit at TxD. One bit time later, DATA is activated, which enables
the output bit of the transmit shift register to TxD. The first shift pulse
occurs one bit time after that. The first shift clocks a 1 (the stop bit)
into the 9th bit position of the shift register. Thereafter, only zeros
are clocked in. Thus, as data bits shift out to the right, zeros are
clocked in from the left. When TB8 is at the output position of the
shift register, then the stop bit is just to the left of TB8, and all
positions to the left of that contain zeros. This condition flags the TX
Control unit to do one last shift and then deactivate SEND and set
TI. This occurs at the 11th divide-by-16 rollover after “write to SUBF.”
Reception is initiated by a detected 1-to-0 transition at RxD. For this
purpose RxD is sampled at a rate of 16 times whatever baud rate
has been established. When a transition is detected, the
divide-by-16 counter is immediately reset, and 1FFH is written to the
input shift register.
At the 7th, 8th, and 9th counter states of each bit time, the bit
detector samples the value of R-D. The value accepted is the value
that was seen in at least 2 of the 3 samples. If the value accepted
during the first bit time is not 0, the receive circuits are reset and the
unit goes back to looking for another 1-to-0 transition. If the start bit
proves valid, it is shifted into the input shift register, and reception of
the rest of the frame will proceed.
As data bits come in from the right, 1s shift out to the left. When the
start bit arrives at the leftmost position in the shift register (which in
Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do
one last shift, load SBUF and RB8, and set RI.
The signal to load SBUF and RB8, and to set RI, will be generated
if, and only if, the following conditions are met at the time the final
shift pulse is generated. RI = 0, and Either SM2 = 0, or the received 9th data bit = 1.
If either of these conditions is not met, the received frame is
irretrievably lost, and RI is not set. If both conditions are met, the
received 9th data bit goes into RB8, and the first 8 data bits go into
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Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
Enhanced FeaturesThe UART operates in all of the usual modes that are described in
the first section of Data Handbook IC20, 80C51-Based 8-Bit
Microcontrollers. In addition the UART can perform framing error
detect by looking for missing stop bits, and automatic address
recognition. The UART also fully supports multiprocessor
communication as does the standard 80C51 UART.
When used for framing error detect the UART looks for missing stop
bits in the communication. A missing bit will set the FE bit in the
SCON register. The FE bit shares the SCON.7 bit with SM0 and the
function of SCON.7 is determined by PCON.6 (SMOD0) (see
Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7
functions as SM0 when SMOD0 is cleared. When used as FE
SCON.7 can only be cleared by software. Refer to Figure 13.
Automatic Address RecognitionAutomatic Address Recognition is a feature which allows the UART
to recognize certain addresses in the serial bit stream by using
hardware to make the comparisons. This feature saves a great deal
of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART
modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be
automatically set when the received byte contains either the “Given”
address or the “Broadcast” address. The 9-bit mode requires that
the 9th information bit is a 1 to indicate that the received information
is an address and not data. Automatic address recognition is shown
in Figure 14.
The 8 bit mode is called Mode 1. In this mode the RI flag will be set
if SM2 is enabled and the information received has a valid stop bit
following the 8 address bits and the information is either a Given or
Broadcast address.
Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to
selectively communicate with one or more slaves by invoking the
Given slave address or addresses. All of the slaves may be
contacted by using the Broadcast address. Two special Function
Registers are used to define the slave’s address, SADDR, and the
address mask, SADEN. SADEN is used to define which bits in the
SADDR are to b used and which bits are “don’t care”. The SADEN
mask can be logically ANDed with the SADDR to create the “Given”
address which the master will use for addressing each of the slaves.
Use of the Given address allows multiple slaves to be recognized
while excluding others. The following examples will help to show the
versatility of this scheme:
Slave 0 SADDR = 1100 0000
SADEN =
Given = 1100 00X0
Slave 1 SADDR = 1100 0000
SADEN =
Given = 1100 000X
In the above example SADDR is the same and the SADEN data is
used to differentiate between the two slaves. Slave 0 requires a 0 in
bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is
ignored. A unique address for Slave 0 would be 1100 0010 since
slave 1 requires a 0 in bit 1. A unique address for slave 1 would be
1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be
selected at the same time by an address which has bit 0 = 0 (for
slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed
with 1100 0000.
In a more complex system the following could be used to select
slaves 1 and 2 while excluding slave 0:
Slave 0 SADDR = 1100 0000
SADEN = 1111 1001
Given = 1100 0XX0
Slave 1 SADDR = 1110 0000
SADEN = 1111 1010
Given = 1110 0X0X
Slave 2 SADDR = 1110 0000
SADEN = 1111 1100
Given = 1110 00XX
In the above example the differentiation among the 3 slaves is in the
lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and
it can be uniquely addressed by 1110 and 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are trended
as don’t-cares. In most cases, interpreting the don’t-cares as ones,
the broadcast address will be FF hexadecimal.
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR
address 0B9H) are leaded with 0s. This produces a given address
of all “don’t cares” as well as a Broadcast address of all “don’t
cares”. This effectively disables the Automatic Addressing mode and
allows the microcontroller to use standard 80C51 type UART drivers
which do not make use of this feature.
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Figure 13. UART Framing Error Detection
Figure 14. UART Multiprocessor Communication, Automatic Address Recognition
Philips Semiconductors Product data
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MHz), two 400KB I2 C interfaces
SIO1 and SIO2, I2C Serial I/OThe I2 C-bus is a simple bi-directional 2-wire bus to transfer
information between devices connected to the bus. The main
features of the bus are: Only two bus lines are required: a serial clock line (SCL) and a
serial data line (SDA). Bi-directional data transfer between masters and slaves. Each device connected to the bus is software addressable by a
unique address. Masters can operate as Master-transmitter or as Master-receiver. It is a true multi-master bus (no central master) and includes
collision detection and arbitration to prevent data corruption if two
or more masters simultaneously initiate data transfer. Serial clock synchronization allows devices with different bit rates
to communicate via the same serial bus. Serial clock synchronization can be used as a handshake
mechanism to suspend and resume serial transfer. Devices can be added to or removed from an I2C-bus system
without affecting any other device on the bus. Fault diagnostics and debugging are simple; malfunctions can be
immediately traced.
For more information see the Philips publication “The I2C-Bus
Specification”, especially for detailed descriptions of the Fast and
the Standard data-transfer modes. Also, refer to the data sheets for
the 8xC552, the 8xC554, the 8xC557, and the 8xC65x.
The SIO1 I2 C serial port interface has a selectable bi-directional
data-transfer mode, either the 400Kbit/s Fast-mode or the 100Kbit/s
Standard-mode. In the Fast-mode, the port performance and the
register definitions are identical to those of the 8xC557 devices, and
in the Standard-mode (the reset default), they are identical to those
of the 8xC652, 8xC654, 8xC552, and 8xC554 devices.
The Fast-mode is functionally the same as the Standard-mode
except for the bit rate selection (see Tables 7 and 8), the timing
of the SCL and SDA signals (see the I2 C electrical
characteristics), and the output slew-rate control. The
Fast-mode allows up to a four-fold bit-rate increase over that of
the Standard-mode, and yet, it is downward compatible with the
Standard-mode, i.e. it can be used in a 0 to 100Kbit/s bus
system.The SCL serial port for the clock line of the I2 C bus is an alternate
function of the P1.6 port pin, and the SDA serial port for the data line
of the I2C bus is an alternate function of the P1.7 port pin.
Consequently, these 2 port pins are open drain outputs (no
pull-ups), and the output latches of P1.6 and P1.7 must be set to
logic 1 in order to enable the SIO1 outputs.
The second I2C serial port of the 8xC661X2, SIO2, has the
400Kbit/s Fast data-transfer mode only and selectable slew-rate
control of the output pins. It also has the same port performance
and register definitions as those of the 8xC557. The SCL1 and
SDA1 serial ports have dedicated pins with open-drain outputs and
Schmitt-trigger inputs.
There is an analog circuit for controlling the turn-on and turn-off
circuit must be disabled. For the SIO1 serial port, the slew-rate
control circuits for both the SCL and SDA pins are disabled in the
Standard mode (maximum slew-rate), and they are enabled in the
Fast-mode. For the SIO2 serial port, the slew-rate control circuits
for both pins are enabled by reset, but the Slew-Rate Disable bit
(SRD bit) in the AUXR Register disables the slew-rate circuits for
both the SCL1 and SDA1 pins when set for maximum slew-rates.
This feature of the SIO2 slew-rate control is very useful for higher
bus loads, higher temperatures and lower voltages that cause
additional decreases in slew-rates.
All of the functional descriptions discussed below apply to
both the SIO1 and the SIO2 I2C serial ports although the text
may refer to the SIO1 only. See page 10 for the corresponding
SIO2 register addresses.The I2C on-chip logic performs a byte oriented data transfer, clock
generation, address recognition and bus control arbitration, and
interfaces to the external I2C-bus via the two port pins SCL and
SDA. It meets the I2C-bus specification and supports all transfer
modes (other than the low-speed mode) from-and-to the I2C-bus.
The logic handles byte transfers autonomously. It also keeps track
of serial transfers, and a status register (SxSTA) reflects the status
of the SIOx logic and the I2C-bus.
The CPU interfaces to the logic of each of the two I2Cs via the
following four Special Function Registers (where x=1,2): SxCON: Control register, bit addressable by the CPU. SxSTA: Status register whose contents may be used as a vector
to service routines. SxDAT: Data shift register; the data byte is stable as long as the
SI bit = 1 (SxCON.3). SxADR: Slave address register; its LSB enables / disables
general call address recognition.
A typical I2 C-bus configuration is shown in Figure 15, and Figure 16
shows how a data transfer is accomplished on the bus. Depending
on the state of the direction bit (R/W), two types of data transfers are
possible on the I2 C-bus: Data transfer from a master transmitter to a slave receiver. The
first byte transmitted by the master is the slave address. Next
follows a number of data bytes. The slave returns an
acknowledge bit after each received byte. Data transfer from a slave transmitter to a master receiver. The
first byte (the slave address) is transmitted by the master. The
slave then returns an acknowledge bit. Next follows the data
bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last
byte. At the end of the last received byte, a “not acknowledge” is
returned.
The master device generates all of the serial clock pulses and the
START and STOP conditions. A transfer is ended with a STOP
condition or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial transfer, the
I2C bus will not be released.
Modes of Operation: The on-chip SIO1 logic may operate in thefollowing four modes: Master Transmitter Mode:
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of the receiving device (7 bytes) and the data direction bit. In this
case the data direction bit (R/W) will be logic 0, and we say that
a “W” is transmitted. Thus the first byte transmitted is SLA+W.
Serial data is transmitted 8 bits at a time. After each byte is
transmitted, an acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the end of a
serial transfer. Master Receiver Mode:
The first byte transmitted contains the slave address of
the transmitting device (7 bits) and the data direction bit. In this
case, the data direction bit (R/W) will be logic 1, and we say that
an “R” is transmitted. Thus the first byte transmitted is SLA+R.
Serial data is received via P1.7/SDA while P1.6/SCL outputs the
serial clock. Serial data is received 8 bits at a time. After each
byte is received an acknowledge bit is transmitted. START and
STOP conditions are output to indicate the beginning and end of
a serial transfer. Slave Receiver Mode:
Serial data and the serial clock are received through P1.7/SDA
and P1.6/SCL. After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is
performed by hardware after reception of the slave address and
direction bit. Slave Transmitter Mode:
The first byte is received and handled as in the slave receiver
mode. However, in this mode, the direction bit will indicate that
the transfer direction is reversed. Serial data is transmitted via
P1.7/SDA while the serial clock is input through P1.6/SCL.
START and STOP conditions are recognized as the beginning
and end of a serial transfer.
In a given application, SIO1 may operate as a master and as a
slave. In the slave mode, the SIO1 hardware looks for its own slave
address and the general call address. If one of these addresses is
detected, an interrupt is requested. When the microcontroller wishes
to become the bus master, the hardware waits until the bus is free
before the master mode is entered so that a possible slave action is
not interrupted. If bus arbitration is lost in the master mode, SIO1
switches to the slave mode immediately and can detect its own
slave address in the same serial transfer.
Figure 15. Typical I2C Bus Configuration
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SIO1 Implementation and Operation: Figure 17 shows how theon-chip I2 C bus interface is implemented, and the following text
describes the individual blocks.
INPUT FILTERS AND OUTPUT STAGES
The input filters have I2 C compatible input levels. If the input voltage
is less than 1.5 V, the input logic level is interpreted as 0; if the input
voltage is greater than 3.0 V, the input logic level is interpreted as 1.
Input signals are synchronized with the internal clock (fOSC/4), and
spikes shorter than three oscillator periods are filtered out.
The output stages consist of open drain transistors that can sink
3 mA at VOUT < 0.4 V. These open drain outputs do not have
clamping diodes to VDD. Thus, if the device is connected to the I2C
bus and VDD is switched off, the I2C bus is not affected.
ADDRESS REGISTER, S1ADR
This 8-bit special function register may be loaded with the 7-bit slave
address (7 most significant bits) to which SIO1 will respond when
programmed as a slave transmitter or receiver. The LSB (GC) is
used to enable general call address (00H) recognition.
COMPARATOR
The comparator compares the received 7-bit slave address with its
own slave address (7 most significant bits in S1ADR). It also
compares the first received 8-bit byte with the general call address
(00H). If an equality is found, the appropriate status bits are set and
an interrupt is requested.
SHIFT REGISTER, S1DAT
This 8-bit special function register contains a byte of serial data to
be transmitted or a byte which has just been received. Data in
S1DAT is always shifted from right to left; the first bit to be
transmitted is the MSB (bit 7) and, after a byte has been received,
the first bit of received data is located at the MSB of S1DAT. While
data is being shifted out, data on the bus is simultaneously being
shifted in; S1DAT always contains the last byte present on the bus.
Thus, in the event of lost arbitration, the transition from master
transmitter to slave receiver is made with the correct data in S1DAT.
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Figure 17. I2C Bus Serial Interface Block Diagram
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RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
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ARBITRATION AND SYNCHRONIZATION LOGIC
In the master transmitter mode, the arbitration logic checks that
every transmitted logic 1 actually appears as a logic 1 on the I2C
bus. If another device on the bus overrules a logic 1 and pulls the
SDA line LOW, arbitration is lost, and SIO1 immediately changes
from master transmitter to slave receiver. SIO1 will continue to
output clock pulses (on SCL) until transmission of the current serial
byte is complete.
Arbitration may also be lost in the master receiver mode. Loss of
arbitration in this mode can only occur while SIO1 is returning a “not
acknowledge: (logic 1) to the bus. Arbitration is lost when another
device on the bus pulls this signal LOW. Since this can occur only at
the end of a serial byte, SIO1 generates no further clock pulses.
Figure 18 shows the arbitration procedure.
The synchronization logic will synchronize the serial clock generator
with the clock pulses on the SCL line from another device. If two or
more master devices generate clock pulses, the “mark” duration is
determined by the device that generates the shortest “marks,” and
the “space” duration is determined by the device that generates the
longest “spaces.” Figure 19 shows the synchronization procedure.
A slave may stretch the space duration to slow down the bus
master. The space duration may also be stretched for handshaking
purposes. This can be done after each bit or after a complete byte
transfer. SIO1 will stretch the SCL space duration after a byte has
been transmitted or received and the acknowledge bit has been
transferred. The serial interrupt flag (SI) is set, and the stretching
continues until the serial interrupt flag is cleared.
Figure 18. Arbitration Procedure
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SERIAL CLOCK GENERATOR
This programmable clock pulse generator provides the SCL clock
pulses when SIO1 is in the master transmitter or master receiver
mode. It is switched off when SIO1 is in a slave mode. In standard
speed mode, the programmable output clock frequencies are:
fOSC/120, fOSC/9600, and the Timer 1 overflow rate divided by eight.
The output clock pulses have a 50% duty cycle unless the clock
generator is synchronized with other SCL clock sources as
described above.
TIMING AND CONTROL
The timing and control logic generates the timing and control signals
for serial byte handling. This logic block provides the shift pulses for
S1DAT, enables the comparator, generates and detects start and
stop conditions, receives and transmits acknowledge bits, controls
the master and slave modes, contains interrupt request logic, and
monitors the I2C bus status.
CONTROL REGISTER, S1CON
This 7-bit special function register is used by the microcontroller to
control the following SIO1 functions: start and restart of a serial
transfer, termination of a serial transfer, bit rate, address recognition,
and acknowledgment.
STATUS DECODER AND STATUS REGISTER
The status decoder takes all of the internal status bits and
compresses them into a 5-bit code. This code is unique for each I2C
bus status. The 5-bit code may be used to generate vector
addresses for fast processing of the various service routines. Each
service routine processes a particular bus status. There are 26
possible bus states if all four modes of SIO1 are used. The 5-bit
status code is latched into the five most significant bits of the status
register when the serial interrupt flag is set (by hardware) and
remains stable until the interrupt flag is cleared by software. The
three least significant bits of the status register are always zero. If
the status code is used as a vector to service routines, then the
routines are displaced by eight address locations. Eight bytes of
code is sufficient for most of the service routines (see the software
example in this section).
The Four SIO1 Special Function Registers: The microcontrollerinterfaces to SIO1 via four special function registers. These four
SFRs (S1ADR, S1DAT, S1CON, and S1STA) are described
individually in the following sections.
The Address Register, S1ADR: The CPU can read from and writeto this 8-bit, directly addressable SFR. S1ADR is not affected by the
SIO1 hardware. The contents of this register are irrelevant when
SIO1 is in a master mode. In the slave modes, the seven most
significant bits must be loaded with the microcontroller’s own slave
address, and, if the least significant bit is set, the general call
address (00H) is recognized; otherwise it is ignored.
S1ADR (DBH) 65 4 3 2 1 0
The most significant bit corresponds to the first bit received from the
I2C bus after a start condition. A logic 1 in S1ADR corresponds to a
HIGH level on the I2C bus, and a logic 0 corresponds to a LOW
level on the bus.
The Data Register, S1DAT: S1DAT contains a byte of serial data toread from and write to this 8-bit, directly addressable SFR while it is
not in the process of shifting a byte. This occurs when SIO1 is in a
defined state and the serial interrupt flag is set. Data in S1DAT
remains stable as long as SI is set. Data in S1DAT is always shifted
from right to left: the first bit to be transmitted is the MSB (bit 7), and,
after a byte has been received, the first bit of received data is
located at the MSB of S1DAT. While data is being shifted out, data
on the bus is simultaneously being shifted in; S1DAT always
contains the last data byte present on the bus. Thus, in the event of
lost arbitration, the transition from master transmitter to slave
receiver is made with the correct data in S1DAT.
S1DAT (DAH) 65 4 3 2 1 0
shift direction
SD7 - SD0:
Eight bits to be transmitted or just received. A logic 1 in S1DAT
corresponds to a HIGH level on the I2C bus, and a logic 0
corresponds to a LOW level on the bus. Serial data shifts through
S1DAT from right to left. Figure 20 shows how data in S1DAT is
serially transferred to and from the SDA line.
S1DAT and the ACK flag form a 9-bit shift register which shifts in or
shifts out an 8-bit byte, followed by an acknowledge bit. The ACK
flag is controlled by the SIO1 hardware and cannot be accessed by
the CPU. Serial data is shifted through the ACK flag into S1DAT on
the rising edges of serial clock pulses on the SCL line. When a byte
has been shifted into S1DAT, the serial data is available in S1DAT,
and the acknowledge bit is returned by the control logic during the
ninth clock pulse. Serial data is shifted out from S1DAT via a buffer
(BSD7) on the falling edges of clock pulses on the SCL line.
When the CPU writes to S1DAT, BSD7 is loaded with the content of
S1DAT.7, which is the first bit to be transmitted to the SDA line (see
Figure 21). After nine serial clock pulses, the eight bits in S1DAT will
have been transmitted to the SDA line, and the acknowledge bit will
be present in ACK. Note that the eight transmitted bits are shifted
back into S1DAT.
The Control Register, S1CON: The CPU can read from and writeto this 8-bit, directly addressable SFR. Two bits are affected by the
SIO1 hardware: the SI bit is set when a serial interrupt is requested,
and the STO bit is cleared when a STOP condition is present on the
I2C bus. The STO bit is also cleared when ENS1 = “0”.
S1CON (D8H) 65 4 3 2 1 0
ENS1, THE SIO1 ENABLE BIT
ENS1 = “0”: When ENS1 is “0”, the SDA and SCL outputs are in a
high impedance state. SDA and SCL input signals are ignored, SIO1
is in the “not addressed” slave state, and the STO bit in S1CON is
forced to “0”. No other bits are affected. P1.6 and P1.7 may be used
as open drain I/O ports.
ENS1 = “1”: When ENS1 is “1”, SIO1 is enabled. The P1.6 and P1.7
port latches must be set to logic 1.
ENS1 should not be used to temporarily release SIO1 from the I2C
bus since, when ENS1 is reset, the I2C bus status is lost. The AA
flag should be used instead (see description of the AA flag in the
following text).
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Figure 20. Serial Input/Output Configuration
Figure 21. Shift-in and Shift-out TimingIn the following text, it is assumed that ENS1 = “1”.
STA, THE START FLAG
STA = “1”: When the STA bit is set to enter a master mode, the SIO1
hardware checks the status of the I2C bus and generates a START
condition if the bus is free. If the bus is not free, then SIO1 waits for
a STOP condition (which will free the bus) and generates a START
condition after a delay of a half clock period of the internal serial
clock generator.
STA = “0”: When the STA bit is reset, no START condition or
repeated START condition will be generated.
STO, THE STOP FLAG
STO = “1”: When the STO bit is set while SIO1 is in a master mode,
a STOP condition is transmitted to the I2C bus. When the STOP
condition is detected on the bus, the SIO1 hardware clears the STO
flag. In a slave mode, the STO flag may be set to recover from an
error condition. In this case, no STOP condition is transmitted to the
I2C bus. However, the SIO1 hardware behaves as if a STOP
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If the STA and STO bits are both set, the a STOP condition is
transmitted to the I2 C bus if SIO1 is in a master mode (in a slave
mode, SIO1 generates an internal STOP condition which is not
transmitted). SIO1 then transmits a START condition.
STO = “0”: When the STO bit is reset, no STOP condition will be
generated.
SI, THE SERIAL INTERRUPT FLAG
SI = “1”: When the SI flag is set, then, if the EA and ES1 (interrupt
enable register) bits are also set, a serial interrupt is requested. SI is
set by hardware when one of 25 of the 26 possible SIO1 states is
entered. The only state that does not cause SI to be set is state
F8H, which indicates that no relevant state information is available.
While SI is set, the LOW period of the serial clock on the SCL line is
stretched, and the serial transfer is suspended. A HIGH level on the
SCL line is unaffected by the serial interrupt flag. SI must be reset
by software.
SI = “0”: When the SI flag is reset, no serial interrupt is requested,
and there is no stretching of the serial clock on the SCL line.
AA, THE ASSERT ACKNOWLEDGE FLAG
AA = “1”: If the AA flag is set, an acknowledge (LOW level to SDA)
will be returned during the acknowledge clock pulse on the SCL line
when: The “own slave address” has been received The general call address has been received while the general call
bit (GC) in S1ADR is set A data byte has been received while SIO1 is in the master
receiver mode A data byte has been received while SIO1 is in the addressed
slave receiver mode
AA = “0”: if the AA flag is reset, a not acknowledge (HIGH level to
SDA) will be returned during the acknowledge clock pulse on SCL
when: A data has been received while SIO1 is in the master receiver
mode A data byte has been received while SIO1 is in the addressed
slave receiver mode
When SIO1 is in the addressed slave transmitter mode, state C8H
will be entered after the last serial is transmitted (see Figure 25).
When SI is cleared, SIO1 leaves state C8H, enters the not
addressed slave receiver mode, and the SDA line remains at a
HIGH level. In state C8H, the AA flag can be set again for future
address recognition.
When SIO1 is in the not addressed slave mode, its own slave
address and the general call address are ignored. Consequently, no
acknowledge is returned, and a serial interrupt is not requested.
Thus, SIO1 can be temporarily released from the I2C bus while the
bus status is monitored. While SIO1 is released from the bus,
START and STOP conditions are detected, and serial data is shifted
in. Address recognition can be resumed at any time by setting the
AA flag. If the AA flag is set when the part’s own slave address or
the general call address has been partly received, the address will
be recognized at the end of the byte transmission.
CR0, CR1, AND CR2, THE CLOCK RATE BITS
These three bits determine the serial clock frequency when SIO1 is
in a master mode. The various serial rates are shown in Table 7.
For the SIO1 serial port, the Standard data transfer mode is the
default mode after reset. To change the data transfer mode to the
Fast–mode, the Fast Mode Enable bit (FME bit) of the AUXR
Register (AUXR.3 bit) must be set. After setting the FME bit you
cannot clear it (a one–time set bit), and it can only be cleared with
a reset.For the SIO2 serial port, the analog circuits for controlling the
slew–rates of the output pull-downs may be disabled with the
Slew–Rate Disable bit (AUXR.5 bit). For maximum slew rates,
setting this bit disables the slew–rate control circuits of the SCL1
and SDA1 pins. This bit is cleared by reset (reset default), and it
can be set/cleared by software. This feature of the SIO2 slew–rate
control is very useful for higher bus loads, higher temperatures and
lower voltages that cause additional decreases in slew–rates.
AUXR (8EH) 65 4 3 2 1 0
A 12.5kHz bit rate may be used by devices that interface to the I2C
bus via standard I/O port lines which are software driven and slow.
100kHz is usually the maximum bit rate and can be derived from a
16 MHz, 12 MHz, or a 6 MHz oscillator. A variable bit rate (0.5kHz to
62.5kHz) may also be used if Timer 1 is not required for any other
purpose while SIO1 is in a master mode.
The frequencies shown in Table 7 are unimportant when SIO1 is in a
slave mode. In the slave modes, SIO1 will automatically synchronize
with any clock frequency up to 100kHz.
The Status Register, S1STA: S1STA is an 8-bit read-only specialfunction register. The three least significant bits are always zero.
The five most significant bits contain the status code. There are 26
possible status codes. When S1STA contains F8H, no relevant state
information is available and no serial interrupt is requested. All other
S1STA values correspond to defined SIO1 states. When each of
these states is entered, a serial interrupt is requested (SI = “1”). A
valid status code is present in S1STA one machine cycle after SI is
set by hardware and is still present one machine cycle after SI has
been reset by software.
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Table 7. 400 kbytes I2 C interface serial clock rates
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Table 8. 100 kbytes I2 C interface serial clock rates
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More Information on SIO1 Operating Modes: The four operatingmodes are: Master Transmitter Master Receiver Slave Receiver Slave Transmitter
Data transfers in each mode of operation are shown in Figures
22–25. These figures contain the following abbreviations:
Abbreviation Explanation Start condition
SLA 7-bit slave address Read bit (HIGH level at SDA) Write bit (LOW level at SDA) Acknowledge bit (LOW level at SDA) Not acknowledge bit (HIGH level at SDA)
Data 8-bit data byte Stop condition
In Figures 22-25, circles are used to indicate when the serial
interrupt flag is set. The numbers in the circles show the status code
held in the S1STA register. At these points, a service routine must
be executed to continue or complete the serial transfer. These
service routines are not critical since the serial transfer is suspended
until the serial interrupt flag is cleared by software.
When a serial interrupt routine is entered, the status code in S1STA
is used to branch to the appropriate service routine. For each status
code, the required software action and details of the following serial
transfer are given in Tables 9-13.
Master Transmitter Mode: In the master transmitter mode, anumber of data bytes are transmitted to a slave receiver (see
Figure 22). Before the master transmitter mode can be entered,
S1CON must be initialized as follows:
S1CON (D8H) 65 4 3 2 1 0
rate
CR0, CR1, and CR2 define the serial bit rate. ENS1 must be set to
logic 1 to enable SIO1. If the AA bit is reset, SIO1 will not
acknowledge its own slave address or the general call address in
the event of another device becoming master of the bus. In other
words, if AA is reset, SIO0 cannot enter a slave mode. STA, STO,
and SI must be reset.
The master transmitter mode may now be entered by setting the
STA bit using the SETB instruction. The SIO1 logic will now test the2 C bus and generate a start condition as soon as the bus becomes
free. When a START condition is transmitted, the serial interrupt flag
(SI) is set, and the status code in the status register (S1STA) will be
08H. This status code must be used to vector to an interrupt service
routine that loads S1DAT with the slave address and the data
direction bit (SLA+W). The SI bit in S1CON must then be reset
before the serial transfer can continue.
When the slave address and the direction bit have been transmitted
and an acknowledgment bit has been received, the serial interrupt
flag (SI) is set again, and a number of status codes in S1STA are
possible. There are 18H, 20H, or 38H for the master mode and also
68H, 78H, or B0H if the slave mode was enabled (AA = logic 1). The
may switch to the master receiver mode by loading S1DAT with
SLA+R).
Master Receiver Mode: In the master receiver mode, a number ofdata bytes are received from a slave transmitter (see Figure 23).
The transfer is initialized as in the master transmitter mode. When
the start condition has been transmitted, the interrupt service routine
must load S1DAT with the 7-bit slave address and the data direction
bit (SLA+R). The SI bit in S1CON must then be cleared before the
serial transfer can continue.
When the slave address and the data direction bit have been
transmitted and an acknowledgment bit has been received, the
serial interrupt flag (SI) is set again, and a number of status codes in
S1STA are possible. These are 40H, 48H, or 38H for the master
mode and also 68H, 78H, or B0H if the slave mode was enabled
(AA = logic 1). The appropriate action to be taken for each of these
status codes is detailed in Table 10. ENS1, CR1, and CR0 are not
affected by the serial transfer and are not referred to in Table 10.
After a repeated start condition (state 10H), SIO1 may switch to the
master transmitter mode by loading S1DAT with SLA+W.
Slave Receiver Mode: In the slave receiver mode, a number ofdata bytes are received from a master transmitter (see Figure 24).
To initiate the slave receiver mode, S1ADR and S1CON must be
loaded as follows:
S1ADR (DBH) 65 43 2 1 0
The upper 7 bits are the address to which SIO1 will respond when
addressed by a master. If the LSB (GC) is set, SIO1 will respond to
the general call address (00H); otherwise it ignores the general call
address.
S1CON (D8H) 65 4 3 2 1 0 0 0 0 1 X X
CR0, CR1, and CR2 do not affect SIO1 in the slave mode. ENS1
must be set to logic 1 to enable SIO1. The AA bit must be set to
enable SIO1 to acknowledge its own slave address or the general
call address. STA, STO, and SI must be reset.
When S1ADR and S1CON have been initialized, SIO1 waits until it
is addressed by its own slave address followed by the data direction
bit which must be “0” (W) for SIO1 to operate in the slave receiver
mode. After its own slave address and the W bit have been
received, the serial interrupt flag (I) is set and a valid status code
can be read from S1STA. This status code is used to vector to an
interrupt service routine, and the appropriate action to be taken for
each of these status codes is detailed in Table 11. The slave
receiver mode may also be entered if arbitration is lost while SIO1 is
in the master mode (see status 68H and 78H).
If the AA bit is reset during a transfer, SIO1 will return a not
acknowledge (logic 1) to SDA after the next received data byte.
While AA is reset, SIO1 does not respond to its own slave address
or a general call address. However, the I2C bus is still monitored
and address recognition may be resumed at any time by setting AA.
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Figure 22. Format and States in the Master Transmitter Mode
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ÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
Figure 23. Format and States in the Master Receiver Mode
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ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇÇÇÇ
ÇÇÇ
ÇÇÇ
Figure 24. Format and States in the Slave Receiver Mode
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Figure 25. Format and States of the Slave Transmitter Mode
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Table 9. Master Transmitter Mode
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Table 10. Master Receiver Mode
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Table 11. Slave Receiver Mode
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Table 11. Slave Receiver Mode (Continued)
Table 12. Slave Transmitter Mode
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Table 13. Miscellaneous States
Slave Transmitter Mode: In the slave transmitter mode, a numberof data bytes are transmitted to a master receiver (see Figure 25).
Data transfer is initialized as in the slave receiver mode. When
S1ADR and S1CON have been initialized, SIO1 waits until it is
addressed by its own slave address followed by the data direction
bit which must be “1” (R) for SIO1 to operate in the slave transmitter
mode. After its own slave address and the R bit have been received,
the serial interrupt flag (SI) is set and a valid status code can be
read from S1STA. This status code is used to vector to an interrupt
service routine, and the appropriate action to be taken for each of
these status codes is detailed in Table 12. The slave transmitter
mode may also be entered if arbitration is lost while SIO1 is in the
master mode (see state B0H).
If the AA bit is reset during a transfer, SIO1 will transmit the last byte
of the transfer and enter state C0H or C8H. SIO1 is switched to the
not addressed slave mode and will ignore the master receiver if it
continues the transfer. Thus the master receiver receives all 1s as
serial data. While AA is reset, SIO1 does not respond to its own
slave address or a general call address. However, the I2C bus is still
monitored, and address recognition may be resumed at any time by
setting AA. This means that the AA bit may be used to temporarily
isolate SIO1 from the I2C bus.
Miscellaneous States: There are two S1STA codes that do notcorrespond to a defined SIO1 hardware state (see Table 13). These
are discussed below.
S1STA = F8H:This status code indicates that no relevant information is available
because the serial interrupt flag, SI, is not yet set. This occurs
between other states and when SIO1 is not involved in a serial
transfer.
S1STA = 00H:This status code indicates that a bus error has occurred during an
SIO1 serial transfer. A bus error is caused when a START or STOP
condition occurs at an illegal position in the format frame. Examples
of such illegal positions are during the serial transfer of an address
byte, a data byte, or an acknowledge bit. A bus error may also be
caused when external interference disturbs the internal SIO1
signals. When a bus error occurs, SI is set. To recover from a bus
SDA and SCL lines are released (a STOP condition is not
transmitted).
Some Special Cases: The SIO1 hardware has facilities to handlethe following special cases that may occur during a serial transfer:
Simultaneous Repeated START Conditions from Two Masters
A repeated START condition may be generated in the master
transmitter or master receiver modes. A special case occurs if
another master simultaneously generates a repeated START
condition (see Figure 26). Until this occurs, arbitration is not lost by
either master since they were both transmitting the same data.
If the SIO1 hardware detects a repeated START condition on the I2C
bus before generating a repeated START condition itself, it will
release the bus, and no interrupt request is generated. If another
master frees the bus by generating a STOP condition, SIO1 will
transmit a normal START condition (state 08H), and a retry of the
total serial data transfer can commence.
DATA TRANSFER AFTER LOSS OF ARBITRATION
Arbitration may be lost in the master transmitter and master receiver
modes (see Figure 18). Loss of arbitration is indicated by the
following states in S1STA; 38H, 68H, 78H, and B0H (see Figures 22
and 23).
If the STA flag in S1CON is set by the routines which service these
states, then, if the bus is free again, a START condition (state 08H)
is transmitted without intervention by the CPU, and a retry of the
total serial transfer can commence.
FORCED ACCESS TO THE I2C BUS
In some applications, it may be possible for an uncontrolled source
to cause a bus hang-up. In such situations, the problem may be
caused by interference, temporary interruption of the bus or a
temporary short-circuit between SDA and SCL.
If an uncontrolled source generates a superfluous START or masks
a STOP condition, then the I2 C bus stays busy indefinitely. If the
STA flag is set and bus access is not obtained within a reasonable
amount of time, then a forced access to the I2 C bus is possible. This
is achieved by setting the STO flag while the STA flag is still set. No
STOP condition is transmitted. The SIO1 hardware behaves as if a
Philips Semiconductors Product data
P8xC660X2/661X280C51 8-bit microcontroller family 16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I2 C interfaces
Figure 26. Simultaneous Repeated START Conditions from 2 Masters
Figure 27. Forced Access to a Busy I2 C Bus2 C BUS OBSTRUCTED BY A LOW LEVEL ON SCL OR SDA
An I2 C bus hang-up occurs if SDA or SCL is pulled LOW by an
uncontrolled source. If the SCL line is obstructed (pulled LOW) by a
device on the bus, no further serial transfer is possible, and the
SIO1 hardware cannot resolve this type of problem. When this
occurs, the problem must be resolved by the device that is pulling
the SCL bus line LOW.
If the SDA line is obstructed by another device on the bus (e.g., a
slave device out of bit synchronization), the problem can be solved
by transmitting additional clock pulses on the SCL line (see Figure
28). The SIO1 hardware transmits additional clock pulses when the
STA flag is set, but no START condition can be generated because
the SDA line is pulled LOW while the I2C bus is considered free.
The SIO1 hardware attempts to generate a START condition after
every two additional clock pulses on the SCL line. When the SDA
line is eventually released, a normal START condition is transmitted,
state 08H is entered, and the serial transfer continues.
If a forced bus access occurs or a repeated START condition is
transmitted while SDA is obstructed (pulled LOW), the SIO1
hardware performs the same action as described above. In each
case, state 08H is entered after a successful START condition is
transmitted and normal serial transfer continues. Note that the CPU
is not involved in solving these bus hang-up problems.
BUS ERROR
A bus error occurs when a START or STOP condition is present at
an illegal position in the format frame. Examples of illegal positions
are during the serial transfer of an address byte, a data or an
acknowledge bit.
The SIO1 hardware only reacts to a bus error when it is involved in
a serial transfer either as a master or an addressed slave. When a
bus error is detected, SIO1 immediately switches to the not
addressed slave mode, releases the SDA and SCL lines, sets the
interrupt flag, and loads the status register with 00H. This status
code may be used to vector to a service routine which either
attempts the aborted serial transfer again or simply recovers from
the error condition as shown in Table 13.
