P89LPC933FDH-P89LPC934FDH-P89LPC936FDH Fast Delivery |IC PHOENIX CO.,LIMITED

P89LPC934FDH ,8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCsfeatures 4 kB/8 kB/16 kB byte-erasable flash code memory organized into 1 kB/2 kB sectors and 64-b ..
P89LPC935FA ,8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable Flash with 8-bit A/D convertersP89LPC933/934/9358-bit microcontroller with accelerated two-clock 80C51 core4 kB/8 kB 3 V byte-eras ..
P89LPC935FA ,8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable Flash with 8-bit A/D convertersfeatures■ 4 kB/8 kB byte-erasable Flash code memory organized into 1 kB sectors and64-byte pages. S ..
P89LPC935FDH ,8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable Flash with 8-bit A/D convertersGeneral descriptionThe P89LPC933/934/935 is a single-chip microcontroller, available in low costpac ..
P89LPC936FA ,8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCsfeatures■ 4 kB/8 kB/16 kB byte-erasable ﬂash code memory organized into 1 kB/2 kB sectorsand 64-byt ..
P89LPC936FA ,8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCsfeatures■ A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 nsfor all ..
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PCD3310T ,Pulse and DTMF diallers with redial
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PCD3311 ,DTMF/modem/musical-tone generators
PCD3312 ,DTMF/modem/musical-tone generators

P89LPC933FDH-P89LPC934FDH-P89LPC936FDH
8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs
1. General description
The P89LPC933/934/935/936 is a single-chip microcontroller, available in low cost
packages, based on a high performance processor architecture that executes instructions
in two to four clocks, six times the rate of standard 80C51 devices. Many system-level
functions have been incorporated into the P89LPC933/934/935/936 in order to reduce
component count, board space, and system cost.
2. Features and benefits
2.1 Principal features4 kB/8 kB/16 kB byte-erasable flash code memory organized into 1 kB/2 kB sectors
and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile
data storage. 256-byte RAM data memory. Both the P89LPC935 and P89LPC936 also include a
512-byte auxiliary on-chip RAM. 512-byte customer data EEPROM on chip allows serialization of devices, storage of
setup parameters, etc. (P89LPC935/936). Dual 4-input multiplexed 8-bit A/D converters/DAC outputs (P89LPC935/936, single
A/D on P89LPC933/934).Two analog comparators with selectable inputs and
reference source. Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output) and a 23-bit system timer that can also be used
as an RTC. Enhanced UART with fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I2 C-bus
communication port and SPI communication port. Capture/Compare Unit (CCU) provides PWM, input capture, and output compare
functions (P89LPC935/936). High-accuracy internal RC oscillator option allows operation without external oscillator
components. The RC oscillator option is selectable and fine tunable. 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V). 28-pin TSSOP, PLCC, and HVQFN packages with 23 I/O pins minimum and up to 26
I/O pins while using on-chip oscillator and reset options.
P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs
Rev. 8 — 12 January 2011 Product data sheet
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
2.2 Additional features A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns
for all instructions except multiply and divide when executing at 18 MHz. This is six
times the performance of the standard 80C51 running at the same clock frequency. A
lower clock frequency for the same performance results in power savings and reduced
EMI. Serial flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs. Serial flash In-System Programming (ISP) allows coding while the device is mounted
in the end application. In-Application Programming (IAP) of the flash code memory. This allows changing the
code in a running application. Watchdog timer with separate on-chip oscillator, requiring no external components.
The watchdog prescaler is selectable from eight values. Low voltage reset (brownout detect) allows a graceful system shutdown when power
fails. May optionally be configured as an interrupt. Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical power-down
current is 1 μA (total power-down with voltage comparators disabled). Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent spurious
and incomplete resets. A software reset function is also available. Configurable on-chip oscillator with frequency range options selected by user
programmed flash configuration bits. Oscillator options support frequencies from kHz to the maximum operating frequency of 18 MHz. Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function. Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only. Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern. LED drive capability (20 mA) on all port pins. A maximum limit is specified for the
entire chip. Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times. Only power and ground connections are required to operate the
P89LPC933/934/935/936 when internal reset option is selected. Four interrupt priority levels. Eight keypad interrupt inputs, plus two additional external interrupt inputs. Schmitt trigger port inputs. Second data pointer. Emulation support.
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
3. Product comparison overview
Table 1 highlights the differences between the four devices. For a complete list of device
features please see Section 2 “Features and benefits”.
4. Ordering information
4.1 Ordering options
Table 1. Product comparison overview
P89LPC933 4 kB 1 kB X - - -
P89LPC934 8 kB 1 kB X - - -
P89LPC935 8 kB 1 kB X X X X
P89LPC936 16 kB 2 kB X X X X
Table 2. Ordering information
P89LPC935FA PLCC28 plastic leaded chip carrier; 28 leads SOT261-2
P89LPC933HDH TSSOP28 plastic thin shrink small outline
package; 28 leads; body width 4.4 mm
SOT361-1
P89LPC933FDH
P89LPC934FDH
P89LPC935FDH
P89LPC936FDH
P89LPC935FHN HVQFN28 plastic thermal enhanced very thin
quad flat package; no leads; terminals; body6×6× 0.85 mm
SOT788-1
Table 3. Ordering options
P89LPC933HDH 4 kB −40 °Cto+125°C 0 MHzto18MHz
P89LPC933FDH 4kB −40 °Cto+85°C
P89LPC935FA 8kB
P89LPC934FDH
P89LPC935FDH
P89LPC935FHN
P89LPC936FDH 16kB
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
5. Block diagram
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
6. Pinning information
6.1 Pinning
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
6.2 Pin descriptionTable 4. Pin description
P0.0 to P0.7 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type.
During reset Port 0 latches are configured in the input only mode with the
internal pull-up disabled. The operation of Port 0 pins as inputs and
outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to Section 8.13.1 “Port configurations”
and Table 11 “Static characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt trigger inputs.
Port 0 also provides various special functions as described below:
P0.0/CMP2/
KBI0/AD01
327 I/O P0.0 — Port 0 bit0. CMP2 — Comparator 2 output. KBI0 — Keyboard input0. AD01 — ADC0 channel 1 analog input. (P89LPC935/936)
P0.1/CIN2B/
KBI1/AD10 22 I/O P0.1 — Port 0 bit1. CIN2B — Comparator 2 positive input B. KBI1 — Keyboard input1. AD10 — ADC1 channel 0 analog input.
P0.2/CIN2A/
KBI2/AD11 21 I/O P0.2 — Port 0 bit2. CIN2A — Comparator 2 positive input A. KBI2 — Keyboard input2. AD11 — ADC1 channel 1 analog input.
P0.3/CIN1B/
KBI3/AD12 20 I/O P0.3 — Port 0 bit3. CIN1B — Comparator 1 positive input B. KBI3 — Keyboard input3. AD12 — ADC1 channel 2 analog input.
P0.4/CIN1A/
KBI4/DAC1/
AD13 19 I/O P0.4 — Port 0 bit4. CIN1A — Comparator 1 positive input A. KBI4 — Keyboard input4. DAC1 — Digital-to-analog converter output 1. AD13 — ADC1 channel 3 analog input.
P0.5/
CMPREF/
KBI5 18 I/O P0.5 — Port 0 bit5. CMPREF — Comparator reference (negative) input. KBI5 — Keyboard input5.
P0.6/CMP1/
KBI6 16 I/O P0.6 — Port 0 bit6. CMP1 — Comparator 1 output. KBI6 — Keyboard input6.
P0.7/T1/
KBI7 15 I/O P0.7 — Port 0 bit7.
I/O T1 — Timer/counter 1 external count input or overflow output. KBI7 — Keyboard input7.
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
P1.0 to P1.7 I/O, I [1] Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type,
except for three pins as noted below. During reset Port 1 latches are
configured in the input only mode with the internal pull-up disabled. The
operation of the configurable Port 1 pins as inputs and outputs depends
upon the port configuration selected. Each of the configurable port pins
are programmed independently. Refer to Section 8.13.1 “Port
configurations” and Table 11 “Static characteristics” for details. P1.2 and
P1.3 are open drain when used as outputs. P1.5 is input only.
All pins have Schmitt trigger inputs.
Port 1 also provides various special functions as described below:
P1.0/TXD 18 14 I/O P1.0 — Port 1 bit0. TXD — Transmitter output for the serial port.
P1.1/RXD 17 13 I/O P1.1 — Port 1 bit1. RXD — Receiver input for the serial port.
P1.2/T0/SCL 12 8 I/O P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O T0 — Timer/counter 0 external count input or overflow output (open-drain
when used as output).
I/O SCL — I2 C serial clock input/output.
P1.3/INT0/
SDA 7 I/O P1.3 — Port 1 bit 3 (open-drain when used as output). INT0 — External interrupt 0 input.
I/O SDA — I2 C serial data input/output.
P1.4/INT1 10 6 I P1.4 — Port 1 bit4. INT1 — External interrupt 1 input.
P1.5/RST 62I P1.5 — Port 1 bit 5 (input only). RST — External reset input during power-on or if selected via UCFG1.
When functioning as a reset input, a LOW on this pin resets the
microcontroller, causing I/O ports and peripherals to take on their default
states, and the processor begins execution at address 0. Also used during
a power-on sequence to force ISP mode. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be
enabled. An external circuit is required to hold the device in reset at
power-up until VDD has reached its specified level. When system
power is removed VDD will fall below the minimum specified
operating voltage. When using an oscillator frequency above MHz, in some applications, an external brownout detect circuit
may be required to hold the device in reset when VDD falls below the
minimum specified operating voltage.
P1.6/OCB 5 1 I/O P1.6 — Port 1 bit6. OCB — Output Compare B. (P89LPC935/936)
P1.7/OCC/
AD00
428 I/O P1.7 — Port 1 bit7. OCC — Output Compare C. (P89LPC935/936) AD00 — ADC0 channel 0 analog input. (P89LPC935/936)
Table 4. Pin description …continued
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
P2.0 to P2.7 I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type.
During reset Port 2 latches are configured in the input only mode with the
internal pull-up disabled. The operation of Port 2 pins as inputs and
outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to Section 8.13.1 “Port configurations”
and Table 11 “Static characteristics” for details.
All pins have Schmitt trigger inputs.
Port 2 also provides various special functions as described below:
P2.0/ICB/
DAC0/AD03
125 I/O P2.0 — Port 2 bit0. ICB — Input Capture B. (P89LPC935/936) DAC0 — Digital-to-analog converter output. AD03 — ADC0 channel 3 analog input. (P89LPC935/936)
P2.1/OCD/
AD02
226 I/O P2.1 — Port 2 bit1. OCD — Output Compare D. (P89LPC935/936) AD02 — ADC0 channel 2 analog input. (P89LPC935/936)
P2.2/MOSI 13 9 I/O P2.2 — Port 2 bit2.
I/O MOSI — SPI master out slave in. When configured as master, this pin is
output; when configured as slave, this pin is input.
P2.3/MISO 14 10 I/O P2.3 — Port 2 bit3.
I/O MISO — When configured as master, this pin is input, when configured as
slave, this pin is output.
P2.4/SS 15 11 I/O P2.4 — Port 2 bit4. SS — SPI Slave select.
P2.5/
SPICLK 12 I/O P2.5 — Port 2 bit5.
I/O SPICLK — SPI clock. When configured as master, this pin is output; when
configured as slave, this pin is input.
P2.6/OCA 27 23 I/O P2.6 — Port 2 bit6. OCA — Output Compare A. (P89LPC935/936)
P2.7/ICA 28 24 I/O P2.7 — Port 2 bit7. ICA — Input Capture A. (P89LPC935/936)
Table 4. Pin description …continued
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.
P3.0 to P3.1 I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type.
During reset Port 3 latches are configured in the input only mode with the
internal pull-up disabled. The operation of Port 3 pins as inputs and
outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to Section 8.13.1 “Port configurations”
and Table 11 “Static characteristics” for details.
All pins have Schmitt trigger inputs.
Port 3 also provides various special functions as described below:
P3.0/XTAL2/
CLKOUT
95I/O P3.0 — Port 3 bit0. XTAL2 — Output from the oscillator amplifier (when a crystal oscillator
option is selected via the flash configuration. CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -
TRIM.6). It can be used if the CPU clock is the internal RC oscillator,
watchdog oscillator or external clock input, except when XTAL1/XTAL2
are used to generate clock source for the RTC/system timer.
P3.1/XTAL1 8 4 I/O P3.1 — Port 3 bit1. XTAL1 — Input to the oscillator circuit and internal clock generator circuits
(when selected via the flash configuration). It can be a port pin if internal
RC oscillator or watchdog oscillator is used as the CPU clock source, and
if XTAL1/XTAL2 are not used to generate the clock for the RTC/system
timer.
VSS 73I Ground: 0 V reference.
VDD 21 17 I Power supply: This is the power supply voltage for normal operation as
well as Idle and Power-down modes.
Table 4. Pin description …continued
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
7. Logic symbols
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
8. Functional description
Remark: Please refer to the P89LPC933/934/935/936 User manual for a more detailed
functional description.
8.1 Special function registers
Remark: SFR accesses are restricted in the following ways: User must not attempt to access any SFR locations not defined. Accesses to any defined SFR locations must be strictly for the functions for the SFRs. SFR bits labeled ‘-’, logic 0 or logic 1 can only be written and read as follows: ‘-’ Unless otherwise specified, must be written with logic 0, but can return any
value when read (even if it was written with logic 0). It is a reserved bit and may be
used in future derivatives. Logic 0 must be written with logic 0, and will return a logic 0 when read. Logic 1 must be written with logic 1, and will return a logic 1 when read.
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NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
ble 5.
l fun
tion
gister
s -
P89
PC9
33/934
dicates SFRs that
e bit
ddressab
le.
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NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
ble 5.
l fun
tion
gister
s -
P89
PC9
33/934
…continu
dicates SFRs that
e bit
ddressab
le.
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NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
ble 5.
l fun
tion
gister
s -
P89
PC9
33/934
…continu
dicates SFRs that
e bit
ddressab
le.
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NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
ble 5.
l fun
tion
gister
s -
P89
PC9
33/934
…continu
dicates SFRs that
e bit
ddressab
le.
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NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
nimplemented bit
in
Rs (labeled
are X (
unknown)
at all times. U
less other
wise specified, ones should not be wr
itte
to these bit
since
they ma
y be u
ed f
r other
pur
poses in futur
derivatives. The r
t values shown for
these bit
ar
0s alth
ough they are u
kno
n when r
ead.
RGR1 and
BRGR
0 must
only be w
ten if BR
GEN in BRGCON SFR
is
logic 0. If an
y ar
e written w
ile BRGEN
1, the r
sult is un
edict
able
ll por
are in input only (
h-impedance) st
ate af
ter pow
er-u
he RST
RC r
egister
flect
the
cause
of th
e P89LPC93
/934/
935/93
6 re
set.
Upon
a pow
er-u
p re
set,
all r
set source f
lags ar
cleared
except
POF
and
BOF
; the
powe
r-on
reset
valu
e is xx1
he only r
set
sour
ce
that af
fect
s these SF
Rs is power
-on r
set.
n power
-on r
set, the T
IM SFR is initialize
d with a factory
prepr
ogra
mmed va
lue. Other
reset
will not cause initializatio
n o
the TR
IM regist
t, the
value
is
01x1
, i.e.,
E2 to
PRE0
are
l logic
1, WDRUN
and
WDCLK
1. WDT
F bit is lo
gic
dog r
set and
is
logic
0 af
ter
power-
on
reset.
Other r
set
will not af
fect WDT
ble 5.
l fun
tion
gister
s -
P89
PC9
33/934
…continu
dicates SFRs that
e bit
ddressab
le.
xxx
xxx
xxxx
xxx
xxxx
xxx
xx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxx
xxx
x x
x
x x
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
x x
xxxx
xxx
xxx
xxxx
xxx
x xx
xx
xx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
xx x
xxx
xx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xxx
xxxx
xx
xxxx
xxx
xxx
x x
xxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xx
xxxx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
x xx
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
ble 6.
l fun
tion
gister
s -
P89
PC9
35/936
dicates SFRs that
e bit
ddressab
le.
xxx
xxx
xxxx
xxx
xxxx
xxx
xx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxx
xxx
x x
x
x x
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
x x
xxxx
xxx
xxx
xxxx
xxx
x xx
xx
xx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
xx x
xxx
xx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xxx
xxxx
xx
xxxx
xxx
xxx
x x
xxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xx
xxxx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
x xx
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
ble 6.
l fun
tion
gister
s -
P89
PC9
35/936
…continu
dicates SFRs that
e bit
ddressab
le.
xxx
xxx
xxxx
xxx
xxxx
xxx
xx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxx
xxx
x x
x
x x
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
x x
xxxx
xxx
xxx
xxxx
xxx
x xx
xx
xx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
xx x
xxx
xx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xxx
xxxx
xx
xxxx
xxx
xxx
x x
xxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xx
xxxx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
x xx
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
ble 6.
l fun
tion
gister
s -
P89
PC9
35/936
…continu
dicates SFRs that
e bit
ddressab
le.
xxx
xxx
xxxx
xxx
xxxx
xxx
xx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxx
xxx
x x
x
x x
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
x x
xxxx
xxx
xxx
xxxx
xxx
x xx
xx
xx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
xx x
xxx
xx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xxx
xxxx
xx
xxxx
xxx
xxx
x x
xxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xx
xxxx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
x xx
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
ble 6.
l fun
tion
gister
s -
P89
PC9
35/936
…continu
dicates SFRs that
e bit
ddressab
le.
xxx
xxx
xxxx
xxx
xxxx
xxx
xx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxx
xxx
x x
x
x x
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
x x
xxxx
xxx
xxx
xxxx
xxx
x xx
xx
xx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
xx x
xxx
xx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xxx
xxxx
xx
xxxx
xxx
xxx
x x
xxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xx
xxxx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
x xx
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
ble 6.
l fun
tion
gister
s -
P89
PC9
35/936
…continu
dicates SFRs that
e bit
ddressab
le.
xxx
xxx
xxxx
xxx
xxxx
xxx
xx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxx
xxx
x x
x
x x
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
x x
xxxx
xxx
xxx
xxxx
xxx
x xx
xx
xx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
xx x
xxx
xx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xxx
xxxx
xx
xxxx
xxx
xxx
x x
xxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xx
xxxx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
x xx
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
nimplemented bit
in
Rs (labeled
are X (
unknown)
at all times. U
less other
wise specified, ones should not be wr
itte
to these bit
since
they ma
y be u
ed f
r other
pur
poses in futur
derivatives. The r
t values shown for
these bit
ar
0s alth
ough they are u
kno
n when r
ead.
ll por
are in input only (
h-impedance) st
ate af
ter pow
er-u
RGR1 and
BRGR
0 must
only be w
ten if BR
GEN in BRGCON SFR
is
logic 0. If an
y ar
e written w
ile BRGEN
1, the r
sult is un
edict
able
he RST
RC r
egister
flect
the
cause
of th
e P89LPC93
/934/
935/93
6 re
set.
Upon
a pow
er-u
p re
set,
all r
set source f
lags ar
cleared
except
POF
and
BOF
; the
powe
r-on
reset
valu
e is xx1
t, the
value
is
01x1
, i.e.,
E2 to
PRE0
are
l logic
1, WDRUN
and
WDCLK
1. WDT
F bit is lo
gic
dog r
set and
is
logic
0 af
ter
power-
on
reset.
Other r
set
will not af
fect WDT
n power
-on r
set, the T
IM SFR is initialize
d with a factory
prepr
ogra
mmed va
lue. Other
reset
will not cause initializatio
n o
the TR
IM regist
he only r
set
sour
ce
that af
fect
s these SF
Rs is power
-on r
set.
ble 6.
l fun
tion
gister
s -
P89
PC9
35/936
…continu
dicates SFRs that
e bit
ddressab
le.
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
8.2 Enhanced CPU
The P89LPC933/934/935/936 uses an enhanced 80C51 CPU which runs at six times the
speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and
most instructions execute in one or two machine cycles.
8.3 Clocks
8.3.1 Clock definitions
The P89LPC933/934/935/936 device has several internal clocks as defined below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock
sources (see Figure 8) and can also be optionally divided to a slower frequency (see
Section 8.8 “CCLK modification: DIVM register”).
Remark: fosc is defined as the OSCCLK frequency.
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine
cycle, and most instructions are executed in one to two machine cycles (two or four CCLK
cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.
PCLK — Clock for the various peripheral devices and is CCLK⁄2.
8.3.2 CPU clock (OSCCLK)
The P89LPC933/934/935/936 provides several user-selectable oscillator options in
generating the CPU clock. This allows optimization for a range of needs from high
precision to lowest possible cost. These options are configured when the flash is
programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an
oscillator using an external crystal, or an external clock source. The crystal oscillator can
be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to MHz.
8.3.3 Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this configuration.
8.3.4 Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this configuration.
8.3.5 High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this configuration.
8.3.6 Clock output
The P89LPC933/934/935/936 supports a user-selectable clock output function on the
XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if
another clock source has been selected (on-chip RC oscillator, watchdog oscillator,
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
external clock input on X1) and if the RTC is not using the crystal oscillator as its clock
source. This allows external devices to synchronize to the P89LPC933/934/935/936. This
output is enabled by the ENCLK bit in the TRIM register.
The frequency of this clock output is 1 ⁄2 that of the CCLK. If the clock output is not needed
in Idle mode, it may be turned off prior to entering Idle, saving additional power.
8.4 On-chip RC oscillator option
The P89LPC933/934/935/936 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
preprogrammed value to adjust the oscillator frequency to 7.373 MHz±1 % at room
temperature. End-user applications can write to the TRIM register to adjust the on-chip
RC oscillator to other frequencies.
8.5 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator
can be used to save power when a high clock frequency is not needed.
8.6 External clock input option
In this configuration, the processor clock is derived from an external source driving the
P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2 pin may be
used as a standard port pin or a clock output. When using an oscillator frequency
above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit
is required to hold the device in reset at power-up until VDD has reached its
specified level. When system power is removed VDD will fall below the minimum
specified operating voltage. When using an oscillator frequency above 12 MHz, in
some applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specified operating voltage.
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
8.7 CCLK wake-up delay
The P89LPC933/934/935/936 has an internal wake-up timer that delays the clock until it
stabilizes depending on the clock source used. If the clock source is any of the three
crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles
plus 60 μsto100 μs. If the clock source is either the internal RC oscillator, watchdog
oscillator, or external clock, the delay is 224 OSCCLK cycles plus 60μsto 100 μs.
8.8 CCLK modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
8.9 Low power select
The P89LPC933/934/935/936 is designed to run at 18 MHz (CCLK) maximum. However,
if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower
the power consumption further. On any reset, CLKLP is logic 0 allowing highest
performance access. This bit can then be set in software if CCLK is running at 8 MHz or
slower.
8.10 Memory organization
The various P89LPC933/934/935/936 memory spaces are as follows: DATA
128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area. IDATA
Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area. This area includes the DATA area and the 128 bytes
immediately above it. SFR
Selected CPU registers and peripheral control and status registers, accessible only
via direct addressing. XDATA (P89LPC935/936)
‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space
addressed via the MOVX instruction using the SPTR, R0, or R1. All or part of this
space could be implemented on-chip. The P89LPC935/936 has 512 bytes of on-chip
XDATA memory.
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core CODE kB of code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC933/934/935/936 have 4 KB/8 kB/16 kB of on-chip
Code memory.
The P89LPC935/936 also has 512 bytes of on-chip data EEPROM that is accessed via
SFRs (see Section 8.27 “Data EEPROM (P89LPC935/936)”).
8.11 Data RAM arrangement
The 768 bytes of on-chip RAM are organized as shown in Table7.
8.12 Interrupts
The P89LPC933/934/935/936 uses a four priority level interrupt structure. This allows
great flexibility in controlling the handling of the many interrupt sources. The
P89LPC933/934/935/936 supports 15 interrupt sources: external interrupts 0 and 1,
timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout detect,
watchdog/Real-Time clock, I2 C-bus, keyboard, comparators 1 and 2, SPI, CCU, data
EEPROM write/ADC completion.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in
the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global
disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt, but
not by another interrupt of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. If two requests of different priority
levels are pending at the start of an instruction, the request of higher priority level is
serviced.
If requests of the same priority level are pending at the start of an instruction, an internal
polling sequence determines which request is serviced. This is called the arbitration
ranking.
Remark: The arbitration ranking is only used to resolve pending requests of the same
priority level.
8.12.1 External interrupt inputs
The P89LPC933/934/935/936 has two external interrupt inputs as well as the Keypad
Interrupt function. The two interrupt inputs are identical to those present on the standard
80C51 microcontrollers.
Table 7. On-chip data memory usages
DATA Memory that can be addressed directly and indirectly 128
IDATA Memory that can be addressed indirectly 256
XDATA Auxiliary (‘External Data’) on-chip memory that is accessed
using the MOVX instructions (P89LPC935/936)
512
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
These external interrupts can be programmed to be level-triggered or edge-triggered by
setting or clearing bit IT1 or IT0 in register TCON.
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle
and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an
interrupt request.
If an external interrupt is enabled when the P89LPC933/934/935/936 is put into
Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume
operation. Refer to Section 8.15 “Power reduction modes” for details.
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
8.13 I/O ports
The P89LPC933/934/935/936 has four I/O ports: Port 0, Port 1, Port 2, and Port3.
Ports 0, 1 and 2 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins
available depends upon the clock and reset options chosen, as shown in Table8.
[1] Required for operation above 12 MHz.
8.13.1 Port configurations
All but three I/O port pins on the P89LPC933/934/935/936 may be configured by software
to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51
port outputs), push-pull, open drain, and input-only. Two configuration registers for each
port select the output type for each port pin. P1.5 (RST) can only be an input and cannot be configured. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or
open-drain.
8.13.1.1 Quasi-bidirectional output configuration
Quasi-bidirectional output type can be used as both an input and output without the need
to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similar to an open-drain output except that there are three pull-up transistors in
the quasi-bidirectional output that serve different purposes.
The P89LPC933/934/935/936 is a 3 V device, but the pins are 5 V-tolerant. In
quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing
from the pin to VDD, causing extra power consumption. Therefore, applying 5 V in
quasi-bidirectional mode is discouraged.
A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
8.13.1.2 Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output, a port configured in this manner must have an external pull-up, typically a resistor
tied to VDD.
Table 8. Number of I/O pins available
On-chip oscillator or watchdog
oscillator
No external reset (except during
power-up)
External RST pin supported 25
External clock input No external reset (except during
power-up)
External RST pin supported[1] 24
Low/medium/high speed oscillator
(external crystal or resonator)
No external reset (except during
power-up)
External RST pin supported[1] 23
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
An open-drain port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
8.13.1.3 Input-only configuration
The input-only port configuration has no output drivers. It is a Schmitt trigger input that
also has a glitch suppression circuit.
8.13.1.4 Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous strong
pull-up when the port latch contains a logic 1. The push-pull mode may be used when
more source current is needed from a port output. A push-pull port pin has a Schmitt
trigger input that also has a glitch suppression circuit.
8.13.2 Port 0 analog functions
The P89LPC933/934/935/936 incorporates two Analog Comparators. In order to give the
best analog function performance and to minimize power consumption, pins that are being
used for analog functions must have the digital outputs and digital inputs disabled.
Digital outputs are disabled by putting the port output into the Input-Only
(high-impedance) mode.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5.
On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions.
8.13.3 Additional port features
After power-up, all pins are in Input-Only mode.
Remark: Please note that this is different from the LPC76x series of devices. After power-up, all I/O pins except P1.5, may be configured by software. Pin P1.5 is input only. Pins P1.2 and P1.3 and are configurable for either input-only or
open-drain.
Every output on the P89LPC933/934/935/936 has been designed to sink typical LED
drive current. However, there is a maximum total output current for all ports which must
not be exceeded. Please refer to Table 11 “Static characteristics” for detailed
specifications.
All ports pins that can function as an output have slew rate controlled outputs to limit noise
generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
8.14 Power monitoring functions
The P89LPC933/934/935/936 incorporates power monitoring functions designed to
prevent incorrect operation during initial power-up and power loss or reduction during
operation. This is accomplished with two hardware functions: Power-on detect and
brownout detect.
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
8.14.1 Brownout detection
The brownout detect function determines if the power supply voltage drops below a
certain level. The default operation is for a brownout detection to cause a processor reset,
however it may alternatively be configured to generate an interrupt.
Brownout detection may be enabled or disabled in software.
If brownout detection is enabled the brownout condition occurs when VDD falls below the
brownout trip voltage, Vbo (see Table 11 “Static characteristics”), and is negated when VDD
rises above Vbo. If the P89LPC933/934/935/936 device is to operate with a power supply
that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device
can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from
operating.
For correct activation of brownout detect, the VDD rise and fall times must be observed.
Please see Table 11 “Static characteristics” for specifications.
8.14.2 Power-on detection
The power-on detect has a function similar to the brownout detect, but is designed to work
as power comes up initially, before the power supply voltage reaches a level where
brownout detect can work. The POF flag in the RSTSRC register is set to indicate an
initial power-up condition. The POF flag will remain set until cleared by software.
8.15 Power reduction modes
The P89LPC933/934/935/936 supports three different power reduction modes. These
modes are Idle mode, Power-down mode, and total Power-down mode.
8.15.1 Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle
mode.
8.15.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption. The
P89LPC933/934/935/936 exits Power-down mode via any reset, or certain interrupts. In
Power-down mode, the power supply voltage may be reduced to the RAM keep-alive
voltage VRAM. This retains the RAM contents at the point where Power-down mode was
entered. SFR contents are not guaranteed after VDD has been lowered to VDDR, therefore
it is highly recommended to wake-up the processor via reset in this case. VDD must be
raised to within the operating range before the Power-down mode is exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during power-down. These include: brownout detect,
watchdog timer, Comparators (note that Comparators can be powered-down separately),
and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator
has been selected as the system clock and the RTC is enabled.
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
8.15.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry and
the voltage comparators are also disabled to conserve additional power. The internal RC
oscillator is disabled unless both the RC oscillator has been selected as the system clock
and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during
power-down, there will be high power consumption. Please use an external low frequency
clock to achieve low power with the RTC running during power-down.
8.16 Reset
The P1.5/RST pin can function as either a LOW-active reset input or as a digital input,
P1.5. The Reset Pin Enable (RPE) bit in UCFG1, when set to logic 1, enables the external
reset input function on P1.5. When cleared, P1.5 may be used as an input pin.
Remark: During a power-up sequence, the RPE selection is overridden and this pin will
always functions as a reset input. An external circuit connected to this pin should not
hold this pin LOW during a power-on sequence as this will keep the device in reset.
After power-up this input will function either as an external reset input or as a digital input
as defined by the RPE bit. Only a power-up reset will temporarily override the selection
defined by RPE bit. Other sources of reset will not override the RPE bit. When this pin
functions as a reset input, an internal pull-up resistance is connected (see Table 11 “Static
characteristics”).
Reset can be triggered from the following sources: External reset pin (during power-up or if user configured via UCFG1). Power-on detect. Brownout detect. Watchdog timer. Software reset. UART break character detect reset.
For every reset source, there is a flag in the reset register, RSTSRC. The user can read
this register to determine the most recent reset source. These flag bits can be cleared in
software by writing a logic 0 to the corresponding bit. More than one flag bit may be set: During a power-on reset, both POF and BOF are set but the other flag bits are
cleared. For any other reset, previously set flag bits that have not been cleared will remain set.
8.16.1 Reset vector
Following reset, the P89LPC933/934/935/936 will fetch instructions from either address
0000H or the boot address. The boot address is formed by using the boot vector as the
high byte of the address and the low byte of the address= 00H.
The boot address will be used if a UART break reset occurs, or the non-volatile boot
status bit (BOOTSTAT.0)= 1, or the device is forced into ISP mode during power-on (see
P89LPC933/934/935/936 User manual). Otherwise, instructions will be fetched from
address 0000H.
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
8.17 Timers/counters 0 and 1
The P89LPC933/934/935/936 has two general purpose counter/timers which are upward
compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to
operate either as timers or event counter. An option to automatically toggle the T0 and/or
T1 pins upon timer overflow has been added.
In the ‘timer’ function, the register is incremented every machine cycle.
In the ‘counter’ function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
once during every machine cycle.
Timer 0 and Timer 1 have five operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1, 2
and 6 are the same for both timers/counters. Mode 3 is different.
8.17.1 Mode0
Putting either timer into Mode 0 makes it look like an 8048 timer, which is an 8-bit counter
with a divide-by-32 prescaler. In this mode, the timer register is configured as a 13-bit
register. Mode 0 operation is the same for Timer 0 and Timer1.
8.17.2 Mode1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
8.17.3 Mode2
Mode 2 configures the timer register as an 8-bit counter with automatic reload. Mode2
operation is the same for Timer 0 and Timer1.
8.17.4 Mode3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit
counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is
in Mode 3 it can still be used by the serial port as a baud rate generator.
8.17.5 Mode6
In this mode, the corresponding timer can be changed to a PWM with a full period of
256 timer clocks.
8.17.6 Timer overflow toggle output
Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer
overflow occurs. The same device pins that are used for the T0 and T1 count inputs are
also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first
timer overflow when this mode is turned on.
8.18 RTC/system timer
The P89LPC933/934/935/936 has a simple RTC that allows a user to continue running an
accurate timer while the rest of the device is powered-down. The RTC can be a wake-up
or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler
and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be
reloaded again and the RTCF flag will be set. The clock source for this counter can be
either the CPU clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
not being used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then the
RTC will use CCLK as its clock source. Only power-on reset will reset the RTC and its
associated SFRs to the default state.
8.19 CCU (P89LPC935/936)
This unit features: A 16-bit timer with 16-bit reload on overflow. Selectable clock, with prescaler to divide clock source by any integral number
between 1 and 1024. Four compare/PWM outputs with selectable polarity. Symmetrical/asymmetrical PWM selection. Two capture inputs with event counter and digital noise rejection filter. Seven interrupts with common interrupt vector (one overflow, two capture,
four compare). Safe 16-bit read/write via shadow registers.
8.19.1 CCU clock
The CCU runs on the CCUCLK, which is either PCLK in basic timer mode, or the output of
a Phase-Locked Loop (PLL). The PLL is designed to use a clock source between 0.5 MHz
to 1 MHz that is multiplied by 32 to produce a CCUCLK between 16 MHz and 32 MHz in
PWM mode (asymmetrical or symmetrical). The PLL contains a 4-bit divider to help divide
PCLK into a frequency between 0.5 MHz and 1 MHz.
8.19.2 CCUCLK prescaling
This CCUCLK can further be divided down by a prescaler. The prescaler is implemented
as a 10-bit free-running counter with programmable reload at overflow.
8.19.3 Basic timer operation
The timer is a free-running up/down counter with a direction control bit. If the timer
counting direction is changed while the counter is running, the count sequence will be
reversed. The timer can be written or read at any time.
When a reload occurs, the CCU Timer Overflow Interrupt Flag will be set, and an interrupt
generated if enabled. The 16-bit CCU timer may also be used as an 8-bit up/down timer.
8.19.4 Output compare
There are four output compare channels A, B, C and D. Each output compare channel
needs to be enabled in order to operate and the user will have to set the associated I/O
pin to the desired output mode to connect the pin. When the contents of the timer matches
that of a capture compare control register, the Timer Output Compare Interrupt Flag
(TOCFx) becomes set. An interrupt will occur if enabled.
8.19.5 Input capture
Input capture is always enabled. Each time a capture event occurs on one of the two input
capture pins, the contents of the timer is transferred to the corresponding 16-bit input
capture register. The capture event can be programmed to be either rising or falling edge
triggered. A simple noise filter can be enabled on the input capture by enabling the Input
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
Capture Noise Filter bit. If set, the capture logic needs to see four consecutive samples of
the same value in order to recognize an edge as a capture event. An event counter can be
set to delay a capture by a number of capture events.
8.19.6 PWM operation
PWM operation has two main modes, symmetrical and asymmetrical.
In asymmetrical PWM operation the CCU timer operates in down-counting mode
regardless of the direction control bit.
In symmetrical mode, the timer counts up/down alternately. The main difference from
basic timer operation is the operation of the compare module, which in PWM mode is
used for PWM waveform generation.
As with basic timer operation, when the PWM (compare) pins are connected to the
compare logic, their logic state remains unchanged. However, since bit FCO is used to
hold the halt value, only a compare event can change the state of the pin.
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
8.19.7 Alternating output mode
In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating
pairs for bridge drive control. In this mode the output of these PWM channels are
alternately gated on every counter cycle.
8.19.8 PLL operation
The PWM module features a PLL that can be used to generate a CCUCLK frequency
between 16 MHz and 32 MHz. At this frequency the PWM module provides ultrasonic
PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or
higher. The PLL is fed an input signal from 0.5 MHz to 1 MHz and generates an output
signal of 32 times the input frequency. This signal is used to clock the timer. The user will
have to set a divider that scales PCLK by a factor from 1 to 16. This divider is found in the
SFR register TCR21. The PLL frequency can be expressed as shown in Equation1.
(1)
Where: N is the value of PLLDV.3 to PLLDV.0.
Since N ranges from 0to 15, the CCLK frequency can be in the range of PCLK to PCLK⁄16.
PLL frequency PCLK+()------------------=
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
8.19.9 CCU interrupts
There are seven interrupt sources on the CCU which share a common interrupt vector.
8.20 UART
The P89LPC933/934/935/936 has an enhanced UART that is compatible with the
conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate
source. The P89LPC933/934/935/936 does include an independent baud rate generator.
The baud rate can be selected from the oscillator (divided by a constant), Timer1
overflow, or the independent baud rate generator. In addition to the baud rate generation,
enhancements over the standard 80C51 UART include Framing Error detection,
automatic address recognition, selectable double buffering and several interrupt options.
The UART can be operated in four modes: shift register, 8-bit UART, 9-bit UART, and CPU
clock ⁄32 or CPU clock⁄16.
8.20.1 Mode0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at 1 ⁄16 of the CPU clock
frequency.
NXP Semiconductors P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
8.20.2 Mode1 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored
in RB8 in special function register SCON. The baud rate is variable and is determined by
the Timer 1 overflow rate or the baud rate generator (described in Section 8.20.5 “Baud
rate generator and selection”).
8.20.3 Mode2 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data
bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is
transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of logic 0 or logic1.
Or, for example, the parity bit (P , in the PSW) could be moved into TB8. When data is
received, the 9th data bit goes into RB8 in special function register SCON, while the stop
bit is not saved. The baud rate is programmable to either 1 ⁄16 or 1 ⁄32 of the CPU clock
frequency, as determined by the SMOD1 bit in PCON.
8.20.4 Mode3 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is
the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable
and is determined by the Timer 1 overflow rate or the baud rate generator (described in
Section 8.20.5 “Baud rate generator and selection”).
8.20.5 Baud rate generator and selection
The P89LPC933/934/935/936 enhanced UART has an independent baud rate generator.
The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0
SFRs which together form a 16-bit baud rate divisor value that works in a similar manner
as Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be
used for other timing functions.
The UART can use either Timer 1 or the baud rate generator output (see Figure 14). Note
that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent baud rate generator uses CCLK.
8.20.6 Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)
is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is
logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up
when SMOD0 is logic 0.

Partno	Mfg	Dc	Qty	Available	Descript
P89LPC933FDH	NXP	N/a	235	avai	8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs
P89LPC934FDH	NXP	N/a	2500	avai	8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs
P89LPC936FDH	NXP Pb-free	N/a	2007	avai	8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/16 kB 3 V byte-erasable flash with 8-bit ADCs