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PC87415VCG
PCI-IDE DMA Master Mode Interface Controller
TL/F/12497
PC87415
PCI-IDE
DMA
Master
Mode
Interface
Controller
PRELIMINARY
March 1996
PC87415
PCI-IDE DMA Master Mode Interface Controller
1.0 General Description
The Enhanced PCI-IDE Interfaceisa single-chip controller
packagedina 100-pin PQFP.It provides2IDE channelsfor
interfacingupto4IDE drives,or2IDE drivesand CD-ROM
directlyonthePCI Local bus.An enhanced DMA controller
on-chip increases system performanceby providingfull
scatter/gather data transfers betweenIDE devicesandsys-
tem memory without CPU intervention. Four levelsof both
write posting and read prefetchingper channel allowthe
host CPUtorun concurrently withIDE cycles. Programma-
bletiming functions provide maximum flexibilityof timingpa-
rametersper drivefor optimizingthe data transfer rateper
drive. BothPC compatible addressing and PCI compliant
addressingare supportedby re-mappingthe base address-
es.A power control feature allows turningoff powertothe
IDE cables.
The Enhanced PCI-IDE Interface connectiontothePCIbus virtually ‘‘glue-less’’, with only one additional TTL data
buffer (optional). This high-integration solution reduces
component count, eases board design, reduces costand
increases reliability.
The Enhanced PCI-IDE supports faster ATA devices using
PIO modes1,2,3,and4aswellas DMA modes0,1,and2. comes withafull suiteof software driversfor DOS 5.0–
6.x, WindowsÉ 3.x, WindowsÉ95, Windows NTTM, OS/2
2.x, NovellÉ NetWareTM 3.1x–4.x,and SCO UNIXÉ3.x.
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
WATCHDOGTMisa trademarkof National SemiconductorCorporation.
NovellÉisa registeredtrademarkof Novell,Inc.
NetWareTMisa trademark ofNovell,Inc.
UnixÉisaregistered trademarkofAT&TBell Laboratories.
WindowsÉand WindowsÉ95are registeredtrademarksof Microsoft Corporation.
Windows NTTMisa trademark ofMicrosoftCorporation.
2.0 Features PCIbus interfaceforupto4IDE devices33 MHz, 32-bit PCIbus data path withfull parity error
reporting 16.7 MByte/sec maximumIDE transfer rate Supportfor2IDE channels(@2IDE devicesper chan-
nel) Primaryor secondary IDE addressing (1F0x/170x)in compatible mode Re-mappable base registersforfullPCI compliance Concurrent channel operation (PIO& DMA modes)4 Double Word write FIFOper channel4 Double Word read prefetch FIFOper channel Enhanced DMA mode with scatter/gather capability ANSI ATA Modes0 through4 PIO support (internal
DMAnot selected) IORDY handshakingforPIO ANSI ATA Modes0 through2 Multiword DMA support
(internal DMA selected) Individually programmable command and recovery tim-
ingfor reads and writesper channel/drivefor com-
mand, controland data Individually programmable data sector sizefor read pre-
fetchesper channelPC compatible interrupt routingof IRQ14 and IRQ15 Hardwareand software chip enable/disable Optional Power ControlforIDE Drives Fully static logic design 100-pin PQFP package
TL/F/12497–1
FIGURE 1.The PC87415inaPCI Based System
C1996National SemiconductorCorporation RRD-B30M46/Printed inU.S.A. http://
