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PCA24S08ADP
1024 x 8-bit CMOS EEPROM with access protection
General descriptionThe PCA24S08A provides 8192 bits of serial Electrically Erasable and Programmable
Read-Only Memory (EEPROM) organized as 1024 words of 8 bits each. Data bytes are
received and transmitted via the serial I2 C-bus.
Access permissions limiting reads or writes are set via the I2 C-bus to isolate blocks of
memory from improper access.
The PCA24S08A is intended to be pin compatible with standard 24C08 serial EEPROM
devices except for pins 1, 2, and 3, which are address pins in the standard part. Other
exceptions to the PCA24S08A serial EEPROM data sheet are noted in Section 6.6.
All bits are sent to or read from the device, most significant bit first, in a manner consistent
with the 24C08 serial EEPROM. The bit fields in this document are correspondingly listed
with the MSB on the left and the LSB on the right.
The EEPROM memory is broken up into 8 blocks of 1 kbit (128 bytes) each. Within each
block, the memory is physically organized in to 8 pages of 128 bits (16 bytes) each. In
addition to these 8 kbits, there are two more 128-bit pages that are used to store the
access protection and ID information. There are a total of 8448 bits of EEPROM memory
available in the PCA24S08A.
Access protection (both read and write) is organized on a block basis for block 1 through
block 7 and on a page and a block basis for block 0. Protection information for these
blocks and pages is stored in one of the additional pages of EEPROM memory that is
addressed separately from the main data storage array. SeeSection 6.4 for more details.
The ID value is located in the ID page of the EEPROM, the second of the additional byte pages.
Writes from the serial interface may include from one byte to 16 bytes at a time,
depending on the protocol followed by the bus master. All page accesses must be
properly aligned to the internal EEPROM page.
The EEPROM memory offers an endurance of 100,000 write cycles per byte, with 10 year
data retention. Writes to the EEPROM take less than 5 ms to complete.
After manufacturing, all EEPROM bits will be set to a value of ‘1’.
PCA24S08A
1024 × 8-bit CMOS EEPROM with access protection
Rev. 01 — 19 January 2010 Product data sheet
NXP Semiconductors PCA24S08A
1024 × 8-bit CMOS EEPROM with access protection Features Non-volatile storage of 8 kbits organized as 8 blocks of 128 bytes eachI2 C-bus interface logic Compatible with 24C08 serial EEPROM, and alternate source of Atmel AT24RF08C
without the RF interface Write operation: Byte write mode 16-byte page write mode Read operation: Sequential read Random read Programmable access protection to limit reads and writes Lock/unlock function Write protect feature protecting the full memory array against write operations Self timed write cycle Internal power-on reset High reliability:T en years non-volatile data retention time 100,000 write cycle endurance Low power CMOS technology Operating power supply voltage range of 2.5 V to 3.6V0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8, TSSOP8
Ordering informationTable 1. Ordering informationTamb= −40 °C to +85°C
PCA24S08AD P24S08A SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PCA24S08ADP PS08A TSSOP8 plastic thin shrink small outline package; 8 leads; body width3 mm SOT505-1
NXP Semiconductors PCA24S08A
1024 × 8-bit CMOS EEPROM with access protection Block diagram Pinning information
5.1 Pinning
NXP Semiconductors PCA24S08A
1024 × 8-bit CMOS EEPROM with access protection
5.2 Pin description Functional descriptionRefer to Figure 1 “Block diagram”.
6.1 Device addressingFollowing a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA24S08A is shown in Figure4.
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read operation is selected, while logic 0 selects a write operation. Bits B2 and B1
in the slave address represent the 2 most significant bits of the word to be addressed. The
third device address bit in the I2 C-bus protocol that is usually matched to A2 (pin 3) on a
standard 24C08 serial EEPROM is internally connected HIGH, so device addresses A8h
through AFh (hex) are used to access the memory on the chip.
6.2 Write operationsWrite operations on the device can be performed only when WP is held LOW. When the
WP pin is held HIGH, content of the full memory is protected (Block 0 to Block7,
APP registers, ID Page), and no write operation is allowed.
6.2.1 Byte/word writeWrite command may be used to set the address for a subsequent Read command. For a
write operation, the PCA24S08A requires a second address field. The address field
associated with the two software selectable bits in the slave address is a word address
providing access to the 1024 bytes of memory, as shown in Figure 5. Upon receipt of the
word address, the PCA24S08A responds with an acknowledge and awaits the next 8 bits
Table 2. Pin descriptionn.c. 1, 2 not connected
PROT 3 active LOW protect reset input
VSS 4 ground supply voltage
SDA 5 serial data; open-drain I/O
SCL 6 serial clock; open-drain input 7 active HIGH write protect input
VDD 8 supply voltage
NXP Semiconductors PCA24S08A
1024 × 8-bit CMOS EEPROM with access protectionFigure 6 shows how the memory array is addressed when the slave address byte and
address field byte are sent. The master terminates the transfer by generating a STOP
condition. After this STOP condition, the Erase/Write (E/W) cycle starts and the I2 C-bus is
free for another transmission. Up to 16 bytes of data can be written in the slave writing
sequence (E/W cycle).
NXP Semiconductors PCA24S08A
1024 × 8-bit CMOS EEPROM with access protectionThe general command encoding used by the serial port for EEPROM accesses is shown
in Figure 11, where B[2:0] is the block number, P[2:0] is the page number within the block
and A[3:0] is the byte address within the page. Bits denoted as ‘X’ are ignored by the
device.
6.2.2 Page writeThe PCA24S08A is capable of a 16-byte page write operation. It is initiated in the same
manner as the byte write operation. The master can transit 16 data bytes within one
transmission. After receipt of each byte, the PCA24S08A will respond with an
acknowledge. The typical E/W time in this mode is 5 ms.
After the receipt of each data byte, the four low-order bits of the word address are
internally incremented. The six high-order bits of the address remain unchanged. The
slave acknowledges the reception of each data byte with an ACK. The I2 C-bus data
transfer is terminated by the master after the 16th byte of data with a STOP condition.
After a write to the last byte in a page, the internal address is wrapped around to point to
the beginning of that page. If the master transmits more than 16 bytes prior to generating
the STOP condition, no acknowledge will be given on the 17th (and following) data bytes
and the whole transmission will be ignored and no programming will be done. As in the
byte write operation, all inputs are disabled until completion of the internal write cycles.
After this STOP condition, the E/W cycle starts and the I2 C-bus is free for another
transmission.
During the E/W cycle the slave receiver does not acknowledge if addressed via the 2 C-bus.
NXP Semiconductors PCA24S08A
1024 × 8-bit CMOS EEPROM with access protection
6.3 Read operationsRead operations are initiated in the same manner as write operations with the exception
that the LSB of the slave address is set to logic1.
The lower 7 bits of the word address are incremented after each transmission of a data
byte during a read. The three MSBs of the word address are not changed when the word
counter overflows. Thus, the word address overflows from 127 to 0, and from 255 to 128.
After the read of the last byte within a block, the internal serial address wraps around to
point at the beginning of that block.
NXP Semiconductors PCA24S08A
1024 × 8-bit CMOS EEPROM with access protection
6.4 Access protectionWrite operation on the Access protection registers can be performed when WP pin is
LOW. If the WP pin is HIGH, all write operations are prohibited from the serial port,
although write commands may be used to set the address for a subsequent read
command.
All access protection bits are stored on a separate page of the EEPROM that is not
accessed using the normal commands of a PCA24S08A memory. See Section 6.4.2.2
“Access Protection Page (APP)” for more detail on this information.
6.4.1 RFID access fields (RF)Even though the PCA24S08A does not have the RFID capability, RFID access fields (RF)
can be stored in order to keep existing software compatibility. The fields are stored in the
EEPROM and organized as shown in Table3.
6.4.2 Protection bits (PB)The protection bits fields in the Access Protection Page determine what type of accesses
will be permitted via the serial port for each of the blocks on the chip. If an illegal access is
attempted, the command will be NACKed. The MSB (if clear) prohibits all access to the
block, and the LSB (if clear) prohibits writes. The fields are stored in the EEPROM and are
organized as shown in Table4.
Table 3. RFID access field organization 0 no accesses permitted from RFID port 1 no accesses permitted from RFID port 0 read only from RFID port 1 no restrictions for RFID accesses
Table 4. PB organization 0 no accesses permitted in the block 1 no accesses permitted in the block 0 read only; writes cause a NACK
NXP Semiconductors PCA24S08A
1024 × 8-bit CMOS EEPROM with access protectionAccessed within the Access Protection Page is an individual CMOS Sticky Bit (SB) for
each of the 8 blocks on the device. When the value of the sticky bit is ‘0’, the Protection
Bits (PB) for the corresponding block may not be changed via the software. These bits are
all set to logic 1 when power is initially applied or when the PROT pin is LOW. These
sticky bits may be written only to a ‘0’ via the serial interface using the standard serial write
operations. Reading the sticky bits does not affect their state.
Because permissions are set individually for each of the blocks, all reads via serial port
will only read bytes within the block that was specified when the current address was
latched in the device (with a write command). The block address bits (B2 or B1) that are
sent with the write command are ignored on a read command.
When a sticky bit is cleared (programmed at 0), the byte containing the sticky bit cannot
be changed anymore. If a write operation to this byte is attempted, it will be normally
acknowledged but no change will happen in the byte value. The device does not go to an
E/W cycle and can be accessed immediately.
If a block is protected and only read operation is allowed (the corresponding APP register
has its PB bits programmed to 10b), a write operation to this block is not acknowledged
(Slave Address and Register pointer only are acknowledged). The device does not go to
an E/W cycle and can be accessed immediately.
S – Addr+W – ACK – Reg Pointer – ACK – Data – NACK
This applies to:
EEPROM block 0 to block 7, controlled by PB0 to PB7.
The last 7 bytes of the APP block (09h to 0Fh) and the ID page (10h to 1Fh) controlled
by PBAP.
If a block is protected and neither read operation nor write operation is allowed (the
corresponding APP register has its PB bits programmed to 00b or 01b), a write operation
to this block is not acknowledged (Slave Address and Register pointer only are
acknowledged).
S – Addr+W – ACK – Reg Pointer – ACK – Data – NACK
A read operation to this block is not allowed.
S – Addr+W – ACK – Reg Pointer – ACK – Sr – Addr+R – NACK
S – Addr+W – ACK – Reg Pointer – ACK – P – S – Addr+R – NACK
This applies to:
EEPROM block 0 to block 7, controlled by PB0 to PB7.
The last 7 bytes of the APP block (09h to 0Fh) and the ID page (10h to 1Fh) controlled
by PBAP.
NXP Semiconductors PCA24S08A
1024 × 8-bit CMOS EEPROM with access protection
6.4.2.1 Block 0 write protection bitsThe PCA24S08A provides a mechanism to divide block 0 into eight 128-bit (16-byte)
pages that can be individually protected against writes. These eight write protection
(WPN) bits are stored within a byte of the access protection page and are organized such
that the LSB protects the first 128 bits, and so on. If a bit in this byte is set to a one and the
PB0 field is set to 11b, then writes are permitted on the page corresponding to the WPN
bit. If the WPN bit is set to a logic 0 or the PB0 is any value other than 11b, then writes are
not permitted in that page.
The Write Protection hierarchy for serial accesses is shown in Figure 10. In this drawing
the bits within the boxes to the left of the arrows are the only thing that determine whether
or not the bit in the box to the right of the arrow can be written. Read access control is not
shown in this diagram. Addresses listed in this diagram are for the serial port assuming
that the R/W bit in the command byte is set to ‘0’.
NXP Semiconductors PCA24S08A
1024 × 8-bit CMOS EEPROM with access protectionFor example, when SB1 is a 1, the PB1 field can be written to any value by the system.
When the PB1 field is 11b, Block 1 can be written to by the system. Note that the state of
the SB1 bit does not affect whether or not Block 1 can be written.
There is no individual page Write Protection for any other block other than block 0 within
the device. Within the remaining blocks on the chip, access permissions are controlled on
a block basis (BP bits) or full chip basis (WP pin) only.
6.4.2.2 Access Protection Page (APP)The serial port may be used to read and write the Access Protection Page (APP) and ID
Page using device access codes B8h and B9h instead of the normal value of A8h through
AFh (hex) that are used to access the rest of the EEPROM memory. The second byte of
write commands (the word address) should be in the range of 00h through 0Fh for the
APP page and 10h through 1Fh for the ID page. This coding is shown in Figure 11.
Reads and writes to these two pages may take place on a single byte basis only.
Multi-byte operations will be NACKed.
As an example, the bit encoding for a single byte read and write command are shown in
Figure 11.
The PCA24S08A will acknowledge all device addresses of B8h or B9h. If the most
significant three its of the word address are not all 0 (indicating an address outside the
Access protection and ID pages), the chip will NACK the access.
Byte 0 through byte 7 of the APP contain 8 identical sets of access control fields (PBx and
SBx) for each of the eight blocks of memory on the chip, which operate according to
Table 4. When the sticky bit in one of these bytes is set, that byte can be written by the
system. Once a sticky bit is reset (written to zero) by the software, the byte containing it
can no longer be modified by the software until the next power cycle. These bytes can
always be read by the system.
Byte 8 contains another PB field (PBAP) as bit 0 and bit 1, and an additional sticky bit
(SBAP) as bit 7. The value of the PBAP bits controls read and write access to the last bytes (byte 9 through byte 15) of the APP and all 16 bytes of the ID page according to
the encoding listed in Section 6.4. The value of the PBAP bits can only be changed, a
write from the serial port, when SBAP is HIGH. This byte can always be read by the
system. Bit 0 through bit 6 of this byte are stored in EEPROM memory and do not change
when the power is cycled or the PROT pin changes state.
Byte 9 contains the eight block 0 write protection bits (WPN) for each page within block0.
Byte 10 emulates a coil detection feature to keep compatibility with existing software
controlling device.
Even though the PCA24S08A does not have the RFID capability of the AT24RF03C, it
gives a ‘coil non-detected’ information when the detection feature is initiated.
The detection feature uses the Detection Enable bit (DE) and the Detect Coil bit (DC). At
power-up, DE= 0 and DC= 1. Detection is enabled by setting DE bit at 1. Since no coil is
detected, DC is then automatically reset and equal to 0.
NXP Semiconductors PCA24S08A
1024 × 8-bit CMOS EEPROM with access protectionBit 0 in the same byte emulates a TAMPER bit and is always equal to 0. TAMPER is a
read-only bit. Attempt to write a ‘1’ to this bit will be ignored.
Byte 11 through byte 14 are currently reserved and should not be used by the system.
Byte 14 may not be written by the device at any time.
Byte 11 to byte 13 are read/write bytes that are stored in the EEPROM.
Byte 14 is a read-only byte and the returned value during a read operation is FFh. A write
on it is acknowledged, but the write will be ignored.
Byte 15 contains device revision information stored in the EEPROM. It is set at the wafer
production facility and cannot be changed in the field, so any write to this byte will be
ignored but acknowledged. The value of this byte is 10h.
The memory map for the Access Protection Page is shown in Table 5 “APP memory map”.
In this table, an ‘X’ means that the value is a ‘Don’t care’ upon writing, and that it is
undefined upon reading. The PB fields are all 2 bits wide, and the Device Revision field is bits wide. All other fields are 1 bit wide.
With the exception of the 9 Sticky Bits (SB), the two coil detect bits (DE and DC), the
tamper bit (TAMPER), and bytes 14 and 15, all bits within the Access Protection Page are
stored in EEPROM memory. Their state does not change if power is removed or when the
PROT pin is held LOW.
The following page of memory (accessed with A4 = 1) emulate the ID field that would be
transmitted by the device from the RFID port. Bytes within it are accessed with the
address byte at B8h or B9h (write/read). Reading and writing to this page is permitted
when PBAP is 11.
