PCA8565TS ,Real time clock/calendarapplications that require a wide operating temperature range1. The definition of the abbreviations a ..
PCA8574AN , Remote 8-bit I/O expander for I2C-bus with interrupt
PCA8574APW ,Remote 8-bit I/O expander for I虏C-bus with interruptApplications LED signs and displays Servers Key pads Industrial control Medical equipment PLC ..
PCA8574PW ,Remote 8-bit I/O expander for I虏C-bus with interruptapplications and the latched output ports have 25 mA high current sink drive capability for directl ..
PCA8574TS ,Remote 8-bit I/O expander for I虏C-bus with interruptFeatures and benefits2 I C-bus to parallel port expander2 2 400 kHz I C-bus interface (Fast-mode ..
PCA8575PW ,Remote 16-bit I/O expander for I2C-bus with interruptApplicationsn LED signs and displaysn Serversn Industrial controln Medical equipmentn PLCsn Cellula ..
PEF22810TV2.1 ,ETHERNET OVER VDSL CHIPSETBlock DiagramInterleaver QAM DAC Power PostFramerRS-Encoder Modulator 12 Bit Control FilterBroadban ..
PEF22810TV2.1 ,ETHERNET OVER VDSL CHIPSETP RO DU C T B RIEFTM10BaseS is an innovative technology offering the simplicity of Ethernet coupled ..
PEF22810TV21 ,ETHERNET OVER VDSL CHIPSETFeatures(QAM) 1.5 W including line driver Compatible with IEEE 802.3 Frequency division duplexing ..
PEF22822ELV2.2 ,ETHERNET OVER VDSL CHIPSETapplications Robust operation handles micro- JTAG for chip level and board MII Serial Management ..
PEF22822EL-V2.2 ,ETHERNET OVER VDSL CHIPSETFeatures(QAM) 1.5 W including line driver Compatible with IEEE 802.3 Frequency division duplexing ..
PEF22822ELV2.2 . ,ETHERNET OVER VDSL CHIPSETApplications No need for glue logic. Standard Spectral allocation allows noise- 10BaseS, Ethernet ..
PCA8565TS
Real time clock/calendar
General descriptionThe PCA8565 is a CMOS1 real time clock and calendar optimized for low power
consumption.A programmable clock output, interrupt output and voltage-low detector are
also provided. All address and data are transferred serially via a two-line bidirectional2 C-bus. Maximum bus speed is 400 kbit/s. The built-in word address register is
incremented automatically after each written or read data byte.
AEC-Q100 compliant (PCA8565TS) for automotive applications.
Features Provides year, month, day, weekday, hours, minutes and seconds based on a
32.768 kHz quartz crystal Century flag Clock operating voltage: 1.8 V to 5.5V Extended operating temperature range: −40 °C to +125°C Low backup current; typical 0.65 μA at VDD= 3.0 V and Tamb =25°C 400 kHz two-wire I2 C-bus interface (at VDD= 1.8Vto 5.5V) Programmable clock outputfor peripheral devices (32.768 kHz, 1.024 kHz,32 Hz and Hz) Alarm and timer functions Internal power-on resetI2 C-bus slave address: read A3h and write A2h Open-drain interrupt pin One integrated oscillator capacitor
Applications Automotive Industrial Other applications that require a wide operating temperature range
PCA8565
Real time clock/calendar
Rev. 02 — 16 June 2009 Product data sheet The definition of the abbreviations and acronyms used in this data sheet can be found in Section16.
NXP Semiconductors PCA8565
Real time clock/calendar Ordering information Marking
Table 1. Ordering informationPCA8565TS TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm
SOT505-1
PCA8565BS HVSON10 plastic thermal enhanced very thin small outline
package; no leads; 10 terminals;
body 3×3 × 0.85 mm
SOT650-1
Table 2. Marking codesPCA8565TS 8565
PCA8565BS 8565S
NXP Semiconductors PCA8565
Real time clock/calendar Block diagram
NXP Semiconductors PCA8565
Real time clock/calendar Pinning information
7.1 Pinning
7.2 Pin description[1] The die paddle (exposed pad) is wired to VSS but should not be electrically connected.
Table 3. Pin descriptionOSCI 1 1 oscillator input
OSCO 2 2 oscillator output
n.c. - 3, 10 do not connect and do not use as feed through;
connect to VDD if floating pins are not allowed
INT 3 4 interrupt output (open-drain; active LOW)
VSS 45[1] ground
SDA 5 6 serial data I/O
SCL 6 7 serial clock input
CLKOUT 7 8 clock output, open-drain
VDD 8 9 positive supply voltage
NXP Semiconductors PCA8565
Real time clock/calendar Device protection diagram Functional descriptionThe PCA8565 contains sixteen 8-bit registers withan auto-incrementing address register,
an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which
provides the source clockfor the Real Time Clock (RTC),a programmable clock output,a
timer, an alarm, a voltage-low detector and a 400 kHz I2 C-bus interface.
All 16 registers are designed as addressable 8-bit registers although not all bits are
implemented:
The first two registers (memory address 00h and 01h) are usedas control and status
registers
The registers at memory addresses 02h through 08h are used as counters for the
clock function (seconds up to years counters)
Address locations 09h through 0Ch contain alarm registers which define the
conditions for an alarm
The register at address 0Dh controls the CLKOUT output frequency
At address 0Eh is the timer control register and address 0Fh contains the timer value
The arrays SECONDS, MINUTES, HOURS, DAYS, WEEKDAYS, MONTHS, YEARS as
well as the bit fields MINUTE_ALARM, HOUR_ALARM, DAY_ALARM and
WEEKDAY_ALARM are all coded in Binary Coded Decimal (BCD) format.
When one of the RTC registers is read the contents of all time counters are frozen. This
prevents faulty reading of the clock or calendar during a carry condition (see
Section 10.5.3).
NXP Semiconductors PCA8565
Real time clock/calendar
9.1 Register overview
Table 4. Register overview and control bits default valuesBit positions labeled as - are not implemented. Bit positions labeled as N should always be written with logic 0. Reset values
are shown inT able7.
Control registers
Time and date registers
Alarm registers
CLKOUT control register
Timer registers
NXP Semiconductors PCA8565
Real time clock/calendar
9.2 Control registers
9.2.1 Register Control_1[1] Default value.
[2] Bits labeled as N should always be written with logic 0.
9.2.2 Register Control_2[1] Bits labeled as N should always be written with logic 0.
[2] Default value.
Table 5. Register Control_1 (address 00h) bits description TEST1 0[1] normal mode EXT_CLK test mode 0[2] default value
5STOP 0[1] RTC source clock runs all RTC divider chain flip-flops are asynchronously setto
logic0;
the RTC clockis stopped (CLKOUTat 32.768 kHzis still
available) 0[2] default value TESTC 0 power-on reset override facility is disabled;
set to logic 0 for normal operation[1] power-on reset override may be enabledto0N 000[2] default value
Table 6. Register Control_2 (address 01h) bits descriptionto5N 000[1] default value TI_TP 0[2] INT is active when TF is active (subject to the status of
TIE) INT pulses active according to Table 26 (subject to the
status of TIE);
Remark: note thatifAF and AIE are active then INT will
be permanently active
3AF 0[2] alarm flag inactive alarm flag active
2TF 0[2] timer flag inactive timer flag active AIE 0[2] alarm interrupt disabled alarm interrupt enabled TIE 0[2] timer interrupt disabled timer interrupt enabled
NXP Semiconductors PCA8565
Real time clock/calendar
9.3 ResetThe PCA8565 includes an internal reset circuit which is active whenever the oscillator is
stopped.In the reset state theI2 C-bus logicis initialized including the address pointer.All
other registers are set according to Table7.
[1] Registers labeled ‘x’ are undefined at power-on and unchanged by subsequent resets.
9.4 Time and date registersThe majority of the registers are coded in the BCD format to simplify application use.
[1] Start-up value.
[2] Values shown in decimal.
Table 7. Register reset values[1]00h Control_1 0 0 0 0 1 0 0 0
01h Control_2 x x 0 0 0 0 0 0
02h Seconds 1 x x x x x x x
03h Minutes 1 x x x x x x x
04h Hours x x x x x x x x
05h Days xxxxxxxx
06h Weekdays x x x x x x x x
07h Months_century x x x x x x x x
08h Y ears x x x x x x x x
09h Minute_alarm 1 x x x x x x x
0Ah Hour_alarm 1 x x x x x x x
0Bh Day_alarm 1 x x x x x x x
0Ch Weekday_alarm 1 x x x x x x x
0Dh CLKOUT_control 1 x x x x x 0 0
0Eh Timer_control 0 x x x x x 1 1
0Fh Timer x x x x x x x x
Table 8. Register Seconds (address 02h) bits description VL 0 - clock integrity is guaranteed[1] - integrity of the clock information is not guaranteedto4 SECONDS0to5[2] ten’s place actual seconds coded in BCD format
3 to 0 0 to 9[2] unit place
NXP Semiconductors PCA8565
Real time clock/calendar[1] Values shown in decimal.
[1] Values shown in decimal.
[1] The PCA8565 compensates for leap years by adding a 29th day to February if the year counter contains a
value which is exactly divisible by 4, including the year00.
[2] Values shown in decimal.
[1] Values shown in decimal.
Table 9. Seconds coded in BCD format
Table 10. Register Minutes (address 03h) bits description - - - unusedto4 MINUTES 0to5[1] ten’s place actual minutes coded in BCD format
3 to 0 0 to 9[1] unit place
Table 11. Register Hours (address 04h) bits description7 to 6- - - unusedto4 HOURS 0to2[1] ten’s place actual hours coded in BCD format
3 to 0 0 to 9[1] unit place
Table 12. Register Days (address 05h) bits description7 to 6- - - unused
5to4 DAYS[1] 0to3[2] ten’s place actual day coded in BCD format
3 to 0 0 to 9[2] unit place
Table 13. Register Weekdays (address 06h) bits description7 to 3- - unusedto0 WEEKDAYS 0to6[1] actual weekday values, see Table14
NXP Semiconductors PCA8565
Real time clock/calendar[1] Definition may be re-assigned by the user.
[1] This bit may be re-assigned by the user.
[2] This bit is toggled when the years register overflows from 99 to 00.
[3] Values shown in decimal.
Table 14. Weekday assignmentsSunday 0 0 0
Monday 0 0 1
Tuesday 0 1 0
Wednesday 0 1 1
Thursday 1 0 0
Friday 1 0 1
Saturday 1 1 0
Table 15. Register Months_century (address 07h) bits description[1] 0[2] - indicates the century isx - indicates the century isx+1
6 to 5- - - unused MONTHS 0 to 1[3] ten’s place actual month coded in BCD format, see Table16
3 to 0 0 to 9[3] unit place
Table 16. Month assignments coded in BCD format
NXP Semiconductors PCA8565
Real time clock/calendar[1] Values shown in decimal.
9.5 Data flowFigure 5 shows the data flow and data dependencies starting from the 1 Hz clock tick. the time registers are writtenor readby making individual accessto the chip, then there
is the risk that the time will increment between accesses. This has to be avoided by
stopping the increment of the time circuit. After access is completed, the time circuit is
allowedto continue running and any requestto increment that occurred during the access
is initiated.
As a consequence of this method, it is important to read or write all time registers in one
access i.e. secondsupto years. Failingto comply with this method could resultin the time
becoming corrupted.an example,if the time (seconds throughto hours) are setin one access and thenina
second access the dateis set,itis possible that the time may increment between the two
accesses. A similar problem exists when reading. A roll over may occur between reads
thus giving the minutes from one moment and the hours from the next.
Recommended method for reading the time: Send a START condition and the slave address for write (A2h). Set the address pointer to registers Seconds (02h).
Table 17. Register Years (08h) bits descriptionto4 YEARS 0to9[1] ten’s place actual year coded in BCD format
3to0 0to9[1] unit place
NXP Semiconductors PCA8565
Real time clock/calendar Send a RESTART condition or STOP followed by START. Send the slave address for read (A3h). Read the register Seconds. Read the register Minutes. Read the register Hours. Read the register Days. Read the register Weekdays.
10. Read the register Months_century.
11. Read the register Y ears.
12. Send a STOP condition.
9.6 Alarm functionWhen one or more of the alarm registers are loaded with a valid minute, hour, day or
weekday andits correspondingbit alarm enable (AE_x)is logic0, then that informationis
compared with the actual minute, hour, day and weekday.
NXP Semiconductors PCA8565
Real time clock/calendar
9.6.1 Alarm registers[1] Default value.
[2] Values shown in decimal.
[1] Default value.
[2] Values shown in decimal.
[1] Default value.
[2] Values shown in decimal.
[1] Default value.
[2] Values shown in decimal.
9.6.2 Alarm flagWhen all enabled comparisons first match, the Alarm Flag (AF) is set. AF will remain set
until cleared using the interface.
Once AF has been cleared it is only set again when
the time increments to match the alarm condition once more.
Table 18. Register Minute_alarm (address 09h) bits description AE_M 0 - minute alarm is enabled[1] - minute alarm is disabledto4 MINUTE_ALARM 0to5[2] ten’s place minute alarm information coded in BCD
format3 to 0 0 to 9[2] unit place
Table 19. Register Hour_alarm (address 0Ah) bits description AE_H 0 - hour alarm is enabled[1] - hour alarm is disabled - - - unusedto4 HOUR_ALARM 0to2[2] ten’s place hour alarm information coded in BCD
format3 to 0 0 to 9[2] unit place
Table 20. Register Day_alarm (address 0Bh) bits description AE_D 0 - day alarm is enabled[1] - day alarm is disabled - - - unusedto4 DAY_ALARM 0to3[2] ten’s place day alarm information coded in BCD
format3 to 0 0 to 9[2] unit place
Table 21. Register Weekday_alarm (address 0Ch) bits description AE_W 0 weekday alarm is enabled[1] weekday alarm is disabled
6 to 3- - unusedto0 WEEKDAY_ALARM0to6[2] weekday alarm information coded in BCD format
NXP Semiconductors PCA8565
Real time clock/calendarAlarm registers which have their bit AE_x at logic 1 are ignored.
Table 23 shows an example for clearing bit AF but leaving bit TF unaffected. Clearing the
flagsis madebya write command; therefore bits7,6,4,1 and0 mustbe written with their
previous values. Repeatedly re-writing these bits has no influence on the functional
behavior. prevent the timer flags being overwritten while clearing AF,a logical ANDis performed
during a write access. Writing a logic 1 will cause the flag to maintain its value, whereas
writing a logic 0 will cause the flag to be reset.
The following table shows what instruction mustbe sentto clearbit AF.In this examplebit
TF is unaffected.
9.7 Timer functionsThe 8-bit countdown timer at address 0Fh is controlled by the timer control register at
address 0Eh. The timer control register determines one of 4 source clock frequencies for
the timer (4.096 kHz,64 Hz,1 Hz,or1⁄60 Hz) and enablesor disables the timer. The timer
counts down from a software-loaded 8-bit binary value. At the end of every countdown,
the timer sets the timer flag (TF). The TFis cleared using the interface. The asserted TFis
used to generate an interrupt (INT). The interrupt is generated as a pulsed signal every
countdown period or as a permanently active signal which follows the condition of TF.
Bit TI_TP is used to control this mode selection. When reading the timer, the actual
countdown value is returned.
Table 22. Flag location in register Control_2Control_2 - - - - AF TF - -
Table 23. Example to clear only AF (bit 3) in register Control_2Control_2 - - - - 0 1 - -
NXP Semiconductors PCA8565
Real time clock/calendar
9.7.1 Register Timer_control[1] Default value.
[2] These bits determine the source clock for the countdown timer; when not in use, TD[1:0] should be set to
1⁄60 Hz for power saving.
The timer register is an 8-bit binary countdown timer. It is enabled and disabled via the
bit TE in register Timer_control. The source clock for the timer is also selected by the
TD[1:0] in register Timer_control. Other timer properties such as interrupt generation are
controlled via register Control_2.
For accurate read backof the countdown value, theI2 C-bus clock (SCL) must operateata
frequency of at least twice the selected timer clock. Since it is not possible to freeze the
countdown timer counter during read back, it is recommended to read the register twice
and check for consistent results.
9.8 Interrupt output
9.8.1 Bits TF and AFWhen an alarm occurs, AF is setto 1. Similarly, at the end of a timer countdown, TFis
setto 1. These bits maintain their value until overwritten using the interface. If both timer
and alarm interrupts are required in the application, the source of the interrupt is
determined by reading these bits. To prevent one flag being overwritten while clearing
another a logic AND is performed during a write access.
Table 24. Register Timer_control (address 0Eh) bits description7TE 0[1] timer is disabled timer is enabled
6 to 2- - unusedto0 TD[1:0] timer source clock frequency select[2] 4.096 kHz 64Hz 1Hz[2] 1⁄60Hz
Table 25. Timer (address 0Fh) bits descriptionto0 COUNTDOWN_TIMER 00hto FFh countdown value=n;
CountdownPeriod n
SourceClockFrequency---------------------------------------------------------------=
NXP Semiconductors PCA8565
Real time clock/calendar
9.8.2 Bits TIE and AIEThese bits activateor deactivate the generationofan interrupt when TFor AFis asserted
respectively. The interrupt is the logical OR of these two conditions when both AIE and
TIE are set.
9.8.3 Countdown timer interruptsThe pulse generator for the countdown timer interrupt uses an internal clock and is
dependent on the selected source clock for the countdown timer and on the countdown
value n. As a consequence, the width of the interrupt pulse varies (see Table 26).
[1]n= loaded countdown value. Timer stopped when n=0.
9.9 Clock outputA programmable square wave is available at pin CLKOUT . Operation is controlled by the
CLKOUT_control register at address 0Dh. Frequencies of 32.768 kHz (default),
1.024 kHz, 32 Hz and 1 Hz can be generated for use as a system clock, microcontroller
clock, inputtoa charge pump,orfor calibrationof the oscillator. CLKOUTisan open-drain
output and enabled at power-on. If disabled it becomes high-impedance.
Table 26. INT operation (bit TI_TP=1)4096 1⁄8192 1⁄4096 1⁄128 1⁄64 1⁄64 1⁄64
1⁄60 1⁄64 1⁄64
NXP Semiconductors PCA8565
Real time clock/calendar[1] Default value.
9.10 Voltage-low detectorThe PCA8565 hasan on-chip voltage-low detector. When VDD drops below Vlow,bit VLin
the Seconds register is set to indicate that the integrity of the clock information is no
longer guaranteed. The VL flag is cleared using the interface.
Bit VLis intendedto detect the situation when VDDis decreasing slowly,for example under
battery operation. Should VDD reach Vlow before power is re-asserted then bit VL is set.
This indicates that the time may be corrupt (see Figure 9).
9.11 External clock (EXT_CLK) test mode test modeis available which allowsfor on-board testing.In sucha modeitis possibleto
set up test conditions and control the operation of the RTC.
The test mode is entered by setting bit TEST1 in register Control_1. Then pin CLKOUT
becomes an input. The test mode replaces the internal 64 Hz signal with the signal
applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT will then
generate an increment of one second.
Table 27. Register CLKOUT_control (address 0Dh) bits description FE 0 the CLKOUT outputis inhibited and CLKOUT outputisset
to high-impedance[1] the CLKOUT output is activated
6 to 2- - unusedto0 FD[1:0] frequency output at pin CLKOUT[1] 32.768 kHz 1.024 kHz 32Hz 1Hz
NXP Semiconductors PCA8565
Real time clock/calendarThe signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a
minimum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is
divided down to 1 Hz by a 26 divide chain called a pre-scaler. The pre-scaler can be set
into a known state by using bit STOP . When bit STOP is set, the pre-scaler is reset to0
(STOP must be cleared before the pre-scaler can operate again).
From a STOP condition, the first 1 second increment will take place after 32 positive
edges on CLKOUT . Thereafter, every 64 positive edges will cause a 1 second increment.
Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.
When entering the test mode, no assumption as to the state of the pre-scaler can be
made.
Operation example: Set EXT_CLK test mode (Control_1, bit TEST1=1). Set STOP (Control_1, bit STOP= 1). Clear STOP (Control_1, bit STOP=0). Set time registers to desired value. Apply 32 clock pulses to CLKOUT. Read time registers to see the first change. Apply 64 clock pulses to CLKOUT. Read time registers to see the second change.
Repeat 7 and 8 for additional increments.
9.12 STOP bit functionThe functionof the STOPbitisto allowfor accurate startingof the time circuits. The STOP
bit function will cause the upper part of the prescaler (F2 to F14) to be held in reset and
thusno1 Hz ticks willbe generated (see Figure 10). The time circuits can thenbe set and
will not increment until the STOP bit is released (see Figure 11 and Table 28).
NXP Semiconductors PCA8565
Real time clock/calendarThe STOP bit function will not affect the output of 32.768 kHz but will stop 1.024 kHz, Hz and 1 Hz.
The lower two stages of the prescaler (F0 and F1) are not reset and because the I2 C-bus asynchronousto the crystal oscillator, the accuracyof re-starting the time circuits willbe
between zero and one 8.192 kHz cycle (see Figure 11).
[1] F0 is clocked at 32.768 kHz.
Table 28. First increment of time circuits after STOP bit release
Clock is running normally 01-0 0001 1101 0100 12:45:12 prescaler counting normally
STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally XX-0 0000 0000 0000 12:45:12 prescaler is reset; time circuits are frozen
New time is set by user XX-0 0000 0000 0000 08:00:00 prescaler is reset; time circuits are frozen
STOP bit is released by user XX-0 0000 0000 0000 08:00:00 prescaler is now running
XX-1 0000 0000 0000 08:00:00 -
XX-0 1000 0000 0000 08:00:00 -
XX-1 1000 0000 0000 08:00:00 - ::
11-1 1111 1111 1110 08:00:00 -
00-0 0000 0000 0001 08:00:01 0 to 1 transition of F14 increments the time circuits
10-0 0000 0000 0001 08:00:01 - ::
11-1 1111 1111 1111 08:00:01 -
00-0 0000 0000 0000 08:00:01 -
10-0 0000 0000 0000 08:00:01 - :-
11-1 1111 1111 1110 08:00:01 -
00-0 0000 0000 0001 08:00:02 0 to 1 transition of F14 increments the time circuits
013aaa076
0.507813- 0.507935 s
1.000000 s
NXP Semiconductors PCA8565
Real time clock/calendarThe first incrementof the time circuitsis between 0.507813s and 0.507935s after STOP
bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset
(see Table 28) and the unknown state of the 32 kHz clock.
9.13 Power-On Reset (POR) overrideThe POR durationis directly relatedto the crystal oscillator start-up time. Dueto the long
start-up times experienced by these types of circuits, a mechanism has been built in to
disable the POR and hence speedup on-board testof the device. The settingof this mode
requires that the I2 C-bus pins, SDA and SCL, be toggled in a specific order as shown in
Figure 12. All timings are required minimums.
Once the override mode has been entered, the device immediately stops being reset and
normal operation may commence i.e. entry into the EXT_CLK test mode via I2 C-bus
access. The override mode maybe clearedby writinga logic0to TESTC. TESTC mustbe
set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic0
during normal operation hasno effect exceptto prevent entry into the POR override mode.
