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PCA9306IDCURQ1 ,Automotive Dual Bidirectional I2C Bus and SMBus Voltage-Level Translator 8-VSSOP -40 to 85Features • Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II1• Qualified for Automotive Appl ..
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PCA9306D-PCA9306DC1-PCA9306DP-PCA9306DP1-PCA9306GF-PCA9306GM
Dual bidirectional I2C-bus and SMBus voltage-level translator
1. General descriptionThe PCA9306 is a dual bidirectional I2 C-bus and SMBus voltage-level translator with an
enable (EN) input, and is operational from 1.0 V to 3.6 V (Vref(1)) and 1.8 V to 5.5V
(Vbias(ref)(2)).
The PCA9306 allows bidirectional voltage translations between 1.0 V and 5 V without the
use of a direction pin. The low ON-state resistance (Ron) of the switch allows connections
to be made with minimal propagation delay. When EN is HIGH, the translator switch is on,
and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively,
allowing bidirectional data flow between ports. When EN is LOW, the translator switch is
off, and a high-impedance state exists between ports.
The PCA9306 is not a bus buffer like the PCA9509 or PCA9517A that provide both level
translation and physically isolates the capacitance to either side of the bus when both
sides are connected. The PCA9306 only isolates both sides when the device is disabled
and provides voltage level translation when active.
The PCA9306 can also be used to run two buses, one at 400 kHz operating frequency
and the other at 100 kHz operating frequency. If the two buses are operating at different
frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other
bus is required. If the master is running at 400 kHz, the maximum system operating
frequency may be less than 400 kHz because of the delays added by the translator.
As with the standard I2 C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the translator’s bus. The PCA9306 has a standard open-collector
configuration of the I2 C-bus. The size of these pull-up resistors depends on the system,
but each side of the translator must have a pull-up resistor. The device is designed to work
with Standard-mode, Fast-mode and Fast-mode Plus I2 C-bus devices in addition to
SMBus devices. The maximum frequency is dependent on the RC time constant, but
generally supports >2 MHz.
When the SDA1 or SDA2 port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the SDA1 and SDA2 ports. Assuming the higher voltage is on
the SDA2 port when the SDA2 port is HIGH, the voltage on the SDA1 port is limited to the
voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain
pull-up supply voltage (Vpu(D)) by the pull-up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user without the
need for directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2
channel.
PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translator
Rev. 8 — 22 January 2014 Product data sheet
NXP Semiconductors PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translatorAll channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
2. Features and benefits 2-bit bidirectional translator for SDA and SCL lines in mixed-mode I2 C-bus applications Standard-mode, Fast-mode, and Fast-mode Plus I2 C-bus and SMBus compatible Less than 1.5 ns maximum propagation delay to accommodate Standard-mode and
Fast-mode I2 C-bus devices and multiple masters Allows voltage level translation between: 1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2) 1.2 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2) 1.8 V Vref(1) and 3.3 V or 5 V Vbias(ref)(2) 2.5 V Vref(1) and 5 V Vbias(ref)(2) 3.3 V Vref(1) and 5 V Vbias(ref)(2) Provides bidirectional voltage translation with no direction pin Low 3.5 ON-state connection between input and output ports provides less signal
distortion Open-drain I2 C-bus I/O ports (SCL1, SDA1, SCL2 and SDA2) 5V tolerant I2 C-bus I/O ports to support mixed-mode signal operation High-impedance SCL1, SDA1, SCL2 and SDA2 pins for EN= LOW Lock-up free operation Flow through pinout for ease of printed-circuit board trace routing ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Packages offered: SO8, TSSOP8, VSSOP8, XQFN8, XSON8, XSON8U
NXP Semiconductors PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translator
3. Ordering information[1] Same footprint and pinout as the Texas Instruments PCA9306DCU.
[2] PCA9306DC1/DG is functionally the same (electrically and mechanically) as the PCA9306DC1 and the Texas Instruments
PCA9306DCT. It is produced in Dark Green (lead-free and halogen/antimony-free) package material, with a unique orderable part
number for customers who desire to order and only receive Dark Green package material.
[3] Also known as MSOP8.
[4] Same footprint and pinout as the Texas Instruments PCA9306DCT.
[5] Low cost, thinner, drop-in replacement for VSSOP8 (SOT765-1) package.
[6] ‘X’ will change based on date code.
3.1 Ordering options
Table 1. Ordering informationTamb= 40 C to +85 C.
PCA9306D PCA9306 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PCA9306DC 306C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
PCA9306DC1[1] P06 VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
PCA9306DC1/DG[2] P06 VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
PCA9306DP 306P TSSOP8[3] plastic thin shrink small outline package; 8 leads;
body width3 mm
SOT505-1
PCA9306DP1[4] 306T TSSOP8 plastic thin shrink small outline package; 8 leads;
body width3 mm; lead length 0.5 mm
SOT505-2
PCA9306GD1[5] P06 XSON8U plastic extremely thin small outline package; no leads; terminals; UTLP based; body32 0.5 mm
SOT996-2
PCA9306GF 06 XSON8 extremely thin small outline package; no leads; 8 terminals;
body 1.351 0.5 mm
SOT1089
PCA9306GM P6X[6] XQFN8 plastic extremely thin quad flat package; no leads; terminals; body 1.6 1.6 0.5 mm
SOT902-2
Table 2. Ordering optionsPCA9306D PCA9306D,112 SO8 Standard marking *
IC’s tube - DSC bulk pack
2000 Tamb= 40 Cto+85C
PCA9306D,118 SO8 Reel 13” Q1/T1
*standard mark SMD
2500 Tamb= 40 Cto+85C
PCA9306DC PCA9306DC,125 VSSOP8 Reel 7” Q3/T4
*standard mark
3000 Tamb= 40 Cto+85C
PCA9306DC1 PCA9306DC1,125 VSSOP8 Reel 7” Q3/T4
*standard mark
3000 Tamb= 40 Cto+85C
PCA9306DC1/DG PCA9306DC1/DG,125 VSSOP8 Reel 7” Q3/T4
*standard mark
3000 Tamb= 40 Cto+85C
NXP Semiconductors PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translator
4. Functional diagramPCA9306DP PCA9306DP,118 TSSOP8 Reel 13” Q1/T1
*standard mark SMD
2500 Tamb= 40 Cto+85C
PCA9306DP1 PCA9306DP1,125 TSSOP8 Reel 7” Q3/T4
*standard mark
3000 Tamb= 40 Cto+85C
PCA9306GD1 PCA9306GD1,125 XSON8U Reel 7” Q3/T4
*standard mark
3000 Tamb= 40 Cto+85C
PCA9306GF PCA9306GF,115 XSON8 Reel 7” Q1/T1
*standard mark SMD
5000 Tamb= 40 Cto+85C
PCA9306GM PCA9306GM,125 XQFN8 Reel 7” Q3/T4
*standard mark
4000 Tamb= 40 Cto+85C
Table 2. Ordering options …continued
NXP Semiconductors PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translator
5. Pinning information
5.1 PinningNXP Semiconductors PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translator
5.2 Pin description
Table 3. Pin descriptionGND 1 4 ground (0V)
VREF1 2 1 low-voltage side reference supply voltage for
SCL1 and SDA1
SCL1 3 2 serial clock, low-voltage side; connect to
VREF1 through a pull-up resistor
SDA1 4 3 serial data, low-voltage side; connect to VREF1
through a pull-up resistor
SDA2 5 5 serial data, high-voltage side; connect to
VREF2 through a pull-up resistor
SCL2 6 6 serial clock, high-voltage side; connect to
VREF2 through a pull-up resistor
VREF2 7 7 high-voltage side reference supply voltage for
SCL2 and SDA2 8 8 switch enable input; connect to VREF2 and
pull-up through a high resistor
NXP Semiconductors PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translator
6. Functional descriptionRefer to Figure 1 “Logic diagram of PCA9306 (positive logic)”.
6.1 Function table[1] EN is controlled by the Vbias(ref)(2) logic levels and should be at least 1 V higher than Vref(1) for best
translator operation.
7. Limiting values[1] The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp
current ratings are observed.
8. Recommended operating conditions[1] Vref(1) Vbias(ref)(2)1 V for best results in level shifting applications.
Table 4. Function selection (example)= HIGH level; L= LOW level. SCL1= SCL2; SDA1= SDA2 disconnect
Table 5. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Over operating free-air temperature range.
Vref(1) reference voltage (1) 0.5 +6 V
Vbias(ref)(2) reference bias voltage (2) 0.5 +6 V input voltage 0.5[1] +6 V
VI/O voltage on an input/output pin 0.5[1] +6 V
Ich channel current (DC) - 128 mA
IIK input clamping current VI <0V - 50 mA
Tstg storage temperature 65 +150 C
Table 6. Operating conditionsVI/O voltage on an input/output pin SCL1, SDA1,
SCL2, SDA2
05V
Vref(1)[1] reference voltage (1) VREF1 0 5 V
Vbias(ref)(2)[1] reference bias voltage (2) VREF2 0 5 V
VI(EN) input voltage on pin EN 0 5 V
Isw(pass) pass switch current - 64 mA
Tamb ambient temperature operating in free-air 40 +85 C
NXP Semiconductors PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translator
9. Static characteristics[1] All typical values are at Tamb =25C.
[2] Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals at the indicated current through the switch.
ON-state resistance is determined by the lowest voltage of the two terminals.
[3] Guaranteed by design.
[4] For DC, DC1 (VSSOP8) and GD1 (XSON8U) packages only.
Table 7. Static characteristicsTamb= 40 C to +85 C, unless otherwise specified.
VIK input clamping voltage II= 18 mA; VI(EN) =0V - - 1.2 V
IIH HIGH-level input current VI =5 V; VI(EN)=0V --5 A
Ci(EN) input capacitance on pin EN VI=3 V or 0V - 7.1 - pF
Cio(off) off-state input/output capacitance SCLn, SDAn; =3V or0V; VI(EN) =0V 6 pF
Cio(on) on-state input/output capacitance SCLn, SDAn; =3V or0V; VI(EN) =3V 9.3 12.5 pF
Ron ON-state resistance[2] SCLn, SDAn; =0V;IO =64mA
[3]
VI(EN) =4.5V - 2.4 5.0
VI(EN) =3V - 3.0 6.0
VI(EN) =2.3V - 3.8 8.0
VI(EN)= 1.5V - 15 32
VI(EN) =1.5V [4] -32 80 =2.4 V; IO =15mA
VI(EN) =4.5V - 4.8 7.5
VI(EN)=3V - 46 80 =1.7 V; IO =15mA
VI(EN)= 2.3V - 40 80
NXP Semiconductors PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translator
10. Dynamic characteristics
Table 8. Dynamic characteristics (translating down)Tamb= 40 C to +85 C, unless otherwise specified. Values guaranteed by design.
VI(EN)= 3.3 V; VIH =3.3 V; VIL =0V; VM= 1.15 V (see Figure 10)tPLH LOWto HIGH
propagation delay
from (input) SCL2 or SDA2
to (output) SCL1 or SDA1 2.001.2 00.6 ns
tPHL HIGHto LOW
propagation delay
from (input) SCL2 or SDA2
to (output) SCL1 or SDA1 2.001.5 0 0.75 ns
VI(EN)= 2.5 V; VIH =2.5 V; VIL =0V; VM= 0.75 V (see Figure 10)tPLH LOWto HIGH
propagation delay
from (input) SCL2 or SDA2
to (output) SCL1 or SDA1 2.001.2 00.6 ns
tPHL HIGHto LOW
propagation delay
from (input) SCL2 or SDA2
to (output) SCL1 or SDA1 2.501.5 0 0.75 ns
Table 9. Dynamic characteristics (translating up)Tamb= 40 C to +85 C, unless otherwise specified. Values guaranteed by design.
VI(EN)= 3.3 V; VIH =2.3 V; VIL =0V; VTT= 3.3 V; VM =1.15V; RL= 300 (see Figure
10)tPLH LOWto HIGH
propagation delay
from (input) SCL1 or SDA1
to (output) SCL2 or SDA2
01.750 1.0 0 0.5 ns
tPHL HIGHto LOW
propagation delay
from (input) SCL1 or SDA1
to (output) SCL2 or SDA2
02.7501.650 0.8 ns
VI(EN)= 2.5 V; VIH =1.5 V; VIL =0V; VTT= 2.5 V; VM =0.75V; RL= 300 (see Figure
10)tPLH LOWto HIGH
propagation delay
from (input) SCL1 or SDA1
to (output) SCL2 or SDA2
01.750 1.0 0 0.5 ns
tPHL HIGHto LOW
propagation delay
from (input) SCL1 or SDA1
to (output) SCL2 or SDA2 3.302.0 01.0 ns
NXP Semiconductors PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translator
11. Application informationNXP Semiconductors PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translator
11.1 Bidirectional translationFor the bidirectional clamping configuration (higher voltage to lower voltage or lower
voltage to higher voltage), the EN input must be connected to VREF2 and both pins pulled
to HIGH side Vpu(D) through a pull-up resistor (typically 200 k). This allows VREF2 to
regulate the EN input. A filter capacitor on VREF2 is recommended. The I2 C-bus master
output can be totem pole or open-drain (pull-up resistors may be required) and the 2 C-bus device output can be totem pole or open-drain (pull-up resistors are required to
pull the SCL2 and SDA2 outputs to Vpu(D)). However, if either output is totem pole, data
must be unidirectional or the outputs must be 3-stateable and be controlled by some
direction-control mechanism to prevent HIGH-to-LOW contentions in either direction. If
both outputs are open-drain, no direction control is needed.
The reference supply voltage (Vref(1)) is connected to the processor core power supply
voltage. When VREF2 is connected through a 200 k resistor to a 3.3 V to 5.5 V Vpu(D)
power supply, and Vref(1) is set between 1.0 V and (Vpu(D)1 V), the output of each SCL1
and SDA1 has a maximum output voltage equal to VREF1, and the output of each SCL2
and SDA2 has a maximum output voltage equal to Vpu(D).
[1] All typical values are at Tamb =25C.
11.2 How to size pull-up resistor valueSizing the pull-up resistor on an open-drain bus is specific to the individual application and
is dependent on the following driver characteristics:
The driver sink current
The VOL of driver
The VIL of the driver
Frequency of operation
The following tables can be used to estimate the pull-up resistor value in different use
cases so that the minimum resistance for the pull-up resistor can be found.
Table 11, Table 12 and Table 13 contain suggested minimum values of pull-up resistors for
the PCA9306 and NVT20xx devices with typical voltage translation levels and drive
currents. The calculated values assume that both drive currents are the same.
VOL =VIL =0.1 VCC and accounts for a 5%VCC tolerance of the supplies, 1%
resistor values. It should be noted that the resistor chosen in the final application should
be equal to or larger than the values shown in Table 11, Table 12 and Table 13 to ensure
that the pass voltage is less than 10 % of the VCC voltage, and the external driver should
Table 10. Application operating conditionsRefer to Figure11.
Vbias(ref)(2) reference bias voltage (2) Vref(1) +0.6 2.1 5 V
VI(EN) input voltage on pin EN Vref(1) +0.6 2.1 5 V
Vref(1) reference voltage (1) 0 1.5 4.4 V
Isw(pass) pass switch current - 14 - mA
Iref reference current transistor - 5 - A
Tamb ambient temperature operating in free-air 40 - +85 C
NXP Semiconductors PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translatorbe able to sink the total current from both pull-up resistors. When selecting the minimum
resistor value in Table 11, Table 12 or Table 13, the drive current strength that should be
chosen should be the lowest drive current seen in the application and account for any
drive strength current scaling with output voltage. For the GTL devices, the resistance
table should be recalculated to account for the difference in ON resistance and bias
voltage limitations between VCC(B) and VCC(A).
Table 11. Pull-up resistor minimum values, 3 mA driver sink current for PCA9306 and NVT20xx
Table 12. Pull-up resistor minimum values, 10 mA driver sink current for PCA9306 and NVT20xx
NXP Semiconductors PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translator
11.3 How to design for maximum frequency operationThe maximum frequency is limited by the minimum pulse width LOW and HIGH as well as
rise time and fall time. See Equation 1 as an example of the maximum frequency. The rise
and fall times are shown in Figure 13.
(1)
The rise and fall times are dependent upon translation voltages, the drive strength, the
total node capacitance (CL(tot)) and the pull-up resistors (RPU) that are present on the bus.
The node capacitance is the addition of the PCB trace capacitance and the device
capacitance that exists on the bus. Because of the dependency of the external
components, PCB layout and the different device operating states the calculation of rise
and fall times is complex and has several inflection points along the curve.
The main component of the rise and fall times is the RC time constant of the bus line when
the device is in its two primary operating states: when device is in the ON state and it is
low-impedance, the other is when the device is OFF isolating the A-side from the B-side.
A description of the fall time applied to either An or Bn output going from HIGH to LOW is
as follows. Whichever side is asserted first, the B-side down must discharge to the VCC(A)
voltage. The time is determined by the pull-up resistor, pull-down driver strength and the
Table 13. Pull-up resistor minimum values, 15 mA driver sink current for PCA9306 and NVT20xx
NXP Semiconductors PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translatorcapacitance. As the level moves below the VCC(A) voltage, the channel resistance drops
so that both A and B sides equal. The capacitance on both sides is connected to form the
total capacitance and the pull-up resistors on both sides combine to the parallel equivalent
resistance. The Ron of the device is small compared to the pull-up resistor values, so its
effect on the pull-up resistance can be neglected and the fall is determined by the driver
pulling the combined capacitance and pull-up resistor currents. An estimation of the actual
fall time seen by the device is equal to the time it takes for the B-side to fall to the VCC(A)
voltage and the time it takes for both sides to fall from the VCC(A) voltage to the VIL level.
A description of the rise time applied to either An or Bn output going from LOW to HIGH is
as follows. When the signal level is LOW, the Ron is at its minimum, so the A and B sides
are essentially one node. They will rise together with an RC time constant that is the sum
of all the capacitance from both sides and the parallel of the resistance from both sides.
As the signal approaches the VCC(A) voltage, the channel resistance goes up and the
waveforms separate, with the B side finishing its rise with the RC time constant of the side. The rise to VCC(A) is essentially the same for both sides.
There are some basic guidelines to follow that will help maximize the performance of the
device:
Keep trace length to a minimum by placing the NVT device close to the processor.
The signal round trip time on trace should be shorter than the rise or fall time of signal
to reduce reflections.
The faster the edge of the signal, the higher the chance for ringing.
The higher drive strength controlled by the pull-up resistor (up to 15 mA), the higher
the frequency the device can use.
The system designer must design the pull-up resistor value based on external current
drive strength and limit the node capacitance (minimize the wire, stub, connector and
trace length) to get the desired operation frequency result.
NXP Semiconductors PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translator
12. Package outlineNXP Semiconductors PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translatorNXP Semiconductors PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translatorNXP Semiconductors PCA9306
Dual bidirectional I2 C-bus and SMBus voltage-level translator
