PCA9506DGG ,40-bit I2C-bus I/O port with RESET, OE and INTApplications Servers RAID systems Industrial control Medical equipment PLCs Cell phones Gami ..
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PCA9508D ,Hot swappable level translating I2C-bus repeaterfeatures of the I C-bus system during the level shifts, it also permits extension of the2I C-bus by ..
PCA9509D ,Level translating I虏C-bus/SMBus repeaterfeatures of the I C-bus system during the level shifts, it also 2permits extension of the I C-bus b ..
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PEF82912FV1.3 . ,Q-SMINTI (2B1Q Second Gen. Modular IS...Data Sheet, DS 1, March 2001®Q-SMINT I2B1Q Second Gen. Modular ISDN NT (Intelligent)PEF 82912/82913 ..
PEF82912HV1.3 ,Q-SMINTI (2B1Q Second Gen. Modular IS...Data Sheet, DS 1, March 2001®Q-SMINT I2B1Q Second Gen. Modular ISDN NT (Intelligent)PEF 82912/82913 ..
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PEMB13 ,PNP/PNP resistor-equipped transistors; R1 = 4.7 k惟, R2 = 47 k惟
PEMB18 ,PEMB18; PUMB18; PNP/PNP resistor-equipped transistors; R1 = 4.7 kOhm, R2 = 10 kOhmapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..
PEMB19 ,PNP/PNP resistor-equipped transistors; R1 = 22 kOhm, R2 = openapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..
PCA9505DGG-PCA9506BS-PCA9506DGG
40-bit I2C-bus I/O port with RESET, OE and INT
1. General descriptionThe PCA9505/PCA9506 provide 40-bit parallel input/output (I/O) port expansion for 2 C-bus applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are
capable of sourcing 10 mA and sinking 15 mA with a total package load of 600 mA to
allow direct driving of 40 LEDs. Any of the 40 I/O ports can be configured as an input or
output. Output ports are totem-pole and their logic state changes at the Acknowledge
(bank change). The PCA9505 is identical to the PCA9506 except that it includes 100 kΩ
internal pull-up resistors on all the I/Os. The PCA9506 does not include the internal
pull-ups on the I/Os to reduce power consumption when used as outputs or when the
input is driven by a push-pull driver.
The device can be configured to have each input port to be masked in order to prevent it
from generating interrupts when its state changes and to have the I/O data logic state to
be inverted when read by the system master.
An open-drain interrupt (INT) output pin allows monitoring of the input pins and is asserted
each time a change occurs in one or several input ports (unless masked).
The Output Enable (OE) pin 3-states any I/O selected as an output and can be used as an
input signal to blink or dim LEDs (PWM with frequency >80 Hz and change duty cycle).
The internal Power-On Reset (POR) or hardware reset (RESET) pin initializes the 40 I/Os
as inputs. Three address select pins configure one of 8 slave addresses.
The PCA9506 is available in 56-pin TSSOP and HVQFN packages, while the PCA9505 is
available only in a TSSOP package. They are both specified over the −40 °Cto+85 °C
industrial temperature range.
2. Features and benefits Standard mode (100 kHz) and Fast mode (400 kHz) compatible I2 C-bus serial
interface 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os 40 configurable I/O pins that default to inputs at power-up PCA9505 includes 100 kΩ internal pull-up resistors on all the I/Os Outputs: Totem-pole (10 mA source, 15 mA sink) with controlled edge rate output structure Active LOW output enable (OE) input pin 3-states all outputs Output state change on Acknowledge Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level
change of pins programmed as inputs
PCA9505/06
40-bit I2 C-bus I/O port with RESET , OE and INT
Rev. 4 — 3 August 2010 Product data sheet
NXP Semiconductors PCA9505/06
40-bit I2 C-bus I/O port with RESET, OE and INT Inputs: Programmable Interrupt Mask Control for input pins that do not require an interrupt
when their states change Polarity Inversion register allows inversion of the polarity of the I/O pins when read Active LOW reset (RESET) input pin resets device to power-up default state 3 programmable address pins allowing 8 devices on the same bus Designed for live insertion Minimize line disturbance (IOFF and power-up 3-state) Signal transient rejection (50 ns noise filter and robust I2 C-bus state machine) Low standby current −40 °Cto+85 °C operation ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA Offered in TSSOP56 (PCA9505, PCA9506) and HVQFN56 (PCA9506) packages
3. Applications Servers RAID systems Industrial control Medical equipment PLCs Cell phones Gaming machines Instrumentation and test measurement
4. Ordering informationTable 1. Ordering informationPCA9505DGG PCA9505DGG TSSOP56 plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
SOT364-1
PCA9506DGG PCA9506DGG TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1
PCA9506BS PCA9506BS HVQFN56 plastic thermal enhanced very thin quad flat package; leads; 56 terminals; body8×8× 0.85 mm
SOT684-1
NXP Semiconductors PCA9505/06
40-bit I2 C-bus I/O port with RESET, OE and INT
5. Block diagramNXP Semiconductors PCA9505/06
40-bit I2 C-bus I/O port with RESET, OE and INTNXP Semiconductors PCA9505/06
40-bit I2 C-bus I/O port with RESET, OE and INT
6. Pinning information
6.1 PinningNXP Semiconductors PCA9505/06
40-bit I2 C-bus I/O port with RESET, OE and INT
6.2 Pin description
Table 2. Pin descriptionSDA 1 50 I/O serial data line
SCL 2 51 I serial clock line
IO0_0 to IO0_7 3, 4, 5, 7, 8, 9,
10, 12
52, 53, 54, 56, 1,
2, 3, 5
I/O input/output bank 0
IO1_0 to IO1_7 13, 14, 15, 16,
17, 19, 20, 21
6, 7, 8, 9, 10, 12,
13, 14
I/O input/output bank 1
IO2_0 to IO2_7 22, 24, 25, 26,
31, 32, 33, 35
15, 17, 18, 19,
24, 25, 26, 28
I/O input/output bank 2
IO3_0 to IO3_7 36, 37, 38, 40,
41, 42, 43, 44
29, 30, 31, 33,
34, 35, 36, 37
I/O input/output bank 3
IO4_0 to IO4_7 45, 47, 48, 49,
50, 52, 53, 54
38, 40, 41, 42,
43, 45, 46, 47
I/O input/output bank 4
VSS 6, 11, 23, 34,
39, 51
4, 16, 27, 32, 44, [1] power
supply
ground supply voltage
VDD 18, 46 11, 39 power
supply
supply voltage 27 20 I address input 0 28 21 I address input 1 29 22 I address input 2
NXP Semiconductors PCA9505/06
40-bit I2 C-bus I/O port with RESET, OE and INT[1] HVQFN56 package die supply ground is connected to both VSS pins and exposed center pad. VSS pins
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board and for proper heat conduction through the board, thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
7. Functional descriptionRefer to Figure 1 “Block diagram of PCA9505/06” and Figure 2 “Simplified schematic of
IO0_0 to IO4_7”.
7.1 Device addressFollowing a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9505/06 is shown in Figure 5. Slave address pins A2, A1, and A0 choose 1 of 8 slave
addresses and need to be connected to VDD (1) or VSS (0). To conserve power, no internal
pull-up resistors are incorporated on A2, A1, and A0.
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while a logic 0 selects a write operation.
7.2 Command registerFollowing the successful acknowledgement of the slave address + R/W bit, the bus
master will send a byte to the PCA9505/06, which will be stored in the Command register. 30 23 I active LOW output enable input
INT 55 48 O active LOW interrupt output
RESET 56 49 I active LOW reset input
Table 2. Pin description …continued
NXP Semiconductors PCA9505/06
40-bit I2 C-bus I/O port with RESET, OE and INTThe lowest 6 bits are used as a pointer to determine which register will be accessed. The
registers are:
IP: Input Port registers (5 registers)
OP: Output Port registers (5 registers)
PI: Polarity Inversion registers (5 registers)
IOC: I/O Configuration registers (5 registers)
MSK: Mask interrupt registers (5 registers)
If the Auto-Increment flag is set (AI= 1), the 3 least significant bits are automatically
incremented after a read or write. This allows the user to program and/or read the register banks sequentially.
If more than 5 bytes of data are written and AI= 1, previous data in the selected registers
will be overwritten. Reserved registers are skipped and not accessed (refer to Table 3).
If the Auto-Increment flag is cleared (AI= 0), the 3 least significant bits are not
incremented after data is read or written. During a read operation, the same register bank
is read each time. During a write operation, data is written to the same register bank each
time.
Only a Command register code with the 5 least significant bits equal to the 25 allowable
values as defined in Table 3 are valid. Reserved or undefined command codes must not
be accessed for proper device functionality. At power-up, this register defaults to 0x80,
with the AI bit set to logic 1, and the lowest 7 bits set to logic 0.
During a write operation, the PCA9505/06 will acknowledge a byte sent to OPx, PIx, and
IOCx and MSKx registers, but will not acknowledge a byte sent to the IPx registers since
these are read-only registers.
NXP Semiconductors PCA9505/06
40-bit I2 C-bus I/O port with RESET, OE and INT
7.3 Register definitionsTable 3. Register summary
Input Port registers 000000 IP0 read only Input Port register bank 0 000001 IP1 read only Input Port register bank 1 000010 IP2 read only Input Port register bank 2 000011 IP3 read only Input Port register bank 3 000100 IP4 read only Input Port register bank 4 000101 - - reserved for future use 000110 - - reserved for future use 000111 - - reserved for future use
Output Port registers 001000 OP0 read/write Output Port register bank 0 001001 OP1 read/write Output Port register bank 1 001010 OP2 read/write Output Port register bank 2 001011 OP3 read/write Output Port register bank 3 001100 OP4 read/write Output Port register bank 4 001101 - - reserved for future use 001110 - - reserved for future use 001111 - - reserved for future use
Polarity Inversion registers 010000 PI0 read/write Polarity Inversion register bank 0 010001 PI1 read/write Polarity Inversion register bank 1 010010 PI2 read/write Polarity Inversion register bank 2 010011 PI3 read/write Polarity Inversion register bank 3 010100 PI4 read/write Polarity Inversion register bank 4 010101 - - reserved for future use 010110 - - reserved for future use 010111 - - reserved for future use
I/O Configuration registers 011000 IOC0 read/write I/O Configuration register bank 0 011001 IOC1 read/write I/O Configuration register bank 1 011010 IOC2 read/write I/O Configuration register bank 2 011011 IOC3 read/write I/O Configuration register bank 3 011100 IOC4 read/write I/O Configuration register bank 4 011101 - - reserved for future use 011110 - - reserved for future use 011111 - - reserved for future use
NXP Semiconductors PCA9505/06
40-bit I2 C-bus I/O port with RESET, OE and INT
7.3.1 IP0 to IP4 - Input Port registersThese registers are read-only. They reflect the incoming logic levels of the port pins
regardless of whether the pin is defined as an input or an output by the I/O Configuration
register. If the corresponding Px[y] bit in the PI registers is set to logic 0, or the inverted
incoming logic levels if the corresponding Px[y] bit in the PI register is set to logic 1. Writes
to these registers have no effect.
The Polarity Inversion register can invert the logic states of the port pins. The polarity of
the corresponding bit is inverted when Px[y] bit in the PI register is set to logic 1. The
polarity of the corresponding bit is not inverted when Px[y] bits in the PI register is set to
logic0.
Mask Interrupt registers 100000 MSK0 read/write Mask Interrupt register bank 0 100001 MSK1 read/write Mask Interrupt register bank 1 100010 MSK2 read/write Mask Interrupt register bank 2 100011 MSK3 read/write Mask Interrupt register bank 3 100100 MSK4 read/write Mask Interrupt register bank 4 100101 - - reserved for future use 100110 - - reserved for future use 100111 - - reserved for future use
Table 3. Register summary …continued
Table 4. IP0 to IP4 - Input Port registers (address 00h to 04h) bit descriptionLegend: * default value ‘X’ determined by the externally applied logic level.
00h IP0 7 to 0 I0[7:0] R XXXX XXXX* Input Port register bank 0
01h IP1 7 to 0 I1[7:0] R XXXX XXXX* Input Port register bank 1
02h IP2 7 to 0 I2[7:0] R XXXX XXXX* Input Port register bank 2
03h IP3 7 to 0 I3[7:0] R XXXX XXXX* Input Port register bank 3
04h IP4 7 to 0 I4[7:0] R XXXX XXXX* Input Port register bank 4
NXP Semiconductors PCA9505/06
40-bit I2 C-bus I/O port with RESET, OE and INT
7.3.2 OP0 to OP4 - Output Port registersThese registers reflect the outgoing logic levels of the pins defined as outputs by the
I/O Configuration register. Bit values in these registers have no effect on pins defined as
inputs. In turn, reads from these registers reflect the values that are in the flip-flops
controlling the output selection, not the actual pin values.
Ox[y]= 0: IOx_y= 0 if IOx_y defined as output (Cx[y] in IOC register= 0).
Ox[y]= 1: IOx_y= 1 if IOx_y defined as output (Cx[y] in IOC register= 0).
Where ‘x’ refers to the bank number (0to 4); ‘y’ refers to the bit number (0to7).
7.3.3 PI0 to PI4 - Polarity Inversion registersThese registers allow inversion of the polarity of the corresponding Input Port register.
Px[y]= 0: The corresponding Input Port register data polarity is retained.
Px[y]= 1: The corresponding Input Port register data polarity is inverted.
Where ‘x’ refers to the bank number (0to 4); ‘y’ refers to the bit number (0to7).
Table 5. OP0 to OP4 - Output Port registers (address 08h to 0Ch) bit descriptionLegend: * default value.
08h OP0 7 to 0 O0[7:0] R/W 0000 0000* Output Port register bank 0
09h OP1 7 to 0 O1[7:0] R/W 0000 0000* Output Port register bank 1
0Ah OP2 7 to 0 O2[7:0] R/W 0000 0000* Output Port register bank 2
0Bh OP3 7 to 0 O3[7:0] R/W 0000 0000* Output Port register bank 3
0Ch OP4 7 to 0 O4[7:0] R/W 0000 0000* Output Port register bank 4
Table 6. PI0 to PI4 - Polarity Inversion registers (address 10h to 14h) bit descriptionLegend: * default value.
10h PI0 7 to 0 P0[7:0] R/W 0000 0000* Polarity Inversion register bank 0
11h PI1 7 to 0 P1[7:0] R/W 0000 0000* Polarity Inversion register bank 1
12h PI2 7 to 0 P2[7:0] R/W 0000 0000* Polarity Inversion register bank 2
13h PI3 7 to 0 P3[7:0] R/W 0000 0000* Polarity Inversion register bank 3
14h PI4 7 to 0 P4[7:0] R/W 0000 0000* Polarity Inversion register bank 4
NXP Semiconductors PCA9505/06
40-bit I2 C-bus I/O port with RESET, OE and INT
7.3.4 IOC0 to IOC4 - I/O Configuration registersThese registers configure the direction of the I/O pins.
Cx[y]= 0: The corresponding port pin is an output.
Cx[y]= 1: The corresponding port pin is an input.
Where ‘x’ refers to the bank number (0to 4); ‘y’ refers to the bit number (0to7).
7.3.5 MSK0 to MSK4 - Mask interrupt registersThese registers mask the interrupt due to a change in the I/O pins configured as inputs.
‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Mx[y] = 0: A level change at the I/O will generate an interrupt if IOx_y defined as input
(Cx[y] in IOC register = 1).
Mx[y] = 1: A level change in the input port will not generate an interrupt if IOx_y defined
as input (Cx[y] in IOC register = 1).
7.4 Power-on resetWhen power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9505/06
in a reset condition until VDD has reached VPOR. At that point, the reset condition is
released and the PCA9505/06 registers and I2 C-bus state machine will initialize to their
default states. Thereafter, VDD must be lowered below 0.2 V to reset the device.
7.5 RESET inputA reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The
PCA9505/06 registers and I2 C-bus state machine will be held in their default states until
the RESET input is once again HIGH.
Table 7. IOC0 to IOC4 - I/O Configuration registers (address 18h to 1Ch) bit descriptionLegend: * default value.
18h IOC0 7 to 0 C0[7:0] R/W 1111 1111* I/O Configuration register bank 0
19h IOC1 7 to 0 C1[7:0] R/W 1111 1111* I/O Configuration register bank 1
1Ah IOC2 7 to 0 C2[7:0] R/W 1111 1111* I/O Configuration register bank 2
1Bh IOC3 7 to 0 C3[7:0] R/W 1111 1111* I/O Configuration register bank 3
1Ch IOC4 7 to 0 C4[7:0] R/W 1111 1111* I/O Configuration register bank 4
Table 8. MSK0 to MSK4 - Mask interrupt registers (address 20h to 24h) bit descriptionLegend: * default value.
20h MSK0 7 to 0 M0[7:0] R/W 1111 1111* Mask Interrupt register bank 0
21h MSK1 7 to 0 M1[7:0] R/W 1111 1111* Mask Interrupt register bank 1
22h MSK2 7 to 0 M2[7:0] R/W 1111 1111* Mask Interrupt register bank 2
23h MSK3 7 to 0 M3[7:0] R/W 1111 1111* Mask Interrupt register bank 3
24h MSK4 7 to 0 M4[7:0] R/W 1111 1111* Mask Interrupt register bank 4
NXP Semiconductors PCA9505/06
40-bit I2 C-bus I/O port with RESET, OE and INT
7.6 Interrupt output (INT)The open-drain active LOW interrupt is activated when one of the port pins changes state
and the port pin is configured as an input and the interrupt on it is not masked. The
interrupt is deactivated when the port pin input returns to its previous state or the Input
Port register is read.
Remark: Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register.
Only a read of the Input Port register that contains the bit(s) image of the input(s) that
generated the interrupt clears the interrupt condition.
If more than one input register changed state before a read of the Input Port register is
initiated, the interrupt is cleared when all the input registers containing all the inputs that
changed are read.
Example: If IO0_5, IO2_3, and IO3_7 change state at the same time, the interrupt is
cleared only when INREG0, INREG2, and INREG3 are read.
7.7 Output enable input (OE)The active LOW output enable pin allows to enable or disable all the I/Os at the same
time. When a LOW level is applied to the OE pin, all the I/Os configured as outputs are
enabled and the logic value programmed in their respective OP registers is applied to the
pins. When a HIGH level is applied to the OE pin, all the I/Os configured as outputs are
3-stated.
For applications requiring LED blinking with brightness control, this pin can be used to
control the brightness by applying a high frequency PWM signal on the OE pin. LEDs can
be blinked using the Output Port registers and can be dimmed using the PWM signal on
the OE pin thus controlling the brightness by adjusting the duty cycle.
7.8 Live insertionThe PCA9505/06 are fully specified for live insertion applications using IOFF, power-up
3-states, robust state machine, and 50 ns noise filter. The IOFF circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state’s circuitry places the outputs in the high-impedance state
during power-up and power-down, which prevents driver conflict and bus contention.
The robust state machine does not respond until it sees a valid START condition and the ns noise filter will filter out any insertion glitches. The PCA9505/06 will not cause
corruption of active data on the bus, nor will the device be damaged or cause damage to
devices already on the bus when similar featured devices are being used.
7.9 StandbyThe PCA9505/06 goes into standby when the I2 C-bus is idle. Standby supply current is
lower than 1 μA (typical).
NXP Semiconductors PCA9505/06
40-bit I2 C-bus I/O port with RESET, OE and INT
8. Characteristics of the I2 C-busThe I2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transferOne data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 7).
8.1.1 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure8).
8.2 System configurationA device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master' and the devices which are controlled by
the master are the ‘slaves' (see Figure 9).
NXP Semiconductors PCA9505/06
40-bit I2 C-bus I/O port with RESET, OE and INT
8.3 AcknowledgeThe number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
8.4 Bus transactionsData is transmitted to the PCA9505/06 registers using Write Byte transfers (see Figure 11,
Figure 12, and Figure 13). Data is read from the PCA9505/06 registers using Read and
Receive Byte transfers (see Figure 14).
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NXP Semiconductors PCA9505/06
40-bit I2 C-bus I/O port with RESET, OE and INT
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NXP Semiconductors PCA9505/06
40-bit I2 C-bus I/O port with RESET, OE and INT
