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PCA9508D
Hot swappable level translating I2C-bus repeater
General descriptionThe PCA9508 is a CMOS integrated circuit that supports hot-swap with zero offset and
provides level shifting between low voltage (down to 0.9 V) and higher voltage (2.7 V to
5.5 V) for I2 C-bus or SMBus applications. While retaining all the operating modes and
features of the I2 C-bus system during the level shifts, it also permits extension of the2 C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL)
lines, thus enabling two buses of 400 pF. Using the PCA9508 enables the system
designer to isolate two halves of a bus for both voltage and capacitance, and perform
hot-swap and voltage level translation. Furthermore, the dual supply pins canbe powered
up in any sequence; when any of the supply pins are unpowered, the 5 V tolerant I/O are
high-impedance.
The hot swap feature allows an I/O card to be inserted into a live backplane without
corrupting the data and clock buses. Control circuitry prevents the backplane from being
connected to the card until a stop command or bus idle occurs on the backplane without
bus contentionon the card. Zero offset output voltage allows multiple PCA9508stobe put
in series and still maintains an excellent noise margin.
PCA9508 hasB side andA side bus drivers. The 2.7Vto 5.5V busB side drivers behave
much like the drivers on the PCA9515A device, while the adjustable voltage bus A side
drivers drive more current and incur no static offset voltage. This results in a LOW on the side translating into a nearly 0 V LOW on the A side.
The static offset design of the B side PCA9508 I/O drivers prevents them from being
connected to another device that has a rise time accelerator including the PCA9510/A,
PCA9511/A, PCA9512/A, PCA9513/A, or PCA9514/A or a static offset voltage including
the PCA9507 (B side), PCA9508 (B side), PCA9509 (A side), PCA9515/A, PCA9516A,
PCA9517/A (B side), PCA9518, PCA9519 (A side), or P82B96/PCA9600 (Sx/Sy side).
TheA sideof twoor more PCA9508s canbe connected together, however,to allowa star
topology with theA sideon the common bus, and theA side canbe connected directlyto
any other buffer with static or dynamic offset voltage. Multiple PCA9508s can be
connected in series, A side to B side, with no build-up in offset voltage with only
time-of-flight delays to consider.
The PCA9508 drivers are not enabled unless the bus is idle, VCC(A) is above 0.8 V and
VCC(B) is above 2.5 V. The EN pin can also be used to turn the drivers on and off under
system control. Caution should be observed to only change the state of the enable pin
when the bus is idle.
The output pull-down on the B side internal buffer LOW is set for approximately 0.5V,
while the input thresholdof the internal bufferis set about70 mV lower (0.43 V). When the side I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
PCA9508
Hot swappable level translating I2 C-bus repeater
Rev. 01 — 28 April 2008 Product data sheet
NXP Semiconductors PCA9508
Hot swappable level translating I2 C-bus repeaterThis prevents a lock-up condition from occurring. The output pull-down on the A side
drives a hard LOW and the input level is set at 0.5VCC(A) to accommodate the need for a
lower LOW level in systems where the low voltage side supply voltage is as low as 0.9V.
Table 1 shows the comparison between PCA9508 and I2 C-bus repeaters.
[1] PCA9517A is the high ESD (6.5 kV HBM and 550 V MM) drop-in replacement for PCA9517.
Features2 channel, bidirectional buffer isolates capacitance and allows 400pFon either sideof
the device Supports offset-free hot-swap with IDLE/STOP detect circuitry Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5V Footprint and functional replacement for PCA9515, PCA9515A, PCA9517 and
PCA9517AI2 C-bus and SMBus compatible Active HIGH repeater enable input Static level offset on B side Open-drain input/outputs Lock-up free operation Supports arbitration and clock stretching across the repeater Accommodates Standard-mode and Fast-mode I2 C-bus devices and multiple masters Powered-off high-impedance I2 C-bus pinsA side operating supply voltage range of 0.9 V to 5.5VB side operating supply voltage range of 2.7 V to 5.5V5 V tolerant I2 C-bus and enable pins0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be
less than 400 kHz because of the delays added by the repeater). ESD protection exceeds 6000 V HBM per JESD22-A114, 450 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8 and TSSOP8
Table 1. PCA9508 and I2 C-bus repeaters comparisonVCC(A) range (V) 2.7 to 5.5 0.9 to 5.5 1.1 to VCC(B)−1 0.9 to 5.5 1.1 to VCC(B)−1
VCC(B) range (V) 2.7 to 5.5 2.7 to 5.5 3.0 to 5.5 2.7 to 5.5 3.0 to 5.5
rise time
accelerator
yes - - - -
idle/stop detect
for hot-swap yes - - -
normal I/O A side A side B side A side B side
static level offset B side B side A side B side A side
NXP Semiconductors PCA9508
Hot swappable level translating I2 C-bus repeater Ordering information[1] Also known as MSOP8.
Functional diagram
Table 2. Ordering informationTamb= −40 °C to +85 °C.
PCA9508D PCA9508 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PCA9508DP 9508 TSSOP8[1] plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
NXP Semiconductors PCA9508
Hot swappable level translating I2 C-bus repeater Pinning information
5.1 Pinning
5.2 Pin description Functional descriptionRefer to Figure 1 “Functional diagram of PCA9508”.
The PCA9508 enables I2 C-bus or SMBus translation down to VCC(A) as low as 0.9V
without degradation of system performance. The PCA9508 contains two bidirectional
open-drain buffers specifically designed to provide superior hot-swap and/or support
up-translation/down-translation between the low voltage (as low as 0.9 V) and a 3.3 V orI2 C-busor SMBus.All inputs and I/Os are overvoltage tolerantto 5.5V even when the
device is unpowered (VCC(B) and/or VCC(A)=0 V). The PCA9508 includes a power-up
circuit that keeps the output drivers turnedoff until VCC(B)is above 2.5V and the VCC(A)is
above 0.8V. VCC(B) and VCC(A) canbe appliedin any sequenceat power-up. VCC(A)is only
usedto provide the 0.5VCC(A) referenceto theA side input comparators andfor the power
good detect circuit. The PCA9508 logic and all I/Os are powered by the VCC(B) pin.
An undervoltage/initialization circuit holds the PCA9508 in a disconnected state which
presents high-impedancetoall SDA and SCL pins during power-up.A LOWon the enable
pin (EN) also forces the parts into the disconnected state.As the power supplyis brought and ENis HIGHor the partis powered and ENis taken from LOWto HIGHit entersan
initialization state where the internal references are stabilized. At the end of the
initialization state the ‘STOP bit and bus idle’ detect circuit is enabled. With the EN pin
Table 3. Pin descriptionVCC(A) 1 A side supply voltage (0.9 V to 5.5V)
SCLA 2 open-drain input/output serial clock A side bus
SDAA 3 open-drain input/output serial data A side bus
GND 4 supply ground (0V) 5 active HIGH repeater enable input with an internal pull-up (100 kΩ)
SDAB 6 open-drain input/output serial data B side bus
SCLB 7 open-drain input/output serial clock B side bus
VCC(B) 8 B side supply voltage (2.7 V to 5.5V)
NXP Semiconductors PCA9508
Hot swappable level translating I2 C-bus repeaterHIGH long enough to complete the initialization state (ten) and remaining HIGH when all
the SDA and SCL pins have been HIGH for the bus idle time or when all pins are HIGH
anda STOP conditionis seenon the SDAA and SCLA pins, SDAAis connectedto SDAB
and SCLA is connected to SCLB.
6.1 A side to B sideOnce connected, when the PCA9508 senses a LOW level on the A side (below
0.5VCC(A)),it turnson the correspondingB side driver (either SDAor SCL) and drives the side downto about 0.5V. When the external driver turns off, theA side will beginto rise
as it is pulled HIGH by the bus pull-up resistor. When the A side reaches 0.5VCC(A), the side driver turns off and both A and B will continue to rise. The result is two smooth
exponential rising edgeson both buses witha propagation delay between them whichisa
function of the RC time constant on the A side bus.
6.2 B side to A sideWhena LOW levelis sensedon theB side (below 0.4 V), the correspondingA side driver turnedonto drive theA sideto nearly0V. When the external driver turns off, theB side
will beginto riseasitis pulled HIGHby the bus pull-up resistor. When theB side reaches
0.5 V, the A side driver will turn off. The B side driver will remain at about 0.5 V until the side rises above 0.5VCC(A), then the B side will continue to rise. The result is a plateau
on the B side rising edge. See Figure 11.
6.3 Weak drive on B sideThe following condition shouldbe avoidedasit causes the PCA9508to createa glitchon
the bus. As long as I2 C-bus devices connected to the B side can pull the bus lines lower
than 0.4 V, this problem will never occur. When the B side falls first and goes below
0.3VCC(B), the A side driver is turned on and the A side is pulled down to 0V . The B side
pull-downis switchedon and unless theB sideis pulled below 0.4Vbyan external driver,
the A side pull-down will switch off and the A side will be pulled up by the pull-up resistor.
When the A side rises above 0.5VCC(A), the B side pull-down will turn off. To prevent this
glitch, it is necessary to make certain that the B side LOW level driven by an external
driver is below 0.4V.
6.4 Enable pin (EN)The EN pin is active HIGH with an internal pull-up to VCC(B) and allows the user to select
when the repeater is active. This can be used to isolate a badly behaved slave on
power-up until after the system power-up reset. It should never change state during an2 C-bus operation because disabling during a bus operation will hang the bus.
The EN pin should only change state when the global bus and the repeater port areinan
idle state to prevent system failures.
If the PCA9508 is enabled while the bus is active, the PCA9508 will connect at the first
STOP signal or at the first gap in activity that satisfies the internal idle bus time after the
enable sequence is complete.
NXP Semiconductors PCA9508
Hot swappable level translating I2 C-bus repeater
6.5I2 C-bus systemsAs with the standard I2 C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I2 C-bus).
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part designed to work with Standard-mode and
Fast-modeI2 C-bus devicesin additionto SMBus devices. Standard-modeI2 C-bus devices
only specify 3 mA output drive; this limits the termination current to 3 mA in a generic2 C-bus system where Standard-mode devices and multiple masters are possible. Under
certain conditions higher termination currents can be used.
Please see application note AN255, I2 C/SMBus Repeaters, Hubs and Expanders for
additional information on sizing resistors and precautions when using more than one
PCA9508 in a system or using the PCA9508 in conjunction with other bus buffers.
Application design-in informationA typical application is shown in Figure 4. In this example, the system master is runninga 3.3VI2 C-bus while the slaveis connectedtoa 1.2V bus. Both buses runat 400 kHz.
Master devices can be placed on either bus.
The PCA9508 is 5 V tolerant, so it does not require any additional circuitry to translate
between 0.9 V to 5.5 V bus voltages and 2.7 V to 5.5 V bus voltages.
When the A side of the PCA9508 is pulled LOW by a driver on the I2 C-bus, a comparator
detects the falling edge whenit goes below 0.5VCC(A) and causes the internal driveron the side to turn on, causing the B side to pull down to about 0.5 V. When the B side of the
PCA9508 falls, firsta CMOS hysteresis type input detects the falling edge and causes the
internal driver on the A side to turn on and pull the A side pin down to ground. In order to
illustrate what would be seen in a typical application, refer to Figure 7 and Figure 8. If the
bus masterin Figure4 wereto writeto the slave through the PCA9508, waveforms shown Figure7 wouldbe observedon theA bus. This looks likea normalI2 C-bus transmission
except that the HIGH level may be as low as 0.9 V, and the turn on and turn off of the
acknowledge signals are slightly delayed.
NXP Semiconductors PCA9508
Hot swappable level translating I2 C-bus repeaterOn the B bus side of the PCA9508, the clock and data lines would have a positive offset
from ground equal to the VOL of the PCA9508. After the 8th clock pulse, the data line will
be pulled to the VOL of the slave device, which is very close to ground in this example. At
the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9508 for a short delay while the A bus side rises above 0.5VCC(A) then it continues
HIGH.Itis importantto note that any arbitrationor clock stretching events require that the
LOW level on the B bus side at the input of the PCA9508 (VIL) be at or below 0.4 V to be
recognized by the PCA9508 and then transmitted to the A bus side.
Multiple PCA9508A sides canbe connectedina star configuration (Figure5), allowingall
nodes to communicate with each other.
Multiple PCA9508s can be connected in series (Figure 6) as long as the A side is
connected to the B side. I2 C-bus slave devices can be connected to any of the bus
segments. The number of devices that can be connected in series is limited by repeater
delay/time-of-flight considerations on the maximum bus speed requirements.
NXP Semiconductors PCA9508
Hot swappable level translating I2 C-bus repeater
NXP Semiconductors PCA9508
Hot swappable level translating I2 C-bus repeater Limiting values Static characteristics
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VCC(B) supply voltage port B 2.7 V to 5.5V −0.5 +7 V
VCC(A) supply voltage port A adjustable −0.5 +7 V
VI/O voltage on an input/output pin SDAA, SDAB, SCLA, SCLB, EN −0.5 +7 V input current any pin - 50 mA
Ptot total power dissipation - 100 mW
Tstg storage temperature −55 +125 °C
Tamb ambient temperature operating in free air −40 +85 °C junction temperature - +125 °C
Table 5. Static characteristicsVCC =2.7 V to 5.5 V; GND=0V; Tamb= −40 °Cto+85 °C; unless otherwise specified.
SuppliesVCC(B) supply voltage port B 2.7 - 5.5 V
VCC(A) supply voltage port A [1] 0.9 - 5.5 V
ICC(A) supply current port A pin VCC(A) -- 1 mA
ICCH HIGH-level supply current both channels HIGH;
VCC= 5.5V;
SDAn= SCLn= VCC 1.5 3 mA
ICCL LOW-level supply current both channels LOW;
VCC= 5.5 V; one SDA and
one SCL= GND; other SDA
and SCL open 1.5 3 mA
ICC(A)c contention port A supply current VCC= 5.5V;
SDAn= SCLn= VCC 1.5 3 mA
Input and output SDAB and SCLBVIH HIGH-level input voltage 0.7VCC(B)- 5.5 V
VIL LOW-level input voltage [2] −0.5 - +0.3VCC(B)V
VILc contention LOW-level input voltage −0.5 0.4 - V
VIK input clamping voltage II= −18 mA - - −1.2 V
ILI input leakage current VI= 3.6V - - ±1 μA
IIL LOW-level input current SDA, SCL; VI= 0.2V - - 10 μA
VOL LOW-level output voltage IOL= 100 μA or 6 mA 0.47 0.52 0.6 V
VOL−VILc difference between LOW-level
output and LOW-level input voltage
contention
guaranteed by design - - 70 mV
ILOH HIGH-level output leakage current VO =VCC -- 10 μA
Cio input/output capacitance VI=3 V or 0 V; VCC= 3.3V - 5.2 7 pF=3 V or 0 V; VCC=0V - 5.2 7 pF
NXP Semiconductors PCA9508
Hot swappable level translating I2 C-bus repeater[1] LOW-level supply voltage.
[2] VIL specificationisforthe first LOW level seenbythe SDAB/SCLB lines. VILcisforthe second and subsequent LOW levels seenbythe
SDAB/SCLB lines.
Input and output SDAA and SCLAVIH HIGH-level input voltage 0.6VCC(A) 0.5VCC(A) 5.5 V
VIL LOW-level input voltage −0.5 - +0.4VCC(A)V
VIK input clamping voltage II= −18 mA - - −1.2 V
ILI input leakage current VI= 3.6V - - ±1 μA
IIL LOW-level input current SDA, SCL; VI= 0.2V - - 10 μA
VOL LOW-level output voltage IOL=6 mA - 0.1 0.2 V
ILOH HIGH-level output leakage current VO =VCC -- 10 μA
Cio input/output capacitance VI=3 V or 0 V; VCC= 3.3V - 5.2 7 pF=3 V or 0 V; VCC=0V - 5.2 7 pF
EnableVIL LOW-level input voltage −0.5 - +0.3VCC(B)V
VIH HIGH-level input voltage 0.7VCC(B)- 5.5 V
IIL(EN) LOW-level input current on pin EN VI= 0.2 V, EN; VCC= 3.6V - −10 −30 μA
ILI input leakage current VI =VCC −1- +1 μA input capacitance VI= 3.0 V or 0V - 1.7 7 pF
Table 5. Static characteristics …continuedVCC =2.7 V to 5.5 V; GND=0V; Tamb= −40 °Cto+85 °C; unless otherwise specified.
NXP Semiconductors PCA9508
Hot swappable level translating I2 C-bus repeater
10. Dynamic characteristics[1] Times are specified with loads of 1.35 kΩ pull-up resistance and 57 pF load capacitance on the B side, and 167 Ω pull-up resistance
and 57 pF load capacitance on the A side. Different load resistance and capacitance will alter the RC time constant, thereby changing
the propagation delay and transition times.
[2] Pull-up voltages are VCC(A) on the A side and VCC(B) on the B side.
[3] Typical values were measured with VCC(A)=3.3 V at Tamb =25 °C, unless otherwise noted.
[4] The tPLH delay data fromB sidetoA sideis measuredat0.5VontheB sideto 0.5VCC(A)ontheA side when VCC(A)is less than2V, and
1.5 V on the A side if VCC(A) is greater than 2V.
[5] Typical value measured with VCC(A)=2.7 V at Tamb =25°C.
[6] The proportional delay data from A side to B side is measured at 0.3VCC(A) on the A side to 1.5 V on the B side.
[7] Defined as the time required to connect from B side to A side, after B side switches from active to idle, when A side is idle.
[8] Defined as the time required to connect from B side to A side, when B side and A side are idle.
[9] Defined as the time required to connect A side to B side, when B side is idle and A side is going active from idle, by a STOP condition.
[10] The enable pin, EN, should only change state when the global bus and the repeater port are in an idle state.
Table 6. Dynamic characteristicsVCC =2.7 V to 5.5 V; GND=0V; Tamb= −40 °Cto+85 °C; unless otherwise specified. [1][2]
tPLH LOW-to-HIGH propagation delay B side to A side; Figure11 [4] 100 170 250 ns
tPHL HIGH-to-LOW propagation delay B side to A side; Figure9
VCC(A)< 3.0V [5] 20 98 118 ns
VCC(A)> 3.0V 20 76 164 ns
tTLH LOW to HIGH output transition time A side; Figure10 10 20 30 ns
tTHL HIGH to LOW output transition time A side; Figure10
VCC(A)< 2.7V [5]1 7283ns
VCC(A)> 3.0V 8 68 137 ns
tPLH LOW-to-HIGH propagation delay A side to B side; Figure10 [6] 25 53 110 ns
tPHL HIGH-to-LOW propagation delay A side to B side; Figure10 [6] 60 79 230 ns
tTLH LOW to HIGH output transition time B side; Figure9 120 140 170 ns
tTHL HIGH to LOW output transition time B side; Figure9 30 48 90 ns
tconnect connect time[7] B side to A side; Figure12 - 0.5 - μs
tidle(connect) connect idle time[8] B side to A side; Figure13 50 105 200 μs
tstop(connect) connect stop time[9] A side to B side; Figure14 - 0.5 - μs
tsu set-up time EN HIGH before START condition [10] 100 - - ns hold time EN HIGH after STOP condition [10] 100 - - ns
