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PEF82912FV1.3 . ,Q-SMINTI (2B1Q Second Gen. Modular IS...Data Sheet, DS 1, March 2001®Q-SMINT I2B1Q Second Gen. Modular ISDN NT (Intelligent)PEF 82912/82913 ..
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PCA9511AD-PCA9511ADP
Hot swappable I2C-bus and SMBus bus buffer
General descriptionThe PCA9511A is a hot swappable I2 C-bus and SMBus buffer that allows I/O card
insertion into a live backplane without corrupting the data and clock buses. Control
circuitry prevents the backplane from being connectedto the card untila stop commandor
bus idle occurs on the backplane without bus contention on the card. When the
connection is made, the PCA9511A provides bidirectional buffering, keeping the
backplane and card capacitances isolated.
The PCA9511A rise time accelerator circuitry allows the use of weaker DC pull-up
currents while still meeting rise time requirements. The PCA9511A incorporates a digital
ENABLE input pin, which enables the device when asserted HIGH and forces the device
intoa low current mode when asserted LOW, andan open-drain READY output pin, which
indicates that the backplane and card sides are connected together (HIGH) or not (LOW).
During insertion, the PCA9511A SDA and SCL lines are precharged to 1 V to minimize
the current required to charge the parasitic capacitance of the chip.
Features Bidirectional buffer for SDA and SCL lines increases fan out and prevents SDA and
SCL corruption during live board insertion and removal from multipoint backplane
systems Compatible with I2 C-bus Standard-mode, I2 C-bus Fast-mode, and SMBus standards Built-in ΔV/Δt rise time accelerators on all SDA and SCL lines (0.6 V threshold)
requires the bus pull-up voltage and supply voltage (VCC) to be the same Active HIGH ENABLE input Active HIGH READY open-drain output High-impedance SDA and SCL pins for VCC =0V1 V precharge on all SDA and SCL lines Supporting clock stretching and multiple master arbitration/synchronization Operating power supply voltage range: 2.7 V to 5.5V0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8, TSSOP8 (MSOP8)
PCA9511A
Hot swappable I2 C-bus and SMBus bus buffer
Rev. 04 — 19 August 2009 Product data sheet
NXP Semiconductors PCA9511A
Hot swappable I2 C-bus and SMBus bus buffer Applications cPCI, VME, AdvancedTCA cards and other multipoint backplane cards that are
required to be inserted or removed from an operating system
Feature selection Ordering information[1] Also known as ‘MSOP8’.
Table 1. Feature selection chartidle detect yes yes yes yes yes
high-impedance SDA, SCL pins for VCC=0V yes yes yes yes yes
rise time accelerator circuitry on SDAn and SCLn lines - yes yes yes yes
rise time accelerator circuitry hardware disable pin for
lightly loaded systems
--yes --
rise time accelerator threshold 0.8 V versus 0.6V
improves noise margin
---yes yes
ready open-drain output yes yes - yes yes
two VCC pinsto support5Vto 3.3V level translation with
improved noise margins
--yes -- V precharge on all SDA and SCL lines in only yes yes - - μA current source on SCLIN and SDAIN for PICMG
applications
---yes -
Table 2. Ordering informationTamb= −40°Cto +85°C
PCA9511AD PA9511A SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PCA9511ADP 9511A TSSOP8[1] plastic thin shrink small outline package; 8 leads;
body width3 mm
SOT505-1
NXP Semiconductors PCA9511A
Hot swappable I2 C-bus and SMBus bus buffer Block diagram
NXP Semiconductors PCA9511A
Hot swappable I2 C-bus and SMBus bus buffer Pinning information
7.1 Pinning
7.2 Pin description Functional descriptionRefer to Figure 1 “Block diagram of PCA9511A”.
8.1 Start-upAn undervoltage/initialization circuit holds the parts in a disconnected state which
presents high-impedance to all SDA and SCL pins during power-up. A LOW on the
ENABLE pin also forces the parts into the low current disconnected state when the ICC is
essentially zero.As the power supplyis broughtup and the ENABLEis HIGHor the partis
powered and the ENABLE is taken from LOW to HIGH it enters an initialization state
where the internal references are stabilized and the precharge circuit is enabled. At the
end of the initialization state the ‘Stop Bit And Bus Idle’ detect circuit is enabled. With the
ENABLE pin HIGH long enough to complete the initialization state (ten) and remaining
HIGH when all the SDA and SCL pins have been HIGH for the bus idle time or when all
pins are HIGH and a STOP condition is seen on the SDAIN and SCLIN pins, SDAIN is
connected to SDAOUT and SCLIN is connected to SCLOUT. The 1 V precharge circuitry
Table 3. Pin descriptionENABLE 1 Chip enable. Grounding this input puts the part in a low current (<1 μA)
mode. It also disables the rise time accelerators, isolates SDAIN from
SDAOUT and isolates SCLIN from SCLOUT.
SCLOUT 2 serial clock output to and from the SCL bus on the card
SCLIN 3 serial clock input to and from the SCL bus on the backplane
GND 4 Ground. Connect this pin to a ground plane for best results.
READY 5 open-drain output which pulls LOW when SDAIN and SCLIN are
disconnected from SDAOUT and SCLOUT, and goes HIGH when the two
sides are connected
SDAIN 6 serial data input to and from the SDA bus on the backplane
SDAOUT 7 serial data output to and from the SDA bus on the card
VCC 8 power supply
NXP Semiconductors PCA9511A
Hot swappable I2 C-bus and SMBus bus bufferis activated during the initialization and is deactivated when the connection is made. The
precharge circuitry pulls up the SDA and SCL pins to 1 V through individual 100 kΩ
nominal resistors. This precharges the pins to 1 V to minimize the worst case
disturbances that result from insertinga card into the backplane where the backplane and
the card are at opposite logic levels.
8.2 Connect circuitryOnce the connection circuitryis activated, the behaviorof SDAIN and SDAOUTas wellas
SCLIN and SCLOUT become identical with each acting as a bidirectional buffer that
isolates the input capacitance from the output bus capacitance while communicating the
logic levels. A LOW forced on either SDAIN or SDAOUT will cause the other pin to be
driven to a LOW by the part. The same is also true for the SCL pins. Noise between
0.7VCC and VCC is generally ignored because a falling edge is only recognized when it
falls below 0.7VCC with a slew rate of at least 1.25 V/μs. When a falling edge is seen on
one pin, the other pin in the pair turns on a pull-down driver that is referenced to a small
voltage above the falling pin. The driver will pull the pin downata slew rate determinedby
the driver and the load initially, because it does not start until the first falling pin is below
0.7VCC. The first falling pin may have a fast or slow slew rate, if it is faster than the pull
down slew rate then the initial pull-down rate will continue.If the first falling pin hasa slow
slew rate then the second pin will be pulled down at its initial slew rate only until it is just
above the first pin voltage then they will both continue down at the slew rate of the first.
Once both sides are LOW they will remain LOW untilall the external drivers have stopped
driving LOWs. If both sides are being driven LOW to the same value for instance, 10 mV
by external drivers, which is the case for clock stretching and is typically the case for
acknowledge, and one side external driver stops driving that pin will rise until the internal
driver pulls it down to the offset voltage. When the last external driver stops driving a
LOW, that pin will riseup and settle out just above the other pinas both rise together with slew rate determinedby the internal slew rate control and the RC time constant. As long
as the slew rate is at least 1.25 V/μs, when the pin voltage exceeds 0.6 V for the
PCA9511A, the rise time accelerator’s circuits are turned on and the pull-down driver is
turned off.
8.3 Maximum number of devices in seriesEach buffer adds about 0.1V dynamic level offsetat25°C with the offset largerat higher
temperatures. Maximum offset (Voffset) is 0.150 V with a 10 kΩ pull-up resistor. The LOW
level at the signal origination end (master) is dependent upon the load and the only
specification point is that the I2 C-bus specification of 3 mA will produce VOL< 0.4V,
althoughif lightly loaded the VOL maybe ~0.1V. Assuming VOL= 0.1V and Voffset= 0.1V,
the level after four buffers wouldbe 0.5V, whichis only about 0.1V below the thresholdof
the rising edge accelerator (about 0.6 V). With great care a system with four buffers may
work, butas the VOL movesup from 0.1V, noiseor bounceson the line will resultin firing
the rising edge accelerator thus introducing false clock edges. Generally it is
recommended to limit the number of buffers in series to two, and to keep the load light to
minimize the offset.
The PCA9510A (rise time accelerator is permanently disabled) and the PCA9512A (rise
time accelerator canbe turned off) area little different with the rise time accelerator turned
off because the rise time accelerator will not pull the node up, but the same logic that turns
NXP Semiconductors PCA9511A
Hot swappable I2 C-bus and SMBus bus bufferon the accelerator turns the pull-down off. If the VIL is above ~0.6 V and a rising edge is
detected, the pull-down will turn off and will not turn back on until a falling edge is
detected.
Consider a system with three buffers connected to a common node and communication
between the Master and SlaveB that are connectedat either endof bufferA and bufferB seriesas shownin Figure4. Considerif the VOLat the inputof bufferAis 0.3V and the
VOL of Slave B (when acknowledging) is 0.4 V with the direction changing from Master to
SlaveB and then from SlaveBto Master. Before the direction change you would observe
VILat the inputof bufferAof 0.3V andits output, the common node,is ~0.4V. The output
of buffer B and buffer C would be ~0.5 V, but Slave B is driving 0.4V , so the voltage at
SlaveBis 0.4V. The outputof bufferCis ~0.5V. When the Master pull-down turns off, the
inputof bufferA rises andso doesits output, the common node, becauseitis the only part
driving the node. The common node will rise to 0.5 V before buffer B’s output turns on, if
the pull-upis strong the node may bounce.If the bounce goes above the thresholdfor the
rising edge accelerator ~0.6 V the accelerators on both buffer A and buffer C will fire
contending with the output of buffer B. The node on the input of buffer A will go HIGH as
will the input node of buffer C. After the common node voltage is stable for a while the
rising edge accelerators will turn off and the common node will return to ~0.5 V because
the bufferBis still on. The voltageat both the Master and SlaveC nodes would then fallto
~0.6 V until Slave B turned off. This would not cause a failure on the data line as long as
the return to 0.5 V on the common node (~0.6 V at the Master and Slave C) occurred
before the data setup time. If this were the SCL line, the parts on buffer A and bufferC
would see a false clock rather than a stretched clock, which would cause a system error.
8.4 Propagation delaysThe delay for a rising edge is determined by the combined pull-up current from the bus
resistors and the rise time accelerator current source and the effective capacitanceon the
lines. If the pull-up currents are the same, any difference in rise time is directly
proportional to the difference in capacitance between the two sides. The tPLH may be
negativeif the output capacitanceis less than the input capacitance and wouldbe positive
if the output capacitance is larger than the input capacitance, when the currents are the
same.
The tPHL can never be negative because the output does not start to fall until the input is
below 0.7VCC, and the output turn on has a non-zero delay, and the output has a limited
maximum slew rate, and evenif the input slew rateis slow enough that the output catches
up it will still lag the falling voltage of the input by the offset voltage. The maximum tPHL
occurs when the input is driven LOW with zero delay and the output is still limited by its
NXP Semiconductors PCA9511A
Hot swappable I2 C-bus and SMBus bus bufferturn-on delay and the falling edge slew rate. The output falling edge slew rateisa function the internal maximum slew rate whichisa functionof temperature, VCC and process,as
well as the load current and the load capacitance.
8.5 Rise time acceleratorsDuring positive bus transitions a 2 mA current source is switched on to quickly slew the
SDA and SCL lines HIGH once the input level of 0.6 V for the PCA9511A is exceeded.
The rising edge rate shouldbeat least 1.25 V/μsto guarantee turnonof the accelerators.
The built-in ΔV/Δt rise time acceleratorsonall SDA and SCL lines requires the bus pull-up
voltage and supply voltage (VCC) to be the same.
8.6 READY digital outputThis pin providesa digital flag whichis LOW when either ENABLEis LOWor the start-up
sequence described earlier in this section has not been completed. READY goes HIGH
when ENABLE is HIGH and start-up is complete. The pin is driven by an open-drain
pull-down capable of sinking 3 mA while holding 0.4 V on the pin. Connect a resistor of kΩ to VCC to provide the pull-up.
8.7 ENABLE low current disableGrounding the ENABLE pin disconnects the backplane side from the card side, disables
the rise time accelerators, drives READY LOW, disables the bus precharge circuitry, and
puts the part in a low current state. When the pin voltage is driven all the way to VCC, the
part waits for data transactions on both the backplane and card sides to be complete
before reconnecting the two sides.
8.8 Resistor pull-up value selectionThe system pull-up resistors must be strong enough to provide a positive slew rate of
1.25 V/μson the SDA and SCL pins,in orderto activate the boost pull-up currents during
rising edges. Choose maximum resistor value using the formula given in Equation1:
(1)
where R is the pull-up resistor value in Ω, VCC(min) is the minimum VCC voltage in volts,
and C is the equivalent bus capacitance in picofarads (pF). addition, regardlessof the bus capacitance, always chooseR≤ 65.7 kΩfor VCC= 5.5V
maximum,R≤45 kΩfor VCC= 3.6V maximum. The start-up circuitry requires logic HIGH
voltages on SDAOUT and SCLOUT to connect the backplane to the card, and these
pull-up values are neededto overcome the precharge voltage. See the curvesin Figure5
and Figure 6 for guidance in resistor pull-up selection. 800 103× VCC min() 0.6– -----------------------------------≤
NXP Semiconductors PCA9511A
Hot swappable I2 C-bus and SMBus bus buffer
NXP Semiconductors PCA9511A
Hot swappable I2 C-bus and SMBus bus buffer
8.9 Hot swapping and capacitance buffering applicationFigure 7 through Figure 10 illustrate the usage of the PCA9511A in applications that take
advantage of both its hot swapping and capacitance buffering features. In all of these
applications, note that if the I/O cards were plugged directly into the backplane, all of the
backplane and card capacitances would add directly together, making rise time and
fall time requirements difficult to meet. Placing a bus buffer on the edge of each card,
however, isolates the card capacitance from the backplane. For a given I/O card, the
PCA9511A drives the capacitanceof everythingon the card and the backplane must drive
only the capacitance of the bus buffer, which is less than 10 pF , the connector, trace, and
all additional cards on the backplane.
See Application Note AN10160, ‘Hot Swap Bus Buffer’ for more information on
applications and technical assistance.
NXP Semiconductors PCA9511A
Hot swappable I2 C-bus and SMBus bus buffer
NXP Semiconductors PCA9511A
Hot swappable I2 C-bus and SMBus bus buffer Application design-in information
10. Limiting values[1] Voltages with respect to pin GND.
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VCC supply voltage [1] −0.5 +7 V voltage on SDAIN, SCLIN, SDAOUT,
SCLOUT, READY, ENABLE
[1] −0.5 +7 V
Toper operating temperature −40 +85 °C
Tstg storage temperature −65 +150 °C
Tsp solder point temperature 10 s max. - +300 °C
Tj(max) maximum junction temperature - +125 °C
NXP Semiconductors PCA9511A
Hot swappable I2 C-bus and SMBus bus buffer
11. Characteristics
Table 5. CharacteristicsVCC = 2.7 V to 5.5 V; Tamb= −40 °C to +85 V; unless otherwise specified.
Power supplyVCC supply voltage [1] 2.7 - 5.5 V
ICC supply current VCC= 5.5V;
VSDAIN =VSCLIN =0V
[1]- 3.5 6 mA
ICC(sd) Shut-down mode supply
current
VENABLE=0V;all other pinsat
VCC or GND 0.1 - μA
Start-up circuitryVpch precharge voltage SDA, SCL floating [1] 0.8 1.1 1.2 V
VIH(ENABLE) HIGH-level input voltage
on pin ENABLE 0.5× VCC 0.7× VCCV
VIL(ENABLE) LOW-level input voltage
on pin ENABLE
0.3 × VCC 0.5× VCC -V
II(ENABLE) input current on pin
ENABLE
VENABLE = 0 V to VCC - ±0.1 ±1 μA
ten enable time [2]- 110 - μs
tidle(READY) bus idle time to READY
active
[1] 50 105 200 μs
tdis(EN-RDY) disable time (ENABLEto
READY)
-30 - ns
tstp(READY) SDAIN to READY delay
after STOP
[3]- 1.2 - μs
tREADY SCLOUT/SDAOUT to
READY delay
[3]- 0.8 - μs
ILZ(READY) off-state leakage current
on pin READY
VENABLE =VCC - ±0.3 - μA
Ci(ENABLE) input capacitance on
pin ENABLE =VCC or GND [4]- 1.9 4.0 pF
Co(READY) output capacitance on
pin READY =VCC or GND [4]- 2.5 4.0 pF
VOL(READY) LOW-level output
voltage on pin READY
Ipu=3 mA; VENABLE =VCC [1]- - 0.4 V
Rise time acceleratorsItrt(pu) transient boosted pull-up
current
positive transition on SDA,
SCL; VCC= 2.7V;
slew rate= 1.25 V/μs
[5][6] 12 - mA
