PCA9515D-PCA9515DP Fast Delivery |IC PHOENIX CO.,LIMITED

PCA9515DP ,I2C-bus repeaterfeatures of the I C-bus system, it permits2extension of the I C-bus by buffering both the data (SDA ..
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PEF82912FV1.3 . ,Q-SMINTI (2B1Q Second Gen. Modular IS...Data Sheet, DS 1, March 2001®Q-SMINT I2B1Q Second Gen. Modular ISDN NT (Intelligent)PEF 82912/82913 ..
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PCA9515D-PCA9515DP
I2C-bus repeater
General descriptionThe PCA9515 is a BiCMOS integrated circuit intended for application in I2 C-bus and
SMBus systems.
While retaining all the operating modes and features of the I2 C-bus system, it permits
extension of the I2 C-bus by buffering both the data (SDAn) and the clock (SCLn) lines,
thus enabling two buses of 400 pF.
The I2 C-bus capacitance limit of 400 pF restricts the number of devices and bus length.
Using the PCA9515 enables the system designerto isolate two halvesofa bus, thus more
devicesor longer length canbe accommodated.It can alsobe usedto run two buses, one
at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz bus is
isolated when 400 kHz operation of the other is required.
Two or more PCA9515s cannot be put in series. The PCA9515 design does not allow
this conﬁguration. Since thereisno direction pin, slightly different ‘legal’ low voltage levels
are used to avoid lock-up conditions between the input and the output. A ‘regular low’
applied at the input of a PCA9515 will be propagated as a ‘buffered low’ with a slightly
higher value. When this ‘buffered low’ is applied to another PCA9515, PCA9516A, or
PCA9518A in series, the second PCA9515, PCA9516A, or PCA9518A will not recognize
it as a ‘regular low’ and will not propagate it as a ‘buffered low’ again. The
PCA9510A/9511A/9513A/9514A and PCA9512A cannot be used in series with the
PCA9515, PCA9516A, or PCA9518A but can be used in series with themselves since
they use shifting instead of static offsets to avoid lock-up conditions.
The PCA9515 SCLn/SDAnCiis about 200pF versus the normal<10pF when VCC =0V.
The newer PCA9515A should be used in applications where power is secured to the
repeater but an active bus remains on either set of SCLn/SDAn pins to prevent this
increasein bus loading. Additionally, the PCA9515A hasa wider voltage rangeof 2.3Vto
3.6 V and can be used in applications with lower voltage supply constraints. Features 2 channel, bidirectional bufferI2 C-bus and SMBus compatible Active HIGH repeater enable input Open-drain input/outputs Lock-up free operation Supports arbitration and clock stretching across the repeater Accommodates Standard-mode and Fast-mode I2 C-bus devices and multiple masters Powered-off high-impedance I2 C-bus pins Operating supply voltage range of 3.0 V to 3.6V
PCA95152 C-bus repeater
Rev. 09 — 23 April 2009 Product data sheet
NXP Semiconductors PCA95152 C-bus repeater 5.5 V tolerant I2 C-bus (SCLn, SDAn) and enable (EN) pins0 Hz to 400 kHz clock frequency1 ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8 and TSSOP8 (MSOP8) Ordering information
[1] Also known as MSOP8.
3.1 Ordering options Block diagram
The output pull-down of each internal buffer is set for approximately 0.5 V, while the input
threshold of each internal buffer is set about 0.07 V lower, when the output is internally
driven LOW. This prevents a lock-up condition from occurring. The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.
Table 1. Ordering information
PCA9515D SO8 plastic small outline package; 8 leads;
body width 3.9 mm
SOT96-1
PCA9515DP TSSOP8[1] plastic thin shrink small outline package; 8 leads;
body width3 mm
SOT505-1
Table 2. Ordering options
PCA9515D PCA9515 Tamb= −40 °C to +85°C
PCA9515DP 9515 Tamb= −40 °C to +85°C
NXP Semiconductors PCA95152 C-bus repeater Pinning information
5.1 Pinning
5.2 Pin description
Table 3. Pin description
n.c. 1 not connected
SCL0 2 serial clock bus 0
SDA0 3 serial data bus 0
GND 4 supply ground 5 active HIGH repeater enable input
SDA1 6 serial data bus 1
SCL1 7 serial clock bus 1
VCC 8 supply power
NXP Semiconductors PCA95152 C-bus repeater Functional description
The PCA9515 BiCMOS integrated circuit contains two identical buffer circuits which
enable I2 C-bus and similar bus systems to be extended without degradation of system
performance. (Refer to Figure 1 “Block diagram of PCA9515”.)
The PCA9515 BiCMOS integrated circuit contains two bidirectional open-drain buffers
speciﬁcally designed to support the standard low-level-contention arbitration of the2 C-bus. Except during arbitration or clock stretching, the PCA9515 acts like a pair of
non-inverting, open-drain buffers, one for SDA and one for SCL.
6.1 Enable
The EN pin is active HIGH with an internal pull-up and allows the user to select when the
repeater is active. This can be used to isolate a badly behaved slave on power-up until
after the system power-up reset.It should never change state duringanI2 C-bus operation
because disabling duringa bus operation will hang the bus and enabling part way through
a bus cycle could confuse the I2 C-bus parts being enabled.
The enable pin (EN) should only change state when the global bus and the repeater port
are in an idle state to prevent system failures.
6.2I2 C-bus systems
As with the standard I2 C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus. (Standard open-collector conﬁguration of the I2 C-bus.)
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part is designed to work with Standard-mode and
Fast-modeI2 C-bus devicesin additionto SMBus devices. Standard-modeI2 C-bus devices
only specify 3 mA output drive; this limits the termination current to 3 mA in a generic2 C-bus system where Standard-mode devices and multiple masters are possible. Under
certain conditions, higher termination currents can be used. Please see application note
AN255,“I2 C/SMBus Repeaters, Hubs and Expanders”for additional informationon sizing
resistors and precautions when using more than one PCA9515 in a system or using the
PCA9515 in conjunction with the P82B96.
NXP Semiconductors PCA95152 C-bus repeater Application design-in information
A typical application is shown in Figure 4. In this example, the system master is running
on a 3.3 V I2 C-bus while the slave is connected to a 5 V bus. Both buses run at 100 kHz
unless the slave bus is isolated and then the master bus can run at 400 kHz. Master
devices can be placed on either bus.
The PCA9515 is 5 V tolerant so it does not require any additional circuitry to translate
between the different bus voltages.
When one side of the PCA9515 is pulled LOW by a device on the I2 C-bus, a CMOS
hysteresis type input detects the falling edge and causes an internal driver on the other
side to turn on, thus causing the other side to also go LOW. The side driven LOW by the
PCA9515 will typically be at VOL= 0.5V.
In order to illustrate what would be seen in a typical application, refer to Figure 5 and
Figure6.If the bus masterin Figure4 wereto writeto the slave through the PCA9515, we
would see the waveform shown in Figure 5 on Bus 0. This looks like a normal I2 C-bus
transmission until the falling edgeof the8th clock pulse.At that point, the master releases
the data line (SDA) while the slave pullsit LOW through the PCA9515. Because the VOLof
the PCA9515 is typically around 0.5V , a step in the SDA will be seen. After the master
has transmitted the 9th clock pulse, the slave releases the data line.
On the Bus 1 side of the PCA9515, the clock and data lines would have a positive offset
from ground equal to the VOL of the PCA9515. After the 8th clock pulse, the data line will
be pulled to the VOL of the slave device that is very close to ground in our example.
It is important to note that any arbitration or clock stretching events on Bus 1 require that
the VOLof the deviceson Bus1be70 mV below the VOLof the PCA9515 (see VOL−VILcin
Section 9 “Static characteristics”) to be recognized by the PCA9515 and then transmitted
to Bus0.
NXP Semiconductors PCA95152 C-bus repeater Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages with respect to GND.
VCC supply voltage −0.5 +7 V
Vbus voltage range I2 C-bus SCL or SDA −0.5 +7 V DC current any pin - 50 mA
Ptot total power dissipation - 100 mW
Tstg storage temperature −55 +125 °C
Tamb ambient temperature operating −40 +85 °C
NXP Semiconductors PCA95152 C-bus repeater Static characteristics
[1] VIL speciﬁcation is for the ﬁrst LOW level seen by the SDAn/SCLn lines. VILc is for the second and subsequent LOW levels seen by the
SDAn/SCLn lines.
[2] The SCLn/SDAn Ci is about 200 pF when VCC=0 V. The PCA9515A should be used in applications where power is secured to the
repeater but an active bus remains on either set of SCLn/SDAn pins.
Table 5. Static characteristics
VCC =3.0 V to 3.6 V; GND=0V; Tamb= −40 °C to +85 °C; unless otherwise speciﬁed.
Supplies
VCC supply voltage 3.0 3.3 3.6 V
ICCH HIGH-level supply current both channels HIGH;
VCC= 3.6V;
SDAn= SCLn= VCC 2.3 5 mA
ICCL LOW-level supply current both channels LOW;
VCC= 3.6 V; one SDA
and one SCL= GND,
other SDA and SCL open 2.3 5 mA
ICCLc contention LOW-level supply current VCC= 3.6V;
SDAn= SCLn= GND 2.1 5 mA
Input SCLn; input/output SDAn
VIH HIGH-level input voltage 0.7VCC- 5.5 V
VIL LOW-level input voltage [1] −0.5 - +0.3VCC V
VILc contention LOW-level input voltage [1] −0.5 - +0.4 V
VIK input clamping voltage II= −18 mA - - −1.2 V
ILI input leakage current VI= 3.6V −1- +1 μA
IIL LOW-level input current SDA, SCL; VI= 0.2V - - 10 μA
VOL LOW-level output voltage IOL=0 mA or 6 mA 0.47 0.52 0.6 V
VOL−VILc difference between LOW-level
output and LOW-level input voltage
contention
guaranteed by design - - 70 mV
ILOH HIGH-level output leakage current VO= 3.6V - - 10 μA input capacitance VI=3 V or 0V - 6 7[2] pF
Enable input EN
VIL LOW-level input voltage −0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
IIL LOW-level input current EN; VI= 0.2V - 10 30 μA
ILI input leakage current −1- +1 μA input capacitance VI= 3.0 V or 0V - 6 7 pF
NXP Semiconductors PCA95152 C-bus repeater
10. Dynamic characteristics
[1] The tTLH transition time is speciﬁed with loads of 1.35 kΩ pull-up resistance and 7 pF load capacitance, plus an additional 50 pF load
capacitance. Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and
transition times.
11. Test information
Table 6. Dynamic characteristics
VCC =3.0 V to 3.6 V; GND=0V; Tamb= −40 °C to +85 °C; unless otherwise speciﬁed.
tPHL HIGH to LOW propagation delay Figure7 57 98 170 ns
tPLH LOW to HIGH propagation delay Figure7 33 55 78 ns
tTHL HIGH to LOW output transition time Figure7 -67 - ns
tTLH LOW to HIGH output transition time Figure7 [1]- 135 - ns
tsu set-up time EN to START condition 100 - - ns hold time EN after STOP condition 100 - - ns

Partno	Mfg	Dc	Qty	Available	Descript
PCA9515D	NXP	N/a	428	avai	I2C-bus repeater
PCA9515DP	TI	N/a	1337	avai	I2C-bus repeater