PCA9518PW Fast Delivery |IC PHOENIX CO.,LIMITED

PCA9518PW ,Expandable 5-channel I2C-bus hubFeaturesn Expandable 5 channel, bidirectional buffer2n I C-bus and SMBus compatiblen Active HIGH in ..
PCA9518PWR ,Expandable Five-Channel I2C Hub 20-TSSOP -40 to 85Block Diagram..... 93 Revision History........ 28.2 Feature Description.... 104 Description (Contin ..
PCA9527DP ,3-channel bidirectional bus extender for HDMI, I2C-bus and SMBusfeatures as the SDAA and SCLA, butit does not have the rise time accelerator and is powered and ref ..
PCA9530DP ,2-bit I2C-bus LED dimmerapplications.The PCA9530 contains an internal oscillator with two user programmable blink rates and ..
PCA9531 ,8-bit I2C LED dimmer
PCA9531D ,8-bit I2C-bus LED dimmer
PEMB1 ,PNP resistor-equipped transistors R1 = 22kOhm/R2 = 22kOhmLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
PEMB13 ,PNP/PNP resistor-equipped transistors; R1 = 4.7 k惟, R2 = 47 k惟
PEMB18 ,PEMB18; PUMB18; PNP/PNP resistor-equipped transistors; R1 = 4.7 kOhm, R2 = 10 kOhmapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..
PEMB19 ,PNP/PNP resistor-equipped transistors; R1 = 22 kOhm, R2 = openapplications1.4 Quick reference dataTable 2: Quick reference dataSymbol Parameter Conditions Min Ty ..
PEMB3 ,PNP resistor-equipped double transistor R1 = 4.7 kOhm, R2 = openLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
PEMB30 ,PNP/PNP double resistor-equipped transistors; R1 = 2.2 kOhm, R2 = openApplicationsn Low current peripheral driver n Cost-saving alternative for BC857BSand BC857BVn Contr ..

PCA9518PW
Expandable 5-channel I2C-bus hub
General descriptionThe PCA9518 is a BiCMOS integrated circuit intended for application in I2 C-bus and
SMBus systems.
While retaining all the operating modes and features of the I2 C-bus system, it permits
extension of the I2 C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus
enabling virtually an unlimited number of buses of 400pF.
The I2 C-bus capacitance limit of 400 pF restricts the number of devices and bus length.
Using the PCA9518 enables the system designer to divide the bus into an unlimited
numberof segmentsoffofa hub where any segmentto segment transition sees only one
repeater delay and is multiple master capable on each segment.
Using multiple PCA9518 parts, any width hub (in multiples of ﬁve)1 can be implemented
using the expansion pins.
The PCA9518 is a wider voltage range (2.3 V to 3.6 V) version of the PCA9518 and also
improves partial power-down performance, keeping I2 C-bus I/O pins in high-impedance
state when VDD is below 2.0V.
A PCA9518 cluster cannot be put in series with a PCA9515/16 or with another
PCA9518 cluster. Multiple PCA9518 devices can be grouped with other PCA9518
devices into any size cluster thanks to the EXPxxxn pins that allow the I2 C-bus signals to sent/received from/to one PCA9518 to/from another PCA9518 within the cluster. Since
there is no direction pin, slightly different ‘legal’ low voltage levels are used to avoid
lock-up conditions between the input and the output of individual repeaters in the cluster.
A ‘regular LOW’ applied at the input of any of the PCA9518 devices will then be
propagated as a ‘buffered LOW’ with a slightly higher value to all enabled outputs in the
PCA9518 cluster. When this ‘buffered LOW’ is applied to a PCA9515 and PCA9516 or
separate PCA9518 cluster (not connected via the EXPxxxn pins) in series, the second
PCA9515 and PCA9516 or PCA9518 cluster will not recognize it as a ‘regular LOW’ and
will not propagate it as a ‘buffered LOW’ again. The PCA9510/9511/9513/9514 and
PCA9512 cannotbe usedin series with the PCA9515 and PCA9516or PCA9518, but can
be used in series with themselves since they use shifting instead of static offsets to avoid
lock-up conditions.
PCA9518
Expandable 5-channel I2 C-bus hub
Rev. 05 — 2 December 2008 Product data sheet Only four ports per device are available if individual Enable is required.
NXP Semiconductors PCA9518
Expandable 5-channel I2 C-bus hub Features Expandable 5 channel, bidirectional bufferI2 C-bus and SMBus compatible Active HIGH individual repeater enable inputs Open-drain input/outputs Lock-up free operation Supports arbitration and clock stretching across the repeater Accommodates Standard-mode and Fast-mode I2 C-bus devices and multiple masters Powered-off high-impedance I2 C-bus pins Operating supply voltage range of 3.0 V to 3.6V5 V tolerant I2 C-bus and enable pins0 Hz to 400 kHz clock frequency2 ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Package offerings: SO20 and TSSOP20 Ordering information The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.
Table 1. Ordering information
Tamb= −40 °C to +85°C
PCA9518D PCA9518D SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
PCA9518PW PCA9518 TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
NXP Semiconductors PCA9518
Expandable 5-channel I2 C-bus hub Block diagram
A more detailed view of Figure 1 buffer is shown in Figure2.
The output pull-down voltage of each internal buffer is set for approximately 0.5 V, while
the input threshold of each internal buffer is set about 0.07 V lower, when the output is
internally driven LOW. This prevents a lock-up condition from occurring.
NXP Semiconductors PCA9518
Expandable 5-channel I2 C-bus hub Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description
EXPSCL1 1 expandable serial clock pin 1
EXPSCL2 2 expandable serial clock pin 2
SCL0 3 serial clock bus 0
SDA0 4 serial data bus 0
SCL1 5 serial clock bus 1
SDA1 6 serial data bus 1
EN1 7 active HIGH bus 1 enable input
SCL2 8 serial clock bus 2
SDA2 9 serial data bus 2
GND 10 supply ground
EN2 11 active HIGH bus 2 enable input
SCL3 12 serial clock bus 3
SDA3 13 serial data bus 3
EN3 14 active HIGH bus 3 enable input
SCL4 15 serial clock bus 4
SDA4 16 serial data bus 4
EN4 17 active HIGH bus 4 enable input
EXPSDA1 18 expandable serial data pin 1
EXPSDA2 19 expandable serial data pin 2
VCC 20 supply voltage
NXP Semiconductors PCA9518
Expandable 5-channel I2 C-bus hub Functional description
The PCA9518 BiCMOS integrated circuit is a ﬁve-way hub repeater, which enables2 C-bus and similar bus systems to be expanded in increments of ﬁve with only one
repeater delay and no functional degradation of system performance.
The PCA9518 BiCMOS integrated circuit contains ﬁve multi-directional, open-drain buffers
speciﬁcally designed to support the standard low-level contention arbitration of the2 C-bus. Except during arbitration or clock stretching, the PCA9518 acts like a pair of
non-inverting, open-drain buffers, one for SDA and one for SCL.
Refer to Figure 1 “Block diagram of PCA9518”.
6.1 Enable
The enable pins EN1 through EN4 are active HIGH and have internal pull-up resistors.
Each enable pin ENn controlsits associated SDAn and SCLn ports. When LOW, the ENn
pin blocks the inputs from SDAn and SCLn, as well as disabling the output drivers on the
SDAn and SCLn pins. The enable pins should only change state when both the global bus
and the local port are in an idle state to prevent system failures.
The active HIGH enable pins allow the useof open-drain drivers which canbe wire-ORed
to create a distributed enable where either centralized control signal (master) or spoke
signal (sub-master) can enable the channel when it is idle.
Unused channels must have pull-up resistors unless their enable pin (ENn) is always
LOW. Port 0 must always have pull-up resistors since it is always present in the bus and
cannot be disabled.
6.2 Expansion
The PCA9518 includes 4 open-drain I/O pins used for expansion. Two expansion pins,
EXPSDA1 and EXPSDA2 are used to communicate the internal state of the serial data
within each hubto the other hubs. The EXPSDA1 pinsofall hubs are connected together forman open-drain bus. Similarly,all EXPSDA2 pins, EXPSCL1 pins, andall EXPSCL2
pins are connected together forming a 4-wire bus between hubs.
When it is necessary to be able to deselect every port, each expansion device only
contributes 4 ports which can be enabled or disables because the ﬁfth does not have an
enable pin.
Pull-up resistors are required on the EXPxxxn3 pins even if only one PCA9518 is used.
6.3I2 C-bus systems
As with the standard I2 C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus. (Standard open-collector or open-drain conﬁguration of
the I2 C-bus). The size of these pull-up resistors depends on the system, but each side of
the repeater must have a pull-up resistor. This part is designed to work with
Standard-mode (0 Hz to 100 kHz) and Fast-mode (0 Hz to 400 kHz) I2 C-bus devices in
addition to SMBus devices. Standard-mode I2 C-bus devices only specify 3 mA output
drive; this limits the termination current to 3 mA in a generic I2 C-bus system where ‘xxxn’ is SDA1, SDA2, SCL1 or SCL2. ‘xxx’ is SDA or SCL.
NXP Semiconductors PCA9518
Expandable 5-channel I2 C-bus hub
Standard-mode devices and multiple masters are possible. Please see application note
AN255, I2 C/SMBus Repeaters, Hubs and Expanders for additional information on sizing
resistors. Application design-in information
A typical application is shown in Figure 5. In this example, the system master is running
on a 3.3 V I2 C-bus while the slaves are connected to a 3.3 V or 5 V bus. All buses run at
100 kHz unless slave 3, slave 4 and slave 5 are isolated from the bus. Then the master
bus and slave 1, slave 2 and slave 6 can run at 400 kHz.
Any segmentof the hub can talkto any other segmentof the hub. Bus masters and slaves
can be located on any segment with 400 pF load allowed on each segment.
The PCA9518 is 5 V tolerant, so it does not require any additional circuitry to translate
between the different bus voltages.
When one port of the PCA9518 is pulled LOW by a device on the I2 C-bus, a CMOS
hysteresis type input detects the falling edge and drives the EXPxxx1 line LOW, when the
EXPxxx1 voltage is less than 0.5VCC, the other ports are pulled down to the VOL of the
PCA9518 which is typically 0.5V.
In order to illustrate what would be seen in a typical application, refer to Figure 6. If the
bus masterin Figure5 wereto writeto the slave through the PCA9518, we would see the
waveform shown in Figure 6. This looks like a normal I2 C-bus transmission except for the
small foot preceding each clock LOW-to-HIGH transition and proceeding each data
LOW-to-HIGH transitionfor the master. The foot heightis the difference between the LOW
level driven by the master and the higher voltage LOW level driven by the PCA9518
repeater.Its width correspondstoan effective clock stretching coming from the PCA9518
that delays the rising edge of the clock. That same magnitude of delay is seen on the
rising edgeof the data. The footon the rising edgeof the datais extended through the9th
clock pulse as the PCA9518 repeats the acknowledge from the slave to the master. The
clock of the slave looks normal except the VOL is the ~0.5 V level generated by the
PCA9518. The SDA at the slave has a particularly interesting shape during the 9th clock
cycle where the slave pulls the line below the value driven by the PCA9518 during the
acknowledge and then returns to the PCA9518 level creating a foot before it completes
the LOW-to-HIGH transition. SDA lines other than the one with the master and the one
with the slave have a uniform LOW level driven by the PCA9518 repeater.
The other four waveforms are the expansion bus signals and are included primarily for
timing reference points. All timing on the expansion bus is with respect to 0.5VCC.
EXPSDA1 is the expansion bus that is driven LOW whenever any SDA pin falls below
0.3VCC. EXPSDA2 is the expansion bus that is driven LOW whenever any pin is ≤0.4V.
EXPSCL1 is the expansion bus that is driven LOW whenever any SCL pin falls below
0.3VCC. EXPSCL2 is the expansion bus that is driven LOW whenever any SCL pin is
≤0.4 V. The EXPSDA2 returns HIGH after the SDA pin that was the last one being held
below 0.4 V by an external driver starts to rise. The last SDA to rise above 0.4 V is held
downby the PCA9518to ~0.5V until after the delayof the circuit which determines thatit
was the last to rise, then it is allowed to rise above the ~0.5 V level driven by the
PCA9518. Considering the bus 0 SDA to be the last one to go above 0.4 V, then the
EXPSDA1 returnsto HIGH after the EXPSDA2is HIGH and either the bus0 SDA rise time
NXP Semiconductors PCA9518
Expandable 5-channel I2 C-bus hub
is 1 μs or, when the bus 0 SDA reaches 0.7VCC, whichever occurs ﬁrst. After both
EXPSDA2 and EXPSDA1 are HIGH the rest of the SDA lines are allowed to rise. The
same description applies for the EXPSCL1, EXPSCL2, and SCL pins.
NXP Semiconductors PCA9518
Expandable 5-channel I2 C-bus hub
It is important to note that any arbitration or clock stretching events on Bus 1 require that
the VOLof the deviceson Bus1be70 mV below the VOLof the PCA9518 (see VOL−VILcin
Section 9 “Static characteristics”) to be recognized by the PCA9518 and then transmitted
to Bus0.
NXP Semiconductors PCA9518
Expandable 5-channel I2 C-bus hub Limiting values
[1] Voltages with respect to pin GND.
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VCC supply voltage VCC to GND [1] −0.5 +7 V
VI2C-bus I2 C-bus voltage SCL or SDA [1] −0.5 +7 V input current any pin - 50 mA
Ptot total power dissipation - 300 mW
Tstg storage temperature −55 +125 °C
Tamb ambient temperature operating −40 +85 °C
NXP Semiconductors PCA9518
Expandable 5-channel I2 C-bus hub Static characteristics
[1] VIL speciﬁcation is for the ﬁrst LOW level seen by the SDAn/SCLn lines.
[2] VILc is for the second and subsequent LOW levels seen by the SDAn/SCLn lines.
[3] Test performed with IOL =10μA.
Table 4. Static characteristics
VCC =3.0 V to 3.6 V; GND=0V; Tamb= −40 °Cto+85 °C; unless otherwise speciﬁed.
Supplies
VCC supply voltage 3.0 3.3 3.6 V
ICCH HIGH-level supply current both channels HIGH
VCC= 3.6V;
SDAn= SCLn= VCC 7.5 10 mA
ICCL LOW-level supply current both channels LOW
VCC= 3.6V;
one SDA and one SCL= GND;
other SDA and SCL open 9 11 mA
ICCLc contention LOW-level supply
current
VDD= 3.6 V; SDAn= SCLn= VSS - 9 11 mA
Input SCL; input/output SDA
VIH HIGH-level input voltage SCL, SDA 0.7VCC - 5.5 V
VIL LOW-level input voltage SCL, SDA [1] −0.5 - +0.3VCC V
VILc contention LOW-level input voltage SCL, SDA [2] −0.5 - +0.4 V
VIK input clamping voltage II= −18 mA - - −1.2 V
ILI input leakage current VI= 3.6V - - ±1 μA
IIL LOW-level input current SCL, SDA; VI= 0.2V - - 20 μA
VOL LOW-level output voltage SCL, SDA; IOL =0mA[3] mA 0.47 0.52 0.6 V
VOL−VILc difference between LOW-level
outputand LOW-level input voltage
contention
guaranteed by design - - 70 mV input capacitance VI =3V or 0V - 6 8 pF
Enable 1 to Enable 4 (EN1 to EN4)
VIL LOW-level input voltage −0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
IIL LOW-level input current VI= 0.2 V; EN1 to EN4 - 10 30 μA
ILI input leakage current −1- +1 μA input capacitance VI= 3.0 V or 0V - 3 7 pF
Expansion pins (EXPSCL1, EXPSCL2, EXPSDA1, EXPSDA2)
VIH HIGH-level input voltage EXPxxxn 0.55VCC- 5.5 V
VIL LOW-level input voltage EXPxxxn −0.5 - +0.45VCCV
IIL LOW-level input current EXPxxxn; VI= 0.2V - - 5 μA
VOL LOW-level output voltage EXPxxxn; IOL =12mA - - 0.5 V input capacitance VI= 3.0 V or 0V - 6 8 pF
NXP Semiconductors PCA9518
Expandable 5-channel I2 C-bus hub
10. Dynamic characteristics
[1] The SDA and SCL propagation delays are dominated by rise times or fall times. The fall times are mostly internally controlled and are
only sensitive to load capacitance. The rise times are RC time constant controlled and therefore a speciﬁc numerical value can only be
given for ﬁxed RC time constants.
[2] The SDA HIGHto LOW propagation delay includesthefall time from VCCto 0.5VCCofthe EXPSDA1or EXPSCL1 pins andthe SDAor
SCL fall time from the quiescent HIGH (usually VCC) to below 0.3VCC. The SDA and SCL outputs have edge rate control circuits
included which make the fall time almost independent of load capacitance.
[3] The SDA or SCL LOWto HIGH propagation delay includes the rise time constant from the quiescent LOW to 0.5VCC for the EXPSDA1
or EXPSCL2, the rise time constant for the quiescent LOW to 0.5VCC for the EXPSDA1 or EXPSCL1, and the rise time constant from
the quiescent external driven LOWto 0.7VCCforthe SDAor SCL output.Allof these rise timesareRC time constants determinedbythe
external resistance and total capacitance for the various nodes.
Table 5. Dynamic characteristics
tPHL HIGH to LOW propagation delay SDA to SDAn, or
SCLto SCLn; Figure7
[1][2] 105 202 389 ns
tPLH LOW to HIGH propagation delay SDA to SDAn, or
SCLto SCLn; Figure7
[1][3] 110 259 265 ns
tPHL1 HIGH to LOW propagation delay 1 EXPSDA1 to SDA, or
EXPSCL1to SCL; Figure7
109 193 327 ns
tPLH1 LOW to HIGH propagation delay 1 EXPSDA1 to SDA, or
EXPSCL1to SCL; Figure7
130 153 179 ns
tPLH2 LOW to HIGH propagation delay 2 EXPSDA2 to SDA, or
EXPSCL2to SCL; Figure7
160 234 279 ns
tTHL HIGH to LOW output transition time SDA, SCL; Figure7 58 110 187 ns
tTLH LOW to HIGH output transition time SDA, SCL; Figure7 - 0.85 RC - ns
tsu set-up time enable to START condition 300 - - ns hold time enable after STOP condition 300 - - ns

Partno	Mfg	Dc	Qty	Available	Descript
PCA9518PW	NXP	N/a	83	avai	Expandable 5-channel I2C-bus hub