PCA9539BS-PCA9539D-PCA9539RPW Fast Delivery |IC PHOENIX CO.,LIMITED

PCA9539BS ,16-bit I虏C-bus and SMBus low power I/O port with interrupt and reset PCA9539; PCA9539R216-bit I C-bus and SMBus low power I/O port with interrupt and resetRev. 7 — 15 ..
PCA9539D ,PCA9539; 16-bit I²C and SMBus, low power I/O port with interrupt and resetapplications and was developed to enhance the NXP Semiconductors 2family of I C-bus I/O expanders. ..
PCA9539DBQR ,Remote 16-Bit I2C And SMBus, Low-Power I/O Expander With Interrupt Output, Reset & Config. Registers 24-SSOP -40 to 85Electrical Characteristics....... 6211.1 Trademarks..... 286.5 I C Interface Timing Requirements... ..
PCA9539PW ,16-bit I虏C-bus and SMBus low power I/O port with interrupt and resetFEATURESbits. The data for each Input or Output is kept in the corresponding2 Input or Output regis ..
PCA9539PWG4 ,Remote 16-Bit I2C And SMBus, Low-Power I/O Expander With Interrupt Output, Reset & Config. Registers 24-TSSOP -40 to 85Features 2 DescriptionThis 16-bit I/O expander for the two-line bidirectional1• Low Standby-Current ..
PCA9539PWR ,Remote 16-Bit I2C And SMBus, Low-Power I/O Expander With Interrupt Output, Reset & Config. Registers 24-TSSOP -40 to 85 SCPS130G–AUGUST 2005–REVISED JUNE 20144 Description (Continued)The system master can reset the PCA ..
PEMH11 ,R1 = 10 kOhm, R2 = 10 kOhmapplications1.4 Quick reference data Table 2. Quick reference dataSymbol Parameter Conditions Min T ..
PEMH13 ,R1 = 4.7 kOhm, R2 = 47 kOhmLIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 60134).SYMBOL PARAMETER C ..
PEMH14 ,NPN/NPN resistor-equipped transistors; R1 = 47 kOhm, R2 = openLimiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter C ..
PEMH14 ,NPN/NPN resistor-equipped transistors; R1 = 47 kOhm, R2 = openapplications1.4 Quick reference data Table 2. Quick reference dataSymbol Parameter Conditions Min T ..
PEMH16 ,NPN/NPN resistor-equipped transistors; R1 = 22 kOhm, R2 = 47 kOhmGeneral descriptionNPN/NPN Resistor-Equipped Transistors (RET). Table 1. Product overviewType numbe ..
PEMH19 ,NPN/NPN resistor-equipped transistors; R1 = 22 kOhm, R2 = openLimiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter C ..

PCA9539BS-PCA9539D-PCA9539RPW
16-bit I虏C-bus and SMBus low power I/O port with interrupt and reset
1. General description
The PCA9539; PCA9539R is a 24-pin CMOS device that provides 16 bits of General
Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for 2 C-bus/SMBus applications and was developed to enhance the NXP Semiconductors
family of I2 C-bus I/O expanders. I/O expanders provide a simple solution when additional
I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
The PCA9539; PCA9539R consists of two 8-bit configuration (input or output selection),
input, output and polarity inversion (active HIGH or active LOW operation) registers. The
system master can enable the I/Os as either inputs or outputs by writing to the I/O
configuration bits. The data for each input or output is kept in the corresponding Input or
Output register. The polarity of the read register can be inverted with the Polarity inversion
register. All registers can be read by the system master.
The PCA9539; PCA9539R is identical to the PCA9555 except for the removal of the
internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are
held LOW, replacement of A2 with RESET and a different address range.
The PCA9539; PCA9539R open-drain interrupt output is activated when any input state
differs from its corresponding input port register state and is used to indicate to the system
master that an input state has changed.
The power-on reset sets the registers to their default values and initializes the device state
machine. In the PCA9539, the RESET pin causes the same reset/default I/O input
configuration to occur without de-powering the device, holding the registers and I2 C-bus
state machine in their default state until the RESET input is once again HIGH. This input
requires a pull-up to VDD. In the PCA9539R however, only the device state machine is
initialized by the RESET pin and the internal general-purpose registers remain
unchanged. Using the PCA9539R RESET pin will only reset the I2 C-bus interface should
it be stuck LOW to regain access to the I2 C-bus. This allows the I/O pins to retain their last
configured state so that they can keep any lines in their previously defined state and not
cause system errors while the I2 C-bus is being restored.
Two hardware pins (A0, A1) vary the fixed I2 C-bus address and allow up to four devices to
share the same I2 C-bus/SMBus.
2. Features and benefits 16-bit I2 C-bus GPIO with interrupt and reset Operating power supply voltage range of 2.3 V to 5.5V
(5.0V10% for PCA9539PW/Q900 AEC-Q100 compliant devices)5 V tolerant I/Os
PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt
and reset
Rev. 7 — 15 April 2014 Product data sheet
NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset Polarity inversion register Active LOW interrupt output Active LOW reset input Low standby current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset 16 I/O pins which default to 16 inputs0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Offered in three different packages: SO24, TSSOP24, and HVQFN24
3. Ordering information
[1] PCA9539PW/Q900 is AEC-Q100 compliant. Contact I2C.support for PPAP.
3.1 Ordering options
Table 1. Ordering information
Table 2. Ordering options
NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
[1] Pin 1 in Quadrant 1; see Figure2.
[2] Pin 1 in Quadrant 2; see Figure3.
3.1.1 Pin 1 quadrant indication
Table 2. Ordering options …continued
NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
4. Block diagram
NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
5. Pinning information
5.1 Pinning
NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
5.2 Pin description
[1] HVQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
Table 3. Pin description
NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
6. Functional description
Refer to Figure 4 “Block diagram of PCA9539; PCA9539R”.
6.1 Device address
6.2 Registers
6.2.1 Command byte
The command byte is the first byte to follow the address byte during a write transmission.
It is used as a pointer to determine which of the following registers will be written or read.
Table 4. Command byte
NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
6.2.2 Registers 0 and 1: Input port registers
This register is an input-only port. It reflects the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by Register 3. Writes to
this register have no effect.
The default value ‘X’ is determined by the externally applied logic level.
6.2.3 Registers 2 and 3: Output port registers
This register is an output-only port. It reflects the outgoing logic levels of the pins defined
as outputs by Registers 6 and 7. Bit values in this register have no effect on pins defined
as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling
the output selection, not the actual pin value.
6.2.4 Registers 4 and 5: Polarity inversion registers
This register allows the user to invert the polarity of the Input port register data. If a bit in
this register is set (written with ‘1’), the Input port data polarity is inverted. If a bit in this
register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 5. Input port 0 register
Table 6. Input port 1 register
Table 7. Output port 0 register
Table 8. Output port 1 register
Table 9. Polarity inversion port 0 register
Table 10. Polarity inversion port 1 register
NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
6.2.5 Registers 6 and 7: Configuration registers
This register configures the directions of the I/O pins. If a bit in this register is set (written
with ‘1’), the corresponding port pin is enabled as an input with high-impedance output
driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is
enabled as an output. At reset, the device's ports are inputs.
6.3 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCA9539; PCA9539R
in a reset condition until VDD has reached VPOR. At that point, the reset condition is
released and the PCA9539; PCA9539R registers and SMBus state machine will initialize
to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device.
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
6.4 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). In
the PCA9539 the registers and SMBus/I2 C-bus state machine will be held in their default
state until the RESET input is once again HIGH. This input typically requires a pull-up to
VDD. In the PCA9539R, only the device state machine is initialized. The internal
general-purpose registers remain unchanged. Using the PCA9539R hardware reset pin
will only reset the I2 C-bus interface should it be stuck LOW to regain access to the 2 C-bus. This allows the I/O pins to retain their last configured state so that they can keep
any lines in their previously defined state and not cause system errors while the I2 C-bus is
being restored.
6.5 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5V.
If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of
the Output port register. Care should be exercised if an external voltage is applied to an
I/O configured as an output because of the low-impedance path that exists between the
pin and either VDD or VSS.
Table 11. Configuration port 0 register
Table 12. Configuration port 1 register
NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
6.6 Bus transactions
6.6.1 Writing to the port registers
Data is transmitted to the PCA9539; PCA9539R by sending the device address and
setting the least significant bit to a logic 0 (see Figure 8 “PCA9539; PCA9539R device
address”). The command byte is sent after the address and determines which register will
receive the data following the command byte.
The eight registers within the PCA9539; PCA9539R are configured to operate as four
register pairs. The four pairs are Input ports, Output ports, Polarity inversion ports, and
Configuration ports. After sending data to one register, the next data byte will be sent to
the other register in the pair (see Figure 10 and Figure 11). For example, if the first byte is
sent to Output port 1 (register 3), then the next byte will be stored in Output port0
(register 2). There is no limitation on the number of data bytes sent in one write
transmission. In this way, each 8-bit register may be updated independently of the other
registers.
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NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
6.6.2 Reading the port registers
In order to read data from the PCA9539; PCA9539R, the bus master must first send the
PCA9539; PCA9539R address with the least significant bit set to a logic 0 (see Figure 8
“PCA9539; PCA9539R device address”). The command byte is sent after the address and
determines which register will be accessed. After a restart, the device address is sent
again, but this time the least significant bit is set to a logic 1. Data from the register
defined by the command byte will then be sent by the PCA9539; PCA9539R (see
Figure 12, Figure 13 and Figure 14). Data is clocked into the register on the falling edge of
the acknowledge clock pulse. After the first byte is read, additional bytes may be read but
the data will now reflect the information in the other register in the pair. For example, if you
read Input port 1, then the next byte read would be Input port 0. There is no limitation on
the number of data bytes received in one read transmission but the final byte received, the
bus master must not acknowledge the data.
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NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
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NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
6.6.3 Interrupt output
The open-drain interrupt output is activated when one of the port pins changes state and
the pin is configured as an input. The interrupt is deactivated when the input returns to its
previous state or the Input port register is read (see Figure 13). A pin configured as an
output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt
caused by Port 0 will not be cleared by a read of Port 1 or the other way around.
Remark: Changing an I/O from an output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input port register.
7. Characteristics of the I2 C-bus
The I2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 15).
7.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 16).
NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
7.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 17).
7.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
8. Application design-in information
NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
8.1 Minimizing IDD when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD through a
resistor as shown in Figure 19. Since the LED acts as a diode, when the LED is off the I/O
VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower
than VDD.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the I/O pins greater than or equal to VDD when the LED is off.
Figure 20 shows a high value resistor in parallel with the LED. Figure 21 shows VDD less
than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI
at or above VDD and prevents additional supply current consumption when the LED is off.
9. Limiting values
Table 13. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
NXP Semiconductors PCA9539; PCA9539R
16-bit I2 C-bus and SMBus low power I/O port with interrupt and reset
10. Static characteristics
[1] VDD must be lowered to 0.2 V for at least 5 s in order to reset part.
[2] Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a
maximum current of 100 mA for a device total of 200 mA.
Table 14. Static characteristics for all devices except PCA9539PW/Q900
VDD= 2.3 V to 5.5 V; VSS =0V; Tamb= 40 C to +85 C; unless otherwise specified.

Partno	Mfg	Dc	Qty	Available	Descript
PCA9539BS	NXP	N/a	5490	avai	16-bit I虏C-bus and SMBus low power I/O port with interrupt and reset
PCA9539D	NXP	N/a	4	avai	PCA9539; 16-bit I²C and SMBus, low power I/O port with interrupt and reset
PCA9539RPW	NXP	N/a	163	avai	16-bit I虏C-bus and SMBus low power I/O port with interrupt and reset