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PCA9550D-PCA9550DP
2-bit I2C-bus LED driver with programmable blink rates
General descriptionThe PCA9550 LED blinker blinks LEDs in I2 C-bus and SMBus applications where it is
necessary to limit bus traffic or free up the I2 C master's (MCU, MPU, DSP, chip set, etc.)
timer. The uniquenessof this deviceis the internal oscillator with two programmable blink
rates. To blink LEDs using normal I/O expanders like the PCF8574 or PCA9554, the bus
master must send repeated commandsto turn the LEDon and off. This greatly increases
the amountof trafficon theI2 C-bus and usesup oneof the master's timers. The PCA9550
LED blinker instead requires only the initial set-up command to program BLINK RATE1
and BLINK RATE2 (i.e., the frequency and duty cycle). From then on, only one command
from the bus master is required to turn each individual open-drain output ON, OFF , or to
cycle at BLINK RATE 1 or BLINK RATE 2. Maximum output sink current is 25 mA per bit
and 50 mA per package.
Any bits not used for controlling the LEDs can be used for General Purpose parallel
Input/Output (GPIO) expansion.
The active LOW hardware reset pin (RESET) and Power-On Reset (POR) initializes the
registers to their default state, all zeroes, causing the bits to be set HIGH (LED off).
One hardware address pin on the PCA9550 allows two devices to operate on the same
bus.
Features 2 LED drivers (on, off, flashing at a programmable rate) 2 selectable, fully programmable blink rates (frequency and duty cycle) between
0.172 Hz and 44 Hz (5.82 seconds and 0.023 second) Input/output not used as LED drivers can be used as regular GPIOs Internal oscillator requires no external componentsI2 C-bus interface logic compatible with SMBus Internal power-on reset Noise filter on SCL/SDA inputs Active LOW reset input 2 open-drain outputs directly drive LEDs to 25 mA Controlled edge rates to minimize ground bounce No glitch on power-up Supports hot insertion Low standby current Operating power supply voltage range of 2.3 V to 5.5V0 kHz to 400 kHz clock frequency
PCA9550
2-bit I2 C-bus LED driver with programmable blink rates
Rev. 05 — 13 October 2008 Product data sheet
NXP Semiconductors PCA9550
2-bit I2 C-bus LED driver with programmable blink rates ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8, TSSOP8 (MSOP8), HVSON8
Ordering information[1] Also known as MSOP8.
3.1 Ordering options Block diagram
Table 1. Ordering informationPCA9550D SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PCA9550DP TSSOP8[1] plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
PCA9550TK HVSON8 plastic thermal enhanced very thin small outline package;no leads;8 terminals;
body 3×3× 0.85 mm
SOT908-1
Table 2. Ordering optionsPCA9550D PCA9550 Tamb = −40 °C to +85°C
PCA9550DP 9550 Tamb = −40 °C to +85°C
PCA9550TK 9550 Tamb = −40 °C to +85°C
NXP Semiconductors PCA9550
2-bit I2 C-bus LED driver with programmable blink rates Pinning information
5.1 Pinning
5.2 Pin description
Table 3. Pin description 1 address input 0
LED0 2 LED driver 0
LED1 3 LED driver 1
VSS 4 supply ground
RESET 5 active LOW reset input
SCL 6 serial clock line
SDA 7 serial data line
VDD 8 supply voltage
NXP Semiconductors PCA9550
2-bit I2 C-bus LED driver with programmable blink rates Functional descriptionRefer to Figure 1 “Block diagram of PCA9550”.
6.1 Device addressFollowing a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9550 is shown in Figure 5. To conserve power, no
internal pull-up resistoris incorporatedon the hardware selectable address pin andit must
be pulled HIGH or LOW.
The lastbitof the address byte defines the operationtobe performed. When setto logic1
a read is selected, while a logic 0 selects a write operation.
6.2 Control registerFollowing the successful acknowledgementof the slave address, the bus master will send
a byte to the PCA9550, which will be stored in the Control register.
The lowest 3 bits are used as a pointer to determine which register will be accessed.
If the Auto-Increment (AI) flag is set, the three low order bits of the Control register are
automatically incremented after a read or write. This allows the user to program the
registers sequentially. The contentsof these bits will rolloverto ‘000’ after the last register
is accessed.
When the Auto-Increment flag is set (AI= 1) and a read sequence is initiated, the
sequence must start by reading a register different from the input register
(B2 B1 B0≠ 000).
Only the 3 least significant bits are affected by the AI flag. Unused bits must be
programmed with zeroes.
NXP Semiconductors PCA9550
2-bit I2 C-bus LED driver with programmable blink rates
6.2.1 Control register definition
6.3 Register descriptions
6.3.1 INPUT - Input registerThe INPUT register reflects the state of the device pins. Writes to this register will be
acknowledged but will have no effect.
Remark: The default value‘X’is determinedby the externally applied logic level (normally
logic 1) when used for directly driving LED with pull-up to VDD.
6.3.2 PSC0 - Frequency Prescaler0PSC0 is used to program the period of the PWM output.
The period of BLINK0= (PSC0+1)/ 44.
6.3.3 PWM0 - Pulse Width Modulation0The PWM0 register determines the duty cycleof BLINK0. The outputs are LOW (LED off)
when the count is less than the value in PWM0 and HIGH when it is greater. If PWM0 is
programmed with 00h, then the PWM0 output is always LOW.
The duty cycle of BLINK0= (256− PWM0)/ 256.
Table 4. Register summary 0 0 INPUT read only input register 0 1 PSC0 read/write frequency prescaler 0 1 0 PWM0 read/write PWM register 0 1 1 PSC1 read/write frequency prescaler 1 0 0 PWM1 read/write PWM register 1 0 1 LS0 read/write LED selector
Table 5. INPUT - Input register description
Table 6. PSC0 - Frequency Prescaler 0 register description
Table 7. PWM0 - Pulse Width Modulation 0 register description
NXP Semiconductors PCA9550
2-bit I2 C-bus LED driver with programmable blink rates
6.3.4 PSC1 - Frequency Prescaler1PSC1 is used to program the period of the PWM output.
The period of BLINK1= (PSC1+1)/ 44.
6.3.5 PWM1 - Pulse Width Modulation1The PWM1 register determines the duty cycleof BLINK1. The outputs are LOW (LED off)
when the count is less than the value in PWM1 and HIGH when it is greater. If PWM1 is
programmed with 00h, then the PWM1 output is always LOW.
The duty cycle of BLINK1= (256− PWM1)/ 256.
6.3.6 LS0 - LED selectorThe LS0 LED select register determines the source of the LED data.= output is set LOW (LED on)= output is set high-impedance (LED off; default)= output blinks at PWM0 rate= output blinks at PWM1 rate
Table 8. PSC1 - Frequency Prescaler 1 register description
Table 9. PWM1 - Pulse Width Modulation 1 register description
Table 10. LS0 - LED selector register description
NXP Semiconductors PCA9550
2-bit I2 C-bus LED driver with programmable blink rates
6.4 Pins used as GPIOsLED pins not used to control LEDs can be used as General Purpose Input/Outputs
(GPIOs).
For use as input, set LEDn to high-impedance (01) and then read the pin state via the
Input register.
For use as output, connect external pull-up resistor to the pin and size it according to the
DC recommended operating characteristics. LEDn output pin is HIGH when the output is
programmedas high-impedance, and LOW when the outputis programmed LOW through
the LED selector register (LS0). The output canbe pulse-width controlled when PWM0or
PWM1 are used.
6.5 Power-on resetWhen power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9550 in reset condition until VDD has reached VPOR.At that point, the reset conditionis released
and the PCA9550 registers are initialized to their default states, all the outputs in the
OFF state. Thereafter, VDD must be lowered below 0.2 V to reset the device.
6.6 External RESET reset canbe accomplishedby holding the RESET pin LOWfora minimumof tw(rst). The
PCA9550 registers and I2 C-bus state machine will be held in their default states until the
RESET input is once again HIGH.
This input requires a pull-up resistor to VDD if no active connection is used.
NXP Semiconductors PCA9550
2-bit I2 C-bus LED driver with programmable blink rates Characteristics of the I2 C-busTheI2 C-busisfor 2-way, 2-line communication between different ICsor modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transferOne databitis transferred during each clock pulse. The dataon the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure7).
7.1.1 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). LOW-to-HIGH transitionof the data line while the clockis HIGHis definedas the STOP
condition (P) (see Figure 8).
7.2 System configurationA device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 9).
NXP Semiconductors PCA9550
2-bit I2 C-bus LED driver with programmable blink rates
7.3 AcknowledgeThe number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse. slave receiver whichis addressed must generatean acknowledge after the receptionof
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse,so that the SDA lineis stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
NXP Semiconductors PCA9550
2-bit I2 C-bus LED driver with programmable blink rates
7.4 Bus transactions
NXP Semiconductors PCA9550
2-bit I2 C-bus LED driver with programmable blink rates Application design-in information
8.1 Minimizing IDD when the I/Os are used to control LEDsWhen the I/Os are used to control LEDs, they are normally connected to VDD through a
resistor as shown in Figure 14. Since the LED acts as a diode, when the LED is off the
I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes
lower than VDD.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the I/O pins greater thanor equalto VDD when the LEDis off.
Figure 15 shows a high value resistor in parallel with the LED. Figure 16 shows VDD less
than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/OVI
at or above VDD and prevents additional supply current consumption when the LED is off.
NXP Semiconductors PCA9550
2-bit I2 C-bus LED driver with programmable blink rates
8.2 Programming exampleThe following example will show how to set LED0 to blink at 1 Hz at a 50 % duty cycle.
LED1 will be set to blink at 4 Hz and at a 25 % duty cycle.
Limiting values
Table 11. Programming PCA9550START S
PCA9550 address with A0= LOW C0h
PSC0 subaddress + Auto-Increment 11h
Set prescaler PSC0 to achieve a period of 1 second:
PSC0=43
2Bh
Set PWM0 duty cycle to 50%:
PWM0= 128
80h
Set prescaler PSC1 to achieve a period of 0.25 seconds:
PSC1=10
0Ah
Set PWM1 output duty cycle to 25%:
PWM1= 192
C0h
Set LED0 to PWM0, and set LED1 to blink at PWM1 0Eh
STOP P
Blink period 1 PSC0 1+------------------------==
256 PWM0–
256 -------------------------------- 0.5=
Blink period 0.25 PSC11+------------------------==
256 PWM1–
256 -------------------------------- 0.25=
Table 12. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage −0.5 +6.0 V
VI/O voltage on an input/output pin VSS− 0.5 5.5 V
IO(LEDn) output current on pin LEDn - ±25 mA
ISS ground supply current - 50 mA
Ptot total power dissipation - 400 mW
Tstg storage temperature −65 +150 °C
Tamb ambient temperature operating −40 +85 °C
NXP Semiconductors PCA9550
2-bit I2 C-bus LED driver with programmable blink rates
10. Static characteristics[1] Typical limits at VDD=3.3 V, Tamb =25°C.
[2] VDD must be lowered to 0.2 V in order to reset part.
[3] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 50 mA.
Table 13. Static characteristicsVDD= 2.3 V to 5.5 V; VSS =0V; Tamb= −40 °C to +85 °C; unless otherwise specified.
SuppliesVDD supply voltage 2.3 - 5.5 V
IDD supply current operating mode; VDD= 5.5 V; no load; =VDD or VSS; fSCL= 100 kHz 350 500 μA
Istb standby current Standby mode; VDD= 5.5 V; no load; =VDDor VSS; fSCL=0 kHz 1.9 3.0 μA
VPOR power-on reset voltage no load; VI =VDD or VSS [2] 1.4 1.7 2.2 V
Input SCL; input/output SDAVIL LOW-level input voltage −0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - 5.5 V
IOL LOW-level output current VOL= 0.4V 3 6.5 - mA leakage current VI =VDD =VSS −1- +1 μA input capacitance VI =VSS - 3.7 5 pF
I/OsVIL LOW-level input voltage −0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
IOL LOW-level output current VOL= 0.4V
VDD= 2.3V [3] 69 - mA
VDD= 3.0V [3] 811 - mA
VDD= 5.0V [3] 10 14 - mA
VOL= 0.7V
VDD= 2.3V [3] 11 14 - mA
VDD= 3.0V [3] 14 18 - mA
VDD= 5.0V [3] 17 24 - mA
ILI input leakage current VDD= 3.6 V; VI=0 V or VDD −1- +1 μA
Cio input/output capacitance - 2.1 5 pF
Select inputs A0; RESETVIL LOW-level input voltage −0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
ILI input leakage current −1- +1 μA input capacitance VI =VSS - 2.3 5 pF
