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PCA9554ABS-PCA9554AD-PCA9554ADB-PCA9554APW-PCA9554BS-PCA9554D-PCA9554DB-PCA9554PW
8-bit I2C and SMBus I/O port with interrupt
Product data sheet
Supersedes data of 2002 Jul 26
2004 Sep 30
Philips Semiconductors Product data sheet
PCA9554/PCA9554A8-bit I2 C and SMBus I/O port with interrupt
FEATURES Operating power supply voltage range of 2.3 to 5.5 V 5 V tolerant I/Os Polarity inversion register Active-LOW interrupt output Low stand-by current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset 8 I/O pins which default to 8 inputs 0 to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA Six packages offered: DIP16, SO16, SSOP16, SSOP20,
TSSOP16, and HVQFN16
DESCRIPTIONThe PCA9554 and PCA9554A are 16-pin CMOS devices that
provide 8 bits of General Purpose parallel Input/Output (GPIO)
expansion for I2 C/SMBus applications and were developed to
enhance the Philips family of I�C I/O expanders. The improvements
include higher drive capability, 5V I/O tolerance, lower supply
current, individual I/O configuration, 400 kHz clock frequency, and
smaller packaging. I/O expanders provide a simple solution when
additional I/O is needed for ACPI power switches, sensors,
pushbuttons, LEDs, fans, etc.
The PCA9554/54A consist of an 8-bit Configuration register (Input or
Output selection); 8-bit Input register, 8-bit Output register and an
8-bit Polarity inversion register (Active-HIGH or Active-LOW
operation). The system master can enable the I/Os as either inputs
or outputs by writing to the I/O configuration bits. The data for each
Input or Output is kept in the corresponding Input or Output register.
The polarity of the read register can be inverted with the Polarity
Inversion Register. All registers can be read by the system master.
Although pin to pin and I2 C address compatible with the PCF8574
series, software changes are required due to the enhancements and
are discussed in Application Note AN469.
The PCA9554/54A open-drain interrupt output is activated when any
input state differs from its corresponding input port register state and
is used to indicate to the system master that an input state has
changed. The power-on reset sets the registers to their default
values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I2C address and
allow up to eight devices to share the same I2C/SMBus. The
PCA9554A is identical to the PCA9554 except that the fixed I2C
address is different allowing up to sixteen of these devices (eight of
each) on the same I2C/SMBus.
ORDERING INFORMATIONStandard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
I2C is a trademark of Philips Semiconductors Corporation.
SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent.
Philips Semiconductors Product data sheet
PCA9554/PCA9554A8-bit I2 C and SMBus I/O port with interrupt
PIN CONFIGURATION — 16-pin DIP, SO, SSOP,
TSSOP
Figure 1. Pin configuration — 16-pin DIP, SO, SSOP, TSSOP
PIN CONFIGURATION — 20-pin SSOP
Figure 1. Pin configuration — 20-pin SSOP
PIN CONFIGURATION — HVQFN
Figure 2. Pin Configuration — HVQFN
PIN DESCRIPTION
Philips Semiconductors Product data sheet
PCA9554/PCA9554A8-bit I2 C and SMBus I/O port with interrupt
BLOCK DIAGRAM
Figure 3. Block diagram
Philips Semiconductors Product data sheet
PCA9554/PCA9554A8-bit I2 C and SMBus I/O port with interrupt
REGISTERS
Command ByteThe command byte is the first byte to follow the address byte during
a write transmission. It is used as a pointer to determine which of the
following registers will be written or read.
Register 0 – Input Port RegisterThis register is a read only port. It reflects the incoming logic levels
of the pins, regardless of whether the pin is defined as an input or an
output by Register 3. Writes to this register have no effect.
The default value ‘X’ is determined by the externally applied logic
level, normally ‘1’ when no external signal externally applied
because of the internal pull-up resistors.
Register 1 – Output Port RegisterThis register reflects the outgoing logic levels of the pins defined as
outputs by Register 3. Bit values in this register have no effect on
pins defined as inputs. Reads from this register return the value that
is in the flip-flop controlling the output selection, NOT the actual pin
value.
Register 2 – Polarity Inversion RegisterThis register allows the user to invert the polarity of the Input Port
Register data. If a bit in this register is set (written with ‘1’), the
corresponding Input Port data is inverted. If a bit in this register is
cleared (written with a ‘0’), the Input Port data polarity is retained.
Register 3 – Configuration RegisterThis register configures the directions of the I/O pins. If a bit in this
register is set, the corresponding port pin is enabled as an input with
high-impedance output driver. If a bit in this register is cleared, the
corresponding port pin is enabled as an output. At reset, the I/Os are
configured as inputs with a weak pull-up to VDD.
Power-on ResetWhen power is applied to VDD, an internal power-on reset holds the
PCA9554 in a reset condition until VDD has reached VPOR. At that
point, the reset condition is released and the PCA9554 registers and
state machine will initialize to their default states. Thereafter, VDD
must be lowered below 0.2 V to reset the device.
For a power reset cycle, VDD must be lowered below 0.2 V and then
restored to the operating voltage.
Interrupt OutputThe open-drain interrupt output is activated when one of the port
pins change state and the pin is configured as an input. The
interrupt is deactivated when the input returns to its previous state or
the input port register is read.
Note that changing an I/O from an output to an input may cause a
false interrupt to occur if the state of the pin does not match the
contents of the input port register.
Philips Semiconductors Product data sheet
PCA9554/PCA9554A8-bit I2 C and SMBus I/O port with interrupt
SIMPLIFIED SCHEMATIC OF I/O0 TO I/O7
NOTE: At Power-on Reset, all registers return to default values.
Figure 4. Simplified schematic of I/O0 to I/O7
I/O portWhen an I/O is configured as an input, FETs Q1 and Q2 are off,
creating a high-impedance input with a weak pull-up (100 kΩ typ.) to
VDD. The input voltage may be raised above VDD to a maximum of
5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled,
depending on the state of the output port register. Care should be
exercised if an external voltage is applied to an I/O configured as an
output because of the low impedance paths that exist between the
pin and either VDD or VSS.
Philips Semiconductors Product data sheet
PCA9554/PCA9554A8-bit I2 C and SMBus I/O port with interrupt
Device address
Figure 5. PCA9554 address
Figure 6. PCA9554A address
Bus transactionsData is transmitted to the PCA9554/PCA9554A registers using the write mode as shown in Figures 7 and 8. Data is read from the
PCA9554/PCA9554A registers using the read mode as shown in Figures 9 and 10. These devices do not implement an auto-increment function
so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte
has been sent.
Figure 7. WRITE to output port register
Figure 8. WRITE to configuration or polarity inversion registers
Philips Semiconductors Product data sheet
PCA9554/PCA9554A8-bit I2 C and SMBus I/O port with interrupt
Figure 9. READ from register
NOTES: This figure assumes the command byte has previously been programmed with 00h. Transfer of data can be stopped at any moment by a stop condition.
Figure 10. READ input port register
Philips Semiconductors Product data sheet
PCA9554/PCA9554A8-bit I2 C and SMBus I/O port with interrupt
TYPICAL APPLICATION
Figure 11. Typcial application.
Philips Semiconductors Product data sheet
PCA9554/PCA9554A8-bit I2 C and SMBus I/O port with interrupt
ABSOLUTE MAXIMUM RATINGSIn accordance with the Absolute Maximum Rating System (IEC 134)
