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PCA9560PW
PCA9560; Dual 5-bit multiplexed 1-bit latched I²C EEPROM DIP switch
Product data sheet
Supersedes data of 2003 Jun 27
2004 May 19
Philips Semiconductors Product data sheet
PCA9560Dual 5-bit multiplexed 1-bit latched 2 C EEPROM DIP switch
FEATURES 5-bit 3-to-1 multiplexer, 1-bit latch DIP switch• 5-bit external hardware pins Two 6-bit internal non-volatile registers, fully pin-to-pin compatible
with PCA9559• Selection between the two non-volatile registers Selection between non-volatile registers and external hardware
pins•I2 C/SMBus interface logic• Internal pull-up resistors on input pin and control signals Active high write protect on input controls the ability to write to the
non-volatile registers• 2 address pins, allowing up to 4 devices on the I2C-bus 5 open drain multiplexed outputs Open drain non-multiplexed output• Internal 6-bit non-volatile registers programmable and readable via2 C-bus• External hardware 5-bit value readable via I2C-bus Multiplexer selection can be overridden by I2 C-bus Operating power supply voltage 3.0 V to 3.6 V• 5 V and 2.5 V tolerant inputs/outputs 0 to 400 kHz clock frequency• ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V
MM per JESD22-A115, and 1000 V CDM per JESD22-C101• Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA.• Package offering: SO20, TSSOP20
DESCRIPTIONThe PCA9560 is a 20-pin CMOS device consisting of two 6-bit
non-volatile EEPROM registers, 5 hardware pin inputs and a 5-bit
multiplexed output with one latched EEPROM bit. It is used for DIP
switch-free or jumper-less system configuration and supports Mobile
and Desktop VID Configuration, where 3 preset values (2 sets of
internal non-volatile registers and 1 set of external hardware pins)
set processor voltage for operation in either performance, deep
sleep or deeper sleep modes. The PCA9560 is also useful in server
and telecom/networking applications when used to replace DIP
switches or jumpers, since the settings can be easily changed via2 C/SMBus without having to power down the equipment to open the
cabinet. The non-volatile memory retains the most current setting
selected before the power is turned off.
The PCA9560 typically resides between the CPU and Voltage
Regulator Module (VRM) when used for CPU VID (Voltage
IDentification code) configuration. It is used to bypass the
CPU-defined VID values and provide a different set of VID values to
the VRM, if an increase in the CPU voltage is desired. An increase
in CPU voltage combined with an increase in CPU frequency leads
to a performance boost of up to 7.5%. Lower CPU voltage reduces
power consumption. The main advantage of the PCA9560 over the
older PCA9559 device in this application is that it contains two
internal non-volatile EEPROM registers instead of just one, allowing
three independent settings (performance operation, deep sleep
mode and deeper sleep mode) instead of only two (performance
operation and deep sleep mode). The PCA9560 is footprint
compatible and a drop-in replacement for the PCA9559, without any
software modifications required.
The PCA9560 has 2 address pins allow up to 4 devices to be placed
on the same I2C bus or SMBus.
PIN CONFIGURATION
Figure 1. Pin configuration
PIN DESCRIPTION
ORDERING INFORMATION
Philips Semiconductors Product data sheet
PCA9560Dual 5-bit multiplexed 1-bit latched 2 C EEPROM DIP switch
BLOCK DIAGRAM
Philips Semiconductors Product data sheet
PCA9560Dual 5-bit multiplexed 1-bit latched 2 C EEPROM DIP switch
DEVICE ADDRESSFollowing a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9560 is
shown in Figure 3. To conserve power, no internal pull-up resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
The last bit of the slave address byte defines the operation to be
performed. When set to logic 1 a read is selected while a logic 0
selects a write operation.
Figure 3. Slave address
CONTROL REGISTERFollowing the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9560, which will be stored
in the control register. This register can be written and read via the2 C-bus.
Figure 4. Control Register
CONTROL REGISTER DEFINITIONFollowing the address and acknowledge bit with logic 0 in the read/write bit, the first byte written is the command byte. If the command byte is
reserved and therefore not valid, it will not be acknowledged. Only valid command bytes will be acknowledged.
Table 1. Register Addresses
Table 2. Commands
NOTE: All other combinations are reserved. MUX_SELECT pins select between MUX_IN and EEPROM to MUX_OUT.
Philips Semiconductors Product data sheet
PCA9560Dual 5-bit multiplexed 1-bit latched 2 C EEPROM DIP switch
REGISTER DESCRIPTIONIf the command byte is an EEPROM address, the next byte sent will be programmed into that EEPROM address on the following STOP
condition, if the WP is logic 0. If more than one byte is sent sequentially, the second byte will be written in the other-volatile register, on the
following STOP condition. If any more data bytes are sent after the second byte, they will not be acknowledged and no bytes will be written to
the non-volatile registers. After a byte is read from or written to the EEPROM, the part automatically points to the next non-volatile register. If the
command code was FFH, the MUX_IN values are sent with the three MSBs padded with zeroes as shown below. If the command codes was
00H, then the non-volatile register 1 is sent, and if the command code was 01H, then the non-volatile register 1 is sent.
EEPROM Byte 0 Register
EEPROM Byte 1 Register
MUX_IN RegisterIf the command byte is a MUX command byte, any additional data bytes sent after the MUX command code will not be acknowledged. If the
read/write bit in the address is a logic 1, then a read operation follows and the data sent out depends on the previously stored command code.
The MUX_SELECT_1 pin can function as the over-ride pin as on the PCA9559 if the non-volatile register 1 is left at all 0s.
The NON_MUXED_OUT pin is a latched output. It is latched when MUX_SELECT_0 = 1. It is transparent when the MUX_SELECT_0 = 0. The
data sent out on the NON_MUXED_OUT output is the 6th most significant bit of the non-volatile register. Whether this comes from the
non-volatile register 0 or non-volatile register 1 depends on the command code or the external mux-select pins.
After a valid I2C write operation to the EEPROM, the part cannot be addressed via the I2C for 3.6 ms. If the part is addressed prior to this time,
the part will not acknowledge its address.
NOTE: To ensure data integrity, the non-volatile register must be internally write protected when VDD to the I2C bus is powered down or VDD to the
component is dropped below normal operating levels.
Philips Semiconductors Product data sheet
PCA9560Dual 5-bit multiplexed 1-bit latched 2 C EEPROM DIP switch
CONVERSION FROM THE PCA9559 TO THE PCA9560The PCA9560 is a drop in replacement to the PCA9559 with no software modifications. The PCA9559 has only one MUX_SELECT pin to
choose between the MUX_IN values and the single non-volatile register. Since the PCA9560 has two internal non-volatile registers, if Register 1
is left to all 0’s (default condition) then the MUX_SELECT_1 pin can function the same as the PCA9559 OVERRIDE # pin and MUX_SELECT_0
pin can function the same as the PCA9559 MUX_IN pin.
The PCA9560 can read the MUX_IN_X values via I2C that the PACA9559 cannot do. Another difference is that the MUX_SELECT_X control
pins can be overridden by I2C. To replace the PCA9559 with the PCA9560, the function table for the MUX_OUT outputs and the
NON_MUXED_OUT output must stay the same and the MUX_SELECT pin functions should not be overridden by I2C.
EXTERNAL CONTROL SIGNALSThe Write Protect (WP) input is used to control the ability to write the content of the non-volatile registers. If the WP signal is logic 0, the I2 C bus
will be able to write the contents of the non-volatile registers. If the WP signal is logic 1, data will not be allowed to be written into the
non-volatile registers. In this case, the slave address and the command code will be acknowledged but the following data bytes will not be
acknowledged and the EEPROM is not updated.
The factory default for the contents of the non-volatile register are all logic 0. These stored values can be read or written using the I2C-bus
(described in the next section).
The WP, MUX_IN*, MUX_SELECT_0, and MUX_SELECT_1 signals have internal pull-up resistors. See the DC and AC Characteristics for
hysteresis and signal spike suppression figures.
Function Table1
NOTE: This table is valid when not overridden by I2C control register.
POWER-ON RESET (POR)When power is applied to VDD, an internal power-on reset holds the PCA9560 in a reset state until VDD has reached VPOR. At that point, the
reset condition is released and the PCA9560 volatile registers and I2C/SMBus state machine will initialize to their default states.
The MUX_OUT and NON_MUXED_OUT pin values depend on:
the MUX_SELECT_0 and MUX_SELECT_1 logic levels, selecting either the MUX_IN input pins or one of the two 6-bit EEPROMs
the previously stored values in the EEPROM registers/current MUX_IN pin values as shown in the Function Table
Philips Semiconductors Product data sheet
PCA9560Dual 5-bit multiplexed 1-bit latched 2 C EEPROM DIP switch
CHARACTERISTICS OF THE I2 C-BUSThe I2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line
(SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may
be initiated only when the bus is not busy.
Bit transferOne data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as
changes in the data line at this time will be interpreted as control signals (see Figure 5).
Figure 5. Bit transfer
Start and stop conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined
as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 6).
System configurationA device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device initiates a transfer is the ‘master’ and the
devices which are controlled by the master are the ‘slaves’ (see Figure 7).
Figure 6. Definition of start and stop conditions
Figure 7. System configuration
Philips Semiconductors Product data sheet
PCA9560Dual 5-bit multiplexed 1-bit latched 2 C EEPROM DIP switch
AcknowledgeThe number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH-level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the
slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
Figure 8. Acknowledgement on the I2C-bus
Philips Semiconductors Product data sheet
PCA9560Dual 5-bit multiplexed 1-bit latched 2 C EEPROM DIP switch
Bus TransactionsData is transmitted to the PCA9560 registers using Write Byte transfers (see Figures 9 and 10). Data is read from the PCA9560 registers using
Read and Receive Byte transfers (see Figure 11).
Figure 9. WRITE on 1 EEPROM — assuming WP = 0
Figure 10. WRITE on 2 EEPROMs — assuming WP = 0
Figure 11. READ MUX_IN register
