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PCA9632TK-PCA9632TK2
4-bit Fm+ I2C-bus low power LED driver
1. General descriptionThe PCA9632 is an I2 C-bus controlled 4-bit LED driver optimized for
Red/Green/Blue/Amber (RGBA) color mixing applications. The PCA9632 is a drop-in
upgrade for the PCA9633 with 40 power reduction. In Individual brightness control mode,
each LED output has its own 8-bit resolution (256 steps) fixed frequency Individual PWM
controller that operates at 1.5625 kHz with a duty cycle that is adjustable from 0 % to
99.6 % to allow the LED to be set to a specific brightness value. In group dimming mode,
each LED output has its own 6-bit resolution (64 steps) fixed frequency Individual PWM
controller that operates at 6.25 kHz with a duty cycle that is adjustable from 0 % to 98.4 %
to allow the LED to be set to a specific brightness value. A fifth 4-bit resolution (16 steps)
Group PWM controller has a fixed frequency of 190 Hz that is used to dim all the LEDs
with the same value.
While operating in the Blink mode, each LED output has its own 8-bit resolution
(256 steps) fixed frequency Individual PWM controller that operates at 1.5625 kHz with a
duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set to a specific
brightness value. Blink rate is controlled by the Group frequency setting that has 8-bit
resolution (256 steps). The blink rate is adjustable between 24 Hz and once every
10.73 seconds. For Group frequency settings between 6 Hz and 24 Hz, the Group PWM
has a 6-bit resolution (64 steps) with a duty cycle that is adjustable from 0%to 98.4 %.
For Group frequency settings between 6 Hz and 0.09 Hz (once in 10.73 seconds), the
Group PWM has an 8-bit resolution (256 steps) with a duty cycle that is adjustable from % to 99.6 %.
Each LED output can be off, on (no PWM control), set at its Individual PWM controller
value or at both Individual and Group PWM controller values. The LED output driver is
programmed to be either open-drain with a 25 mA current sink capability at 5 V or
totem pole with a 25 mA sink, 10 mA source capability at 5 V. The PCA9632 operates with
a supply voltage range of 2.3 V to 5.5 V and the outputs are 5.5 V tolerant. LEDs can be
directly connected to the LED output (up to 25 mA, 5.5 V) or controlled with external
drivers and a minimum amount of discrete components for larger current or higher voltage
LEDs.
The PCA9632 is in the new Fast-mode Plus (Fm+) family. Fm+ devices offer higher
frequency (up to 1 MHz) and more densely populated bus operation (up to 4000 pF).
Software programmable LED Group and three Sub Call I2 C-bus addresses allow all or
defined groups of PCA9632 devices to respond to a common I2 C-bus address, allowing
for example, all red LEDs to be turned on or off at the same time or marquee chasing
effect, thus minimizing I2 C-bus commands.
PCA9632
4-bit Fm+ I2 C-bus low power LED driver
Rev. 5 — 27 July 2011 Product data sheet
NXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driverThe Software Reset (SWRST) Call allows the master to perform a reset of the PCA9632
through the I2 C-bus, identical to the Power-On Reset (POR) that initializes the registers to
their default state causing the outputs to be set high-impedance. This allows an easy and
quick way to reconfigure all device registers to the same condition.
2. Features and benefits 40 power reduction compared to PCA9633 4 LED drivers. Each output programmable at: Off On Programmable LED brightness Programmable group dimming/blinking mixed with individual LED brightness1 MHz Fast-mode Plus I2 C-bus interface with 30 mA high drive capability on SDA
output for driving high capacitive buses 256-step (8-bit) linear programmable brightness per LED output varying from fully off
(default) to maximum brightness using a 1.5625 kHz PWM signal in Individual
brightness mode 64-step (6-bit) linear programmable brightness for each LED output varying from fully
off (default) to maximum brightness using a 6.25 kHz PWM signal in group dimming
mode In group dimming mode, 16-step group brightness control allows global dimming
(using a 190 Hz PWM signal) from fully off to maximum brightness (default) 256-step (8-bit) linear programmable brightness per LED output varying from fully off
(default) to maximum brightness using a 1.5625 kHz PWM signal in group blinking
mode 64-step group blinking with frequency programmable from 24 Hz to 6 Hz and
duty cycle from 0 % to 98.4% 256-step group blinking with frequency programmable from 6 Hz to 0.09 Hz (10.73s)
and duty cycle from 0 % to 99.6% Four totem pole outputs (sink 25 mA and source 10 mA at 5 V) with software
programmable open-drain LED outputs selection (default at high-impedance). No input
function. 10-pin package option provides two hardware address pins allowing four devices to
operate on the same bus Output state change programmable on the Acknowledge or the STOP Command to
update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’). Software Reset feature (SWRST Call) allows the device to be reset through the 2 C-bus 400 kHz internal oscillator requires no external components Internal power-on reset Noise filter on SDA/SCL inputs Edge rate control on outputs No glitch on power-up Supports hot insertion Low standby current of <1 A Operating power supply voltage range of 2.3 V to 5.5V
NXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driver 5.5 V tolerant inputs 40 C to +85 C operation ESD protection exceeds 5000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: TSSOP8, TSSOP10, HVSON8, HVSON10
3. Applications RGB or RGBA LED drivers for color mixing LED status information LED displays LCD backlights Keypad backlights for cellular phones or handheld devices
4. Ordering informationTable 1. Ordering informationPCA9632DP1 9632 TSSOP8 plastic thin shrink small outline package; 8 leads; body width3 mm SOT505-1
PCA9632DP2 9632 TSSOP10 plastic thin shrink small outline package; 10 leads;
body width3 mm
SOT552-1
PCA9632TK 9632 HVSON8 plastic thermal enhanced very thin small outline package; leads; 8 terminals; body 33 0.85 mm
SOT908-1
PCA9632TK2 9632 HVSON10 plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body 33 0.85 mm SOT650-1
NXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driver
5. Block diagramNXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driver
6. Pinning information
6.1 Pinning
6.2 Pin description[1] HVSON8 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
Table 2. Pin description for TSSOP8 and HVSON8LED0 1 O LED driver 0
LED1 2 O LED driver 1
LED2 3 O LED driver 2
LED3 4 O LED driver 3
VSS 5[1] power supply supply ground
SCL 6 I serial clock line
SDA 7 I/O serial data line
VDD 8 power supply supply voltage
NXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driver[1] HVSON10 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
7. Functional descriptionRefer to Figure 1 “Block diagram of PCA9632”.
7.1 Device addressesFollowing a START condition, the bus master must output the address of the slave it is
accessing.
There are a maximum of 4 possible programmable addresses using the 2 hardware
address pins for the 10-pin version and just one fixed address for the 8-pin version.
7.1.1 Regular I2 C-bus slave addressThe I2 C-bus slave address of the PCA9632 is shown in Figure 6. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW (10-pin versions only).
Remark: Using reserved I2 C-bus addresses will interfere with other devices, but only if
the devices are on the bus and/or the bus will be open to other I2 C-bus systems at some
later date. In a closed system where the designer controls the address assignment these
addresses can be used since the PCA9632 treats them like any other address. The
LEDAll Call, Software Reset and PCA9564 or PCA9665 slave address (if on the bus) can
never be used for individual device addresses.
PCA9632 LED All Call address (1110 000) or Software Reset (0000 0110) which are
active on start-up
PCA9564 (0000 000) or PCA9665 (1110 000) slave address which is active on
start-up
‘reserved for future use’ I2 C-bus addresses (0000 011, 1111 1XX)
slave devices that use the 10-bit addressing scheme (1111 0XX)
Table 3. Pin description for TSSOP10 and HVSON10LED0 1 O LED driver 0
LED1 2 O LED driver 1
LED2 3 O LED driver 2
LED3 4 O LED driver 3 5 I address input 0
VSS 6[1] power supply supply ground 7 I address input 1
SCL 8 I serial clock line
SDA 9 I/O serial data line
VDD 10 power supply supply voltage
NXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driver slave devices that are designed to respond to the General Call address (0000 000)
High-speed mode (Hs-mode) master code (0000 1XX)
The last bit of the address byte defines the operation to be performed. When set to logic1
a read is selected, while a logic 0 selects a write operation.
7.1.2 LED All Call I2 C-bus address Default power-up value (ALLCALLADR register): E0h or 1110 000
Programmable through I2 C-bus (volatile programming)
At power-up, LED All Call I2 C-bus address is enabled. PCA9632 sends an ACK when
E0h (R/W= 0) or E1h (R/W= 1) is sent by the master.
See Section 7.3.8 “LED All Call I2 C-bus address, ALLCALLADR” for more detail.
Remark: The default LED All Call I2 C-bus address (E0h or 1110 000) must not be used as
a regular I2 C-bus slave address since this address is enabled at power-up. All the
PCA9632s on the I2 C-bus will acknowledge the address if sent by the I2 C-bus master.
7.1.3 LED Sub Call I2 C-bus addresses 3 different I2 C-bus addresses can be used
Default power-up values:
SUBADR1 register: E2h or 1110 001
SUBADR2 register: E4h or 1110 010
SUBADR3 register: E8h or 1110 100
Programmable through I2 C-bus (volatile programming)
At power-up, Sub Call I2 C-bus addresses are disabled. PCA9632 does not send an
ACK when E2h (R/W =0) or E3h (R/W= 1), E4h (R/W= 0) or E5h (R/W =1), or
E8h (R/W= 0) or E9h (R/W= 1) is sent by the master.
See Section 7.3.7 “I2 C-bus subaddress 1to 3, SUBADRx” for more detail.
Remark: The default LED Sub Call I2 C-bus addresses may be used as regular I2 C-bus
slave addresses as long as they are disabled.
NXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driver
7.1.4 Software reset I2 C-bus addressThe address shown in Figure 7 is used when a reset of the PCA9632 needs to be
performed by the master. The Software Reset address (SWRST Call) must be used with
R/W= 0. If R/W= 1, the PCA9632 does not acknowledge the SWRST. See Section 7.5
“Software reset” for more detail.
Remark: The Software Reset I2 C-bus address is a reserved address and cannot be used
as a regular I2 C-bus slave address or as an LED All Call or LED Sub Call address.
7.2 Control registerFollowing the successful acknowledgement of the slave address, LED All Call address or
LED Sub Call address, the bus master will send a byte to the PCA9632, which will be
stored in the Control register.
The lowest 4 bits are used as a pointer to determine which register will be accessed
(D[3:0]). The highest 3 bits are used as Auto-Increment flag and Auto-Increment options
(AI[2:0]). Bit 4 is unused and must be programmed with zero (0) for proper device
operation.
When the Auto-Increment flag is set (AI2= 1), the four low order bits of the Control
register are automatically incremented after a read or write. This allows the user to
program the registers sequentially. Four different types of Auto-Increment are possible,
depending on AI1 and AI0 values.
NXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driver
Remark: Other combinations not shown in Table 4 (AI[2:0] = 001, 010, and 011) are
reserved and must not be used for proper device operation.
AI[2:0]= 000 is used when the same register must be accessed several times during a
single I2 C-bus communication, for example, changes the brightness of a single LED. Data
is overwritten each time the register is accessed during a write operation.
AI[2:0]= 100 is used when all the registers must be sequentially accessed, for example,
power-up programming.
AI[2:0]= 101 is used when the four LED drivers must be individually programmed with
different values during the same I2 C-bus communication, for example, changing color
setting to another color setting.
AI[2:0]= 110 is used when the LED drivers must be globally programmed with different
settings during the same I2 C-bus communication, for example, global brightness or
blinking change.
AI[2:0]= 111 is used when individual and global changes must be performed during the
same I2 C-bus communication, for example, changing a color and global brightness at the
same time.
Only the 4 least significant bits D[3:0] are affected by the AI[2:0] bits.
When the Control register is written, the register entry point determined by D[3:0] is the
first register that will be addressed (read or write operation), and can be anywhere
between 0000 and 1100 (as defined in Table 5). When AI[2]= 1, the Auto-Increment flag
is set and the rollover value at which the point where the register increment stops and
goes to the next one is determined by AI[2:0]. See Table 4 for rollover values. For
example, if the Control register = 1110 1000 (E8h), then the register addressing sequence
will be (in hex): … 0C00…0702…0702…0702 … as long
as the master keeps sending or reading data.
Table 4. Auto-Increment options 0 0 no Auto-Increment 0 0 Auto-Increment for all registers. D3, D2, D1, D0 roll over to ‘0000’ after
the last register (1100) is accessed. 0 1 Auto-Increment for Individual brightness registers only. D3, D2, D1, D0
roll over to ‘0010’ after the last register (0101) is accessed. 1 0 Auto-Increment for global control registers only. D3, D2, D1, D0 roll over
to ‘0110’ after the last register (0111) is accessed. 1 1 Auto-Increment for individual and global control registers only. D3, D2,
D1, D0 roll over to ‘0010’ after the last register (0111) is accessed.
NXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driver
7.3 Register definitionsTable 5. Register summaryOnly D[3:0]= 0000to 1100 are allowed and will be acknowledged. D[3:0]= 1101, 1110, or 1111 are reserved and will not be
acknowledged.
When writing to the Control register, bit 4 must be programmed with logic 0 for proper device operation.
00h 0000MODE1 read/write Mode register 1
01h 0001MODE2 read/write Mode register 2
02h 0010PWM0 read/write brightness control LED0
03h 0011PWM1 read/write brightness control LED1
04h 0100PWM2 read/write brightness control LED2
05h 0101PWM3 read/write brightness control LED3
06h 0110GRPPWM read/write group duty cycle control
07h 0111GRPFREQ read/write group frequency
08h 1000LEDOUT read/write LED output state
09h 1001SUBADR1 read/write I2 C-bus subaddress 1
0Ah 1010SUBADR2 read/write I2 C-bus subaddress 2
0Bh 1011SUBADR3 read/write I2 C-bus subaddress 3
0Ch 1100ALLCALLADR read/write LED All Call I2 C-bus address
NXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driver
7.3.1 Mode register 1, MODE1[1] It takes 500 s max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not
guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 s window.
[2] When the oscillator is off (Sleep mode), the LED outputs cannot be turned on, off or dimmed/blinked.
7.3.2 Mode register 2, MODE2[1] See Section 7.6 “Using the PCA9632 with and without external drivers” for more details. Normal LEDs can be driven directly in either
mode. Some newer LEDs include integrated Zener diodes to limit voltage transients, reduce EMI, protect the LEDs, and these must be
driven only in the open-drain mode to prevent overheating the IC.
[2] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9632. Applicable to registers from
02h (PWM0) to 08h (LEDOUT) only.
Table 6. MODE1 - Mode register 1 (address 00h) bit descriptionLegend: * default value. AI2 read only 0 Register Auto-Increment disabled Register Auto-Increment enabled AI1 read only 0* Auto-Increment bit1=0 Auto-Increment bit1=1 AI0 read only 0* Auto-Increment bit0=0 Auto-Increment bit0=1 SLEEP R/W 0 Normal mode[1] Low power mode. Oscillator off[2] SUB1 R/W 0* PCA9632 does not respond to I2 C-bus subaddress 1. PCA9632 responds to I2 C-bus subaddress 1. SUB2 R/W 0* PCA9632 does not respond to I2 C-bus subaddress 2. PCA9632 responds to I2 C-bus subaddress 2. SUB3 R/W 0* PCA9632 does not respond to I2 C-bus subaddress 3. PCA9632 responds to I2 C-bus subaddress 3. ALLCALL R/W 0 PCA9632 does not respond to LED All Call I2 C-bus address. PCA9632 responds to LED All Call I2 C-bus address.
Table 7. MODE2 - Mode register 2 (address 01h) bit descriptionLegend: * default value. - read only 0* reserved - read only 0* reserved DMBLNK R/W 0* Group control = dimming Group control = blinking
4INVRT[1] R/W 0* Output logic state not inverted. Value to use when no external driver used. Output logic state inverted. Value to use when external driver used. OCH R/W 0* Outputs change on STOP command.[2] Outputs change on ACK.
2OUTDRV[1] R/W 0* The 4 LED outputs are configured with an open-drain structure. The 4 LED outputs are configured with a totem pole structure.to0 OUTNE[1:0] R/W 01* unused
NXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driver
7.3.3 PWM registers 0to 3, PWMx — Individual brightness control registersWhile operating in Individual brightness mode (LDRx= 10), a 1.5625 kHz fixed frequency
signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h % duty cycle = LED output off) to FFh (99.6 % duty cycle = LED output at maximum
brightness). In this mode, all the 8 bits are used.
(1)
E.g., if IDCx[7:0]= 1111 1111, then duty cycle= 255/ 256= 99.6%.
While operating in group dimming mode, a 6.25 kHz fixed frequency signal is used for
each output. Duty cycle is controlled through 64 linear steps from 00h (0 % duty cycle =
LED output off) to 3Fh (98.4 % duty cycle = LED output at maximum brightness). In this
mode only the 6 MSBs are used (IDCx[7:2]). The 2 LSBs IDCx[1:0] are ignored.
Applicable to LED outputs programmed with LDRx= 11 (LEDOUT register).
(2)
E.g., if IDCx[7:2] = 111111, then duty cycle = 1111 1100/ 256= 252/ 256= 98.4 %.
While operating in blink mode, a 1.5625 kHz fixed frequency signal is used for each
output. Duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = LED
output off) to FFh (99.6 % duty cycle = LED output at maximum brightness). In this mode,
all the 8 bits are used.
(3)
E.g., if IDCx[7:0] = 1111 1111, then duty cycle = 255/ 256= 99.6%.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).
Table 8. PWM0to PWM3 - PWM registers 0to 3 (address 02h to 05h) bit descriptionLegend: * default value.
02h PWM0 7:0 IDC0[7:0] R/W 0000 0000* PWM0 Individual Duty Cycle
03h PWM1 7:0 IDC1[7:0] R/W 0000 0000* PWM1 Individual Duty Cycle
04h PWM2 7:0 IDC2[7:0] R/W 0000 0000* PWM2 Individual Duty Cycle
05h PWM3 7:0 IDC3[7:0] R/W 0000 0000* PWM3 Individual Duty Cycle
NXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driver
7.3.4 Group duty cycle control, GRPPWMWhen DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz fixed frequency
signal is superimposed with the 6.25 kHz Individual brightness control signal. GRPPWM
is then used as a global brightness control allowing the LED outputs to be dimmed with
the same value. The value in GRPFREQ is then a ‘don’t care’.
In the group dimming mode (DMBLNK= 0) global brightness for the 4 outputs is
controlled through 16 linear steps from 00h (0 % duty cycle = LED output off) to F0h
(93.75 % duty cycle = maximum brightness). In this mode only the 4 MSBs of the
GRPPWM[7:4] are used. Bits GRPPWM[3:0] are unused.
(4)
E.g., if GDC[7:4] = 1111, then duty cycle = 1111 0000/ 256= 240/ 256= 93.75%.
When DMBLNK bit is programmed with 1, GRPPWM and GRPFREQ registers define a
global blinking pattern, where GRPFREQ contains the blinking period (from 24 Hz to
10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
In this mode, when GRPFREQ is programmed to provide a blinking with frequency
programmable from 24 Hz to 6 Hz, GRPPWM[7:2] is used to provide 64-step duty cycle
resolution from 0 % to 98.4 %. GRPPWM[1:0] bits are unused.
(5)
E.g., if GDC[7:2] = 111111, then duty cycle = 1111 1100/ 256 = 252/ 256 = 98.4%.
When GRPFREQ is programmed to provide a blinking with frequency programmable from Hz to 0.09 Hz (10.73 s), GRPPWM[7:0] is used to provide a 256-step duty cycle
resolution from 0 % to 99.6 %. In this case, all the 8 bits of the GRPPWM register are
used.
(6)
E.g., If GDC[7:0] = 1111 1111, then duty cycle = 255/ 256 = 99.6%.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).
Table 9. GRPPWM - Group duty cycle control register (address 06h) bit descriptionLegend: * default value.
06h GRPPWM 7:0 GDC[7:0] R/W 11111111 GRPPWM register
NXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driver
7.3.5 Group frequency, GRPFREQGRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to logic 1. Value in this register is a ‘don’t care’ when DMBLNK=0.
Applicable to LED outputs programmed with LDRx= 11 (LEDOUT register).
Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)
to FFh (10.73 seconds).
(7)
7.3.6 LED driver output state, LEDOUT
LDRx= 00 — LED driver x is off (default power-up state).
LDRx= 01 — LED driver x is fully on (individual brightness and group dimming/blinking not controlled).
LDRx= 10 — LED driver x individual brightness can be controlled through its PWMx register.
LDRx= 11 — LED driver x individual brightness and group dimming/blinking can be controlled through its PWMx register and the GRPPWM registers.
7.3.7I2 C-bus subaddress 1to 3, SUBADRxSubaddresses are programmable through the I2 C-bus. Default power-up values are E2h,
E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up
(the corresponding SUBx bit in MODE1 register is equal to logic 0).
Table 10. GRPFREQ - Group frequency register (address 07h) bit descriptionLegend: * default value.
07h GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000* GRPFREQ register
Table 11. LEDOUT - LED driver output state register (address 08h) bit descriptionLegend: * default value.
08h LEDOUT 7:6 LDR3 R/W 00* LED3 output state control
5:4 LDR2 R/W 00* LED2 output state control
3:2 LDR1 R/W 00* LED1 output state control
1:0 LDR0 R/W 00* LED0 output state control
Table 12. SUBADR1to SUBADR3 - I2 C-bus subaddress registers 0to 3 (address 09h to
0Bh) bit descriptionLegend: * default value.
09h SUBADR1 7:1 A1[7:1] R/W 1110 001* I2 C-bus subaddress 1 A1[0] R only 0* reserved
0Ah SUBADR2 7:1 A2[7:1] R/W 1110 010* I2 C-bus subaddress 2 A2[0] R only 0* reserved
0Bh SUBADR3 7:1 A3[7:1] R/W 1110 100* I2 C-bus subaddress 3 A3[0] R only 0* reserved
NXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driverOnce subaddresses have been programmed to their right values, SUBx bits need to be
set to 1 in order to have the device acknowledging these addresses (MODE1 register).
Only the 7 MSBs representing the I2 C-bus subaddress are valid. The LSB in SUBADRx
register is a read-only bit (0).
When SUBx is set to 1, the corresponding I2 C-bus subaddress can be used during either
an I2 C-bus read or write sequence.
7.3.8 LED All Call I2 C-bus address, ALLCALLADRThe LED All Call I2 C-bus address allows all the PCA9632s in the bus to be programmed
at the same time (ALLCALL bit in register MODE1 must be equal to 1, power-up default
state). This address is programmable through the I2 C-bus and can be used during either
an I2 C-bus read or write sequence. The register address can be programmed as a
sub call.
Only the 7 MSBs representing the All Call I2 C-bus address are valid. The LSB in
ALLCALLADR register is a read-only bit (0).
If ALLCALL bit= 0, the device does not acknowledge the address programmed in register
ALLCALLADR.
7.4 Power-on resetWhen power is applied to VDD, an internal power-on reset holds the PCA9632 in a reset
condition until VDD has reached VPOR. At this point, the reset condition is released and the
PCA9632 registers and I2 C-bus state machine are initialized to their default states (all
zeroes) causing all the channels to be deselected. Thereafter, VDD must be lowered below
0.2 V to reset the device.
7.5 Software resetThe Software Reset Call (SWRST Call) allows all the devices in the I2 C-bus to be reset to
the power-up state value through a specific formatted I2 C-bus command. To be performed
correctly, it implies that the I2 C-bus is functional and that there is no device hanging the
bus.
The SWRST Call function is defined as the following: A START command is sent by the I2 C-bus master. The reserved SWRST I2 C-bus address ‘0000 011’ with the R/W bit set to 0 (write) is
sent by the I2 C-bus master. The PCA9632 device(s) acknowledge(s) after seeing the SWRST Call address
‘0000 0110’ (06h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to 2
Table 13. ALLCALLADR - LED All Call I2 C-bus address register (address 0Ch) bit
descriptionLegend: * default value.
0Ch ALLCALLADR 7:1 AC[7:1] R/W 1110 000* ALLCALL I2 C-bus
address register AC[0] R only 0* reserved
NXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driver Once the SWRST Call address has been sent and acknowledged, the master sends bytes with 2 specific values (SWRST data byte 1 and byte2): Byte 1= A5h: the PCA9632 acknowledges this value only. If byte 1 is not equal to
A5h, the PCA9632 does not acknowledge it. Byte 2= 5Ah: the PCA9632 acknowledges this value only. If byte 2 is not equal to
5Ah, then the PCA9632 does not acknowledge it.
If more than 2 bytes of data are sent, the PCA9632 does not acknowledge any more. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and
correctly acknowledged, the master sends a STOP command to end the SWRST Call:
the PCA9632 then resets to the default value (power-up value) and is ready to be
addressed again within the specified bus free time (tBUF).
The I2 C-bus master must interpret a non-acknowledge from the PCA9632 (at any time) as
a ‘SWRST Call Abort’. The PCA9632 does not initiate a reset of its registers. This
happens only when the format of the SWRST Call sequence is not correct.
7.6 Using the PCA9632 with and without external driversThe PCA9632 LED output drivers are 5.5 V only tolerant and can sink up to 25 mA at 5V.
If the device needs to drive LEDs to a higher voltage and/or higher current, use of an
external driver is required.
INVRT bit (MODE2 register) can be used to keep the LED PWM control firmware the
same (PWMx and GRPPWM values directly calculated from their respective formulas
and the LED output state determined by LEDOUT register value) independently of the
type of external driver.
OUTDRV bit (MODE2 register) allows minimizing the amount of external components
required to control the external driver (N-type or P-type device).
[1] Correct configuration when LEDs directly connected to the LEDn outputs (connection to VDD through current limiting resistor).
[2] Optimum configuration when external N-type (NPN, NMOS) driver used.
[3] Optimum configuration when external P-type (PNP, PMOS) driver used.
Table 14. Use of INVRT and OUTDRV based on connection to the LEDn outputs
NXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driver[1] External pull-up or LED current limiting resistor connects LEDn to VDD.
7.7 Individual brightness control with group dimming/blinkingA 1.5625 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is
used to control individually the brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can be
applied to the 4 LED outputs):
A lower 190 Hz fixed frequency signal with programmable duty cycle (4 bits, 16 steps)
is used to provide a global brightness control.
A programmable frequency signal from 24 Hz to 1 ⁄10.73 Hz (8 bits, 256 steps) with
programmable duty cycle (6 bits, 64 steps) is used to provide a global blinking control
for (24 Hz to 6 Hz) and (8 bits, 256 steps) for (6 Hz to 1 ⁄10.73 Hz).
Table 15. Output transistors based on LEDOUT registers, INVRT and OUTDRV bitsLED driver off 0 off off high-Z[1] on off VDD off on VSS off on VSS
LED driver on off on VSS off on VSS 0 off off high-Z[1] on off VDD
Individual
brightness
control 0 off Individual PWM (non-inverted) VSS or high-Z[1] = PWMx value 1 Individual PWM
(non-inverted)
Individual PWM (non-inverted) VSS or VDD = PWMx value 0 off Individual PWM (inverted) high-Z[1] PWMx value 1 Individual PWM
(inverted)
Individual PWM (inverted) VDD or VSS = 1 PWMx value
Individual +
group
dimming/
blinking 0 off Individual + Group PWM
(non-inverted)
VSS or high-Z[1]
PWMx/GRPPWM values 1 Individual PWM
(non-inverted)
Individual PWM (non-inverted) VSS or VDD = PWMx/GRPPWM
values 0 off Individual + Group PWM
(inverted)
high-Z[1] PWMx) or GRPPWM) values 1 Individual PWM
(inverted)
Individual PWM (inverted) VDD or VSS =(1 PWMx) or GRPPWM) values
NXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driver
Table 16. Dimming and blinking resolutionIndividual LED brightness
without dimming X X X 1.5625 kHz 256 steps
Individual LED brightness
with global dimming 0 16 steps X 190 Hz with 6.25 kHz modulation 64 steps
Blinking (fast) 11 1 64 steps 256 steps blink frequency = 6 Hz to 24Hz
PWMx frequency = 1.5625 kHz
256 steps
Blinking (slow) 11 1 256 steps 256 steps blink frequency = 0.09 Hz to 6Hz
PWMx frequency = 1.5625 kHz
256 steps
NXP Semiconductors PCA9632
4-bit Fm+ I2 C-bus low power LED driver
8. Characteristics of the I2 C-busThe I2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transferOne data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 11).
8.1.1 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 12).
8.2 System configurationA device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 13).
