7.2.2 Device ID (PCA9670 ID field)
The Device ID field is a 3-byte read-only (24 bits) word giving the following information: 12 bits with the manufacturer name, unique per manufacturer (for example, NXP).9 bits with the part identification, assigned by manufacturer.3 bits with the die revision, assigned by manufacturer (for example, Rev X).
The Device ID is read-only, hardwired in the device and can be accessed as follows: START command The master sends the Reserved Device ID I2 C-bus address ‘1111 100’ with the R/W
bit set to 0 (write). The master sends the I2 C-bus slave address of the slave device it needs to identify.
The LSB is a ‘Don’t care’ value. Only one device must acknowledge this byte (the one
that has the I2 C-bus slave address). The master sends a Re-START command.
Remark: A STOP command followed by a START command will reset the slave state
machine and the Device ID read cannot be performed.
Remark: A STOP command or a Re-START command followed by an access to
another slave device will reset the slave state machine and the Device ID read cannot
be performed. The master sends the Reserved Device ID I2 C-bus address ‘1111 100’ with the R/W
bit set to 1 (read). The device ID read can be done, starting with the 12 manufacturer bits (first byte+ MSB of the second byte), followed by the 9 part identification bits and then the 3 die
revision bits (3 LSB of the third byte). The master ends the reading sequence by NACKing the last byte, thus resetting the
slave device state machine and allowing the master to send the STOP command.
NXP Semiconductors PCA9670
Remote 8-bit I/O expander for Fm+ I2 C-bus with reset
Remark: The reading of the Device ID can be stopped anytime by sending a NACK
command.
Remark: If the master continues to ACK the bytes after the third byte, the PCA9670
rolls back to the first byte and keeps sending the Device ID sequence until a NACK
has been detected.
For the PCA9670, the Device ID is as shown in Figure 10.
Simple code for reading Device ID:

NXP Semiconductors PCA9670
Remote 8-bit I/O expander for Fm+ I2 C-bus with reset
8. I/O programming
8.1 Quasi-bidirectional I/O architecture
A quasi-bidirectional I/O is an input or output port without using a direction control register.
Whenever the master reads the register, the value returned to master depends on the
actual voltage or status of the pin. At power-on, all the ports are HIGH with a weak 100 A
internal pull-up to VDD but can be driven LOW by an internal transistor, or an external
signal. The I/O ports are entirely independent of each other but each I/O octal is controlled
by the same read or write data byte.
Advantages of the quasi-bidirectional I/O over totem pole I/O include: Better for driving LEDs since the p-channel (transistor to VDD) is small, which saves
die size and therefore cost. LED drive only requires an internal transistor to ground,
while the LED is connected to VDD through a current-limiting resistor. T otem pole I/O
have both an n-channel and p-channel transistors, which allow solid HIGH and LOW
output levels without a pull-up resistor — good for logic levels. Simpler architecture — only a single register and the I/O can be both input and output
at the same time. Totem pole I/O have a direction register which specifies the port pin
direction and it is always in that configuration unless the direction is explicitly
changed. Does not require a command byte. The simplicity of one register (no need for the
pointer register or technically, the command byte) is an advantage in some embedded
systems where every byte counts because of memory or bandwidth limitations.
There is only one register to control four possibilities of the port pin: Input HIGH, input
LOW, output HIGH or output LOW.
Input HIGH: The master needs to write 1 to the register to set the port as an input mode
if the device is not in the default power-on condition. The master reads the register to
check the input status. If the external source pulls the port pin up to VDD or drives
logic 1, then the master will read the value of 1.
Input LOW: The master needs to write 1 to the register to set the port to input mode if
the device is not in the default power-on condition. The master reads the register to
check the input status. If the external source pulls the port pin down to VSS or drives
logic 0, which sinks the weak 100 A current source, then the master will read the value
of 0.
Output HIGH: The master writes 1 to the register. There is an additional ‘accelerator’ or
strong pull-up current when the master sets the port HIGH. The additional strong pull-up
is only active during the HIGH time of the acknowledge clock cycle. This accelerator
current helps the port’s 100 A current source make a faster rising edge into a heavily
loaded output, but only at the start of the acknowledge clock cycle to avoid bus
contention if an external signal is pulling the port LOW to VSS/driving the port with
logic 0 at the same time. After the half clock cycle there is only the 100 A current
source to hold the port HIGH.
Output LOW: The master writes 0 to the register. There is a strong current sink
transistor that holds the port pin LOW. A large current may flow into the port, which
could potentially damage the part if the master writes a 0 to the register and an external
source is pulling the port HIGH at the same time.
NXP Semiconductors PCA9670
Remote 8-bit I/O expander for Fm+ I2 C-bus with reset
8.2 Writing to the port (Output mode)
The master (microcontroller) sends the START condition and slave address, setting the
last bit of the address byte to logic 0 for the write mode. The PCA9670 acknowledges and
the master then sends the data byte for P7 to P0 to the port register. As the clock line
goes HIGH, the 8-bit data is presented on the port lines after it has been acknowledged by
the PCA9670. If a LOW is written, the strong pull-down turns on and stays on. If a HIGH is
written, the strong pull-up turns on for 1 ⁄2 of the clock cycle, then the line is held HIGH by
the weak current source. The master can then send a STOP condition or continuing
sending data. The number of data bytes that can be sent successively is not limited and
the previous data is overwritten every time a data byte has been sent and acknowledged.
Ensure a logic 1 is written for any port that is being used as an input to ensure the strong
external pull-down is turned off.
NXP Semiconductors PCA9670
Remote 8-bit I/O expander for Fm+ I2 C-bus with reset
8.3 Reading from a port (Input mode)
The port must have been previously written to logic 1, which is the condition after
power-on reset or hardware reset or software reset. To enter the Read mode the master
(microcontroller) addresses the slave device and sets the last bit of the address byte to
logic 1 (address byte read). The slave will acknowledge and then send the data byte to
the master. The master will NACK and then send the STOP condition or ACK and read the
input register again.
The read of any pin being used as an output will indicate HIGH or LOW depending on the
actual state of the input pin.
If the data on the input port changes faster than the master can read, this data may be
lost. The DATA 2 and DATA 3 are lost because these data did not meet the set-up time
and hold time (see Figure 14).
8.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9670 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9670 registers and I2 C-bus/SMBus state machine will initialize to their default
states of all I/Os to inputs with weak current source to VDD. Thereafter VDD must be
lowered below VPOR and back up to the operation voltage for power-on reset cycle.
8.5 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The
PCA9670 registers and I2 C-bus state machine will be held in their default state until the
RESET input is once again HIGH. This RESET input pin requires a pull-up resistor to VDD
if no active connection is used.
NXP Semiconductors PCA9670
Remote 8-bit I/O expander for Fm+ I2 C-bus with reset
9. Characteristics of the I2 C-bus
The I2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 15).
9.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 16.)
NXP Semiconductors PCA9670
Remote 8-bit I/O expander for Fm+ I2 C-bus with reset
9.2 System configuration
A device generating a message is a ‘transmitter'; a device receiving is the ‘receiver'. The
device that controls the message is the ‘master' and the devices which are controlled by
the master are the ‘slaves' (see Figure 17).
9.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit (see Figure 18). The acknowledge bit is an active LOW level (generated
by the receiving device) that indicates to the transmitter that the data transfer was
successful.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that wants to issue an
acknowledge bit has to pull down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during the HIGH period of the acknowledge bit related
clock pulse; set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
NXP Semiconductors PCA9670
Remote 8-bit I/O expander for Fm+ I2 C-bus with reset
10. Application design-in information
10.1 Bidirectional I/O expander applications
In the 8-bit I/O expander application shown in Figure 19, P0 and P1 are inputs, and P2 to
P7 are outputs. When used in this configuration, during a write, the input (P0 and P1)
must be written as HIGH so the external devices fully control the input ports. The
desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P2 to P7). 10 A internal output HIGH is not enough current source, the port needs external pull-up
resistor. During a read, the logic levels of the external devices driving the input ports (P0
and P1) and the previous written logic level to the output ports (P2 to P7) will be read.
The GPIO also has a reset line (RESET) that can be connected to an output pin of the
microprocessor. Since the device does not have an interrupt output, changes of the I/Os
can be monitored by reading the input register. If both a RESET and INT are needed, use
the PCA9672.
10.2 How to read and write to I/O expander (example)
In the application example of PCA9670 shown in Figure 19, the microcontroller wants to
control the P3 switch ON and the P7 LED ON when the temperature sensor P0 changes. When the system power on:
Core Processor needs to issue an initial command to set P0 and P1 as inputs and
P[7:2] as outputs with value 1010 00 (LED off, MP3 off, camera on, audio off, switch
off and latch off). Operation:
When the temperature changes above the threshold, the temperature sensor signal
will toggle from HIGH to LOW. The INT will be activated and notifies the ‘core
processor’ that there have been changes on the input pins. Read the input register. P0= 0 (temperature sensor has changed), then turn on LED and turn on switch. Software code:
//System Power on
// write to PCA9670 with data 1010 0011b to set P[7:2] outputs and P[1:0] inputs
<0100 0000> <1010 0011>

//Initial setting for PCA9670
while (1) //Looping look for P0 = 0
NXP Semiconductors PCA9670
Remote 8-bit I/O expander for Fm+ I2 C-bus with reset
<0100 0001> <1010 0010>

//Read PCA9670 data
If (P0 == 0) //Temperature sensor activated
// write to PCA9670 with data 0010 1011b to turn on LED (P7), on Switch (P3)
and keep P[1:0] as input ports.
<0100 0000> <0010 1011>

// Write to PCA9670
Exit the loop;
10.3 High current-drive load applications
The GPIO has a minimum guaranteed sinking current of 25 mA per bit at 5.5 V. In
applications requiring additional drive, two port pins may be connected together to sink up
to 50 mA current. Both bits must then always be turned on or off together. Up to 8 pins can
be connected together to drive 200 mA, which is the device recommended total limit.
Each pin needs its own limiting resistor as shown in Figure 20 to prevent damage to the
device should all ports not be turned on at the same time.
10.4 Migration path
NXP offers new, more capable drop-in replacements for the PCA9670 in newer
space-saving packages.
PCA9670 replaces the interrupt output of the PCA9674 with hardware reset input to retain
the maximum number of addresses. PCA9672 replaces address A2 of the PCA9674 with
hardware reset input to retain the interrupt, but limit the number of addresses.
Table 5. PCA9670 migration path
PCF8574/74A 100 kHz 2.5 V to 6V 8 yes no 80 mA
PCA8574/74A 400 kHz 2.3 V to 5.5V 8 yes no 200 mA
PCA9674/74A 1 MHz Fm+ 2.3 V to 5.5V 64 yes no 200 mA
PCA9670 1 MHz Fm+ 2.3 V to 5.5V 64 no yes 200 mA
PCA9672 1 MHz Fm+ 2.3 V to 5.5V 16 yes yes 200 mA
NXP Semiconductors PCA9670
Remote 8-bit I/O expander for Fm+ I2 C-bus with reset
11. Limiting values
[1] Total package (maximum) output current is 400 mA.
12. Thermal characteristics
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage 0.5 +6 V
IDD supply current - 100 mA
ISS ground supply current - 400 mA input voltage VSS 0.5 5.5 V input current - 20 mA output current [1]- 50 mA
Ptot total power dissipation - 400 mW
P/out power dissipation per output - 100 mW
Tj(max) maximum junction temperature - 125 C
Tstg storage temperature 65 +150 C
Tamb ambient temperature operating 40 +85 C
Table 7. Thermal characteristics
Rth(j-a) thermal resistance from junction
to ambient
SO16 package 115 C/W
TSSOP16 package 160 C/W
HVQFN16 package 40 C/W