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PCA9698BS-PCA9698DGG
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
1. General descriptionThe PCA9698 provides 40-bit parallel input/output (I/O) port expansion for I2 C-bus
applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable
of sourcing 10 mA and sinking 25 mA with a total package load of 1 A to allow direct
driving of 40 LEDs. Any of the 40 I/O ports can be configured as an input or output.
The PCA9698 is the first GPIO device in a new Fast-mode Plus (Fm+) family. Fm+
devices offer higher frequency (up to 1 MHz) and longer, more densely populated bus
operation (up to 4000 pF).
The device is fully configurable: output ports can be programmed to be totem-pole or
open-drain and logic states can change at either the Acknowledge (bank change) or the
Stop Command (global change), each input port can be masked to prevent it from
generating interrupts when its state changes, I/O data logic state can be inverted when
read by the system master.
An open-drain interrupt output pin (INT) allows monitoring of the input pins and is asserted
each time a change occurs in one or several input ports (unless masked).
The Output Enable pin (OE) 3-states any I/O selected as output and can be used as an
input signal to blink or dim LEDs (PWM with frequency >80 Hz and change duty cycle).
A ‘GPIO All Call’ command allows to program multiple Advanced GPIOs at the same time
even if they have different I2 C-bus addresses. This allows optimal code programming
when more than one device needs to be programmed with the same instruction or if all
outputs need to be turned on or off at the same time (for example, LED test).
The Device ID, hard coded in the PCA9698, allows the system master to read
manufacturer, part type and revision information.
The SMBus Alert feature allows the SMBALERT pins of multiple devices with this feature
to be connected together to form a wired-AND signal and to be used in conjunction with
the SMBus Alert Response Address.
The internal Power-On Reset (POR) or hardware reset pin (RESET) initializes the 40 I/Os
as inputs. Three address select pins configure one of 64 slave addresses.
The PCA9698 is available in 56-pin TSSOP and HVQFN packages and is specified over
the −40 °C to +85 °C industrial temperature range.
2. Features and benefits1 MHz Fast-mode Plus I2 C-bus serial interface Compliant with I2 C-bus Fast-mode (400 kHz) and Standard-mode (100 kHz)
PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
Rev. 3 — 3 August 2010 Product data sheet
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os 40 configurable I/O pins that default to inputs at power-up Outputs: Programmable totem-pole (10 mA source, 25 mA sink) or open-drain (25 mA sink)
with controlled edge rate output structure. Default to totem-pole on power-up. Active LOW Output Enable (OE) input pin 3-states all outputs. Polarity can be
programmed to active HIGH through the I2 C-bus. Defaults to OE on power-up. Output state change programmable on the Acknowledge or the STOP Command to
update outputs byte-by-byte or all at the same time respectively. Defaults to
Acknowledge on power-up. Inputs: Open-drain active LOW Interrupt (INT) output pin allows monitoring of logic level
change of pins programmed as inputs Programmable Interrupt Mask Control for input pins that do not require an interrupt
when their states change Polarity Inverter register allows inversion of the polarity of the I/O pins when read Active LOW SMBus Alert (SMBALERT) output pin allows to initiate SMBus ‘Alert
Response Address’ sequence. Own slave address sent when sequence initiated. Active LOW Reset (RESET) input pin resets device to power-up default state GPIO All Call address allows programming of more than one device at the same time
with the same parameters 64 programmable slave addresses using 3 address pins Readable Device ID (manufacturer, device type and revision) Designed for live insertion in PICMG applications Minimize line disturbance (IOFF and power-up 3-state) Signal transient rejection (50 ns noise filter and robust I2 C-bus state machine) Low standby current −40 °C to +85 °C operation ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: TSSOP56, and HVQFN56
3. Applications Servers RAID systems Industrial control Medical equipment PLCs Cell phones Gaming machines Instrumentation and test measurement
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
4. Ordering information
5. Block diagram
Table 1. Ordering informationTamb= −40 °C to +85°C
PCA9698DGG PCA9698DGG TSSOP56 plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
SOT364-1
PCA9698BS PCA9698BS HVQFN56 plastic thermal enhanced very thin quad flat package; leads; 56 terminals; body8×8× 0.85 mm
SOT684-1
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INTNXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
6. Pinning information
6.1 PinningNXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
6.2 Pin description
Table 2. Pin descriptionSDA 1 50 input/output serial data line
SCL 2 51 input serial clock line
IO0_0 to IO0_7 3, 4, 5, 7, 9, 10, 12
52, 53, 54, 56,
1, 2, 3, 5
input/output input/output bank 0
IO1_0 to IO1_7 13, 14, 15, 16,
17, 19, 20, 21
6, 7, 8, 9, 10,
12, 13, 14
input/output input/output bank 1
IO2_0 to IO2_7 22, 24, 25, 26,
31, 32, 33, 35
15, 17, 18, 19,
24, 25, 26, 28
input/output input/output bank 2
IO3_0 to IO3_7 36, 37, 38, 40,
41, 42, 43, 44
29, 30, 31, 33,
34, 35, 36, 37
input/output input/output bank 3
IO4_0 to IO4_7 45, 47, 48, 49,
50, 52, 53, 54
38, 40, 41, 42,
43, 45, 46, 47
input/output input/output bank 4
VSS 6, 11, 23,
34, 39,51
4, 16, 27, 32,
44, 55[1] power supply supply ground
VDD 18, 46 11, 39 power supply supply voltage
AD0 27 20 input address input 0
AD1 28 21 input address input 1
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT[1] HVQFN56 package die supply ground is connected to both VSS pins and exposed center pad. VSS pins
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board and for proper heat conduction through the board, thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
7. Functional descriptionRefer to Figure 1 “Block diagram of PCA9698”.
7.1 Device addressFollowing a START condition the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9698 is shown in Figure 5. Slave address pins AD2, AD1 and AD0 choose 1 of slave addresses. To conserve power, no internal pull-up resistors are incorporated on
AD2, AD1 and AD0. Address values depending on AD2, AD1 and AD0 can be found in
Table 12 “PCA9698 address map”.
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected while a logic 0 selects a write operation.
AD2 29 22 input address input 2 30 23 input active LOW output enable
INT/SMBALERT 55 48 output active LOW interrupt output/
active LOW SMBus alert
output
RESET 56 49 input active LOW reset input
Table 2. Pin description …continued
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
7.2 Alert response, GPIO All Call and Device ID addressesThree other different addresses can be sent to the PCA9698.
Alert Response address: allows to perform an ‘SMBus Alert’ operation as defined in
the SMBus specification. This address is always used to perform a Read operation.
See Section 7.11 “SMBus Alert output (SMBALERT)” for more information.
GPIO All Call address: allows to program several Advanced GPIO devices at the
same time. This address is always used to perform a Write operation. See Section 7.6
“GPIO All Call” for more information.
Device ID address: allows to read ID information from the device (manufacturer, part
identification, revision). See Section 7.5 “Device ID - PCA9698 ID field” for more
information.
7.3 Command registerFollowing the successful acknowledgement of the slave address+ R/W bit, the bus
master will send a byte to the PCA9698, which will be stored in the Command register.
The lowest 6 bits are used as a pointer to determine which register will be accessed.
Registers are divided into 2 categories: 5-bank register category, and 1-bank register
category.
Only a command register code with the 7 least significant bits equal to the 28 allowable
values as defined in Table 3 “Register summary” will be acknowledged. Reserved or
undefined command codes will not be acknowledged. At power-up, this register defaults
to 80h, with the AI bit set to ‘1’, and the lowest 7 bits set to ‘0'.
During a write operation, the PCA9698 will acknowledge a byte sent to the OP, PI, IOC,
MSK, OUTCONF, ALLBNK, and MODE registers, but will not acknowledge a byte sent to
the IPx registers since these are read-only registers.
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
7.3.1 5-bank register category IP – Input registers
OP – Output registers
PI – Polarity Inversion registers
IOC – I/O Configuration registers
MSK – Mask interrupt registers
If the Auto-Increment flag is set (AI= 1), the 3 least significant bits are automatically
incremented after a read or write. This allows the user to program and/or read the register banks sequentially.
If more than 5 bytes of data are written and AI= 1, previous data in the selected registers
will be overwritten or reread. Reserved registers are skipped and not accessed (refer to
Table 3).
If the Auto-Increment flag is cleared (AI= 0), the 3 least significant bits are not
incremented after data is read or written, only one register will be repeatedly read or
written.
7.3.2 1-bank register category OUTCONF – Output Structure Configuration register
ALLBNK – All Bank Control register
MODE – Mode Selection register
If more than 1 byte of data is written or read, previous data in the same register is
overwritten independently of the value of AI.
7.4 Register definitionsTable 3. Register summary
Input Port registers00h 0 0 0 0 0 0 IP0 read only Input Port register bank 0
01h 0 0 0 0 0 1 IP1 read only Input Port register bank 1
02h 0 0 0 0 1 0 IP2 read only Input Port register bank 2
03h 0 0 0 0 1 1 IP3 read only Input Port register bank 3
04h 0 0 0 1 0 0 IP4 read only Input Port register bank 4
05h 0 0 0 1 0 1 - - reserved for future use
06h 0 0 0 1 1 0 - - reserved for future use
07h 0 0 0 1 1 1 - - reserved for future use
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
Output Port registers08h 0 0 1 0 0 0 OP0 read/write Output Port register bank 0
09h 0 0 1 0 0 1 OP1 read/write Output Port register bank 1
0Ah 0 0 1 0 1 0 OP2 read/write Output Port register bank 2
0Bh 0 0 1 0 1 1 OP3 read/write Output Port register bank 3
0Ch 0 0 1 1 0 0 OP4 read/write Output Port register bank 4
0Dh 0 0 1 1 0 1 - - reserved for future use
0Eh 0 0 1 1 1 0 - - reserved for future use
0Fh 0 0 1 1 1 1 - - reserved for future use
Polarity Inversion registers10h 0 1 0 0 0 0 PI0 read/write Polarity Inversion register bank 0
11h 0 1 0 0 0 1 PI1 read/write Polarity Inversion register bank 1
12h 0 1 0 0 1 0 PI2 read/write Polarity Inversion register bank 2
13h 0 1 0 0 1 1 PI3 read/write Polarity Inversion register bank 3
14h 0 1 0 1 0 0 PI4 read/write Polarity Inversion register bank 4
15h 0 1 0 1 0 1 - - reserved for future use
16h 0 1 0 1 1 0 - - reserved for future use
17h 0 1 0 1 1 1 - - reserved for future use
I/O Configuration registers18h 0 1 1 0 0 0 IOC0 read/write I/O Configuration register bank 0
19h 0 1 1 0 0 1 IOC1 read/write I/O Configuration register bank 1
1Ah 0 1 1 0 1 0 IOC2 read/write I/O Configuration register bank 2
1Bh 0 1 1 0 1 1 IOC3 read/write I/O Configuration register bank 3
1Ch 0 1 1 1 0 0 IOC4 read/write I/O Configuration register bank 4
1Dh 0 1 1 1 0 1 - - reserved for future use
1Eh 0 1 1 1 1 0 - - reserved for future use
1Fh 0 1 1 1 1 1 - - reserved for future use
Mask Interrupt registers20h 1 0 0 0 0 0 MSK0 read/write Mask interrupt register bank 0
21h 1 0 0 0 0 1 MSK1 read/write Mask interrupt register bank 1
22h 1 0 0 0 1 0 MSK2 read/write Mask interrupt register bank 2
23h 1 0 0 0 1 1 MSK3 read/write Mask interrupt register bank 3
24h 1 0 0 1 0 0 MSK4 read/write Mask interrupt register bank 4
25h 1 0 0 1 0 1 - - reserved for future use
26h 1 0 0 1 1 0 - - reserved for future use
27h 1 0 0 1 1 1 - - reserved for future use
Miscellaneous28h 1 0 1 0 0 0 OUTCONF read/write output structure configuration
29h 1 0 1 0 0 1 ALLBNK read/write control all banks
2Ah 1 0 1 0 1 0 MODE read/write PCA9698 mode selection
Table 3. Register summary …continued
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
7.4.1 IP0 to IP4 - Input Port registersThese registers are read-only. They reflect the incoming logic levels of the port pins
regardless of whether the pin is defined as an input or an output by the I/O Configuration
register. If the corresponding Px[y] bit in the PI registers is set to 0, or the inverted
incoming logic levels if the corresponding Px[y] bit in the PI register is set to 1. Writes to
these registers have no effect.
The Polarity Inversion register can invert the logic states of the port pins. The polarity of
the corresponding bit is inverted when Px[y] bit in the PI register is set to 1. The polarity of
the corresponding bit is not inverted when Px[y] bits in the PI register is set to 0.
7.4.2 OP0 to OP4 - Output Port registersThese registers reflect the outgoing logic levels of the pins defined as outputs by the
I/O Configuration register. Bit values in these registers have no effect on pins defined as
inputs. In turn, reads from these registers reflect the values that are in the flip-flops
controlling the output selection, not the actual pin values.
Ox[y]= 0: IOx_y= 0 if IOx_y defined as output (Cx[y] in IOC register= 0).
Ox[y]= 1: IOx_y= 1 if IOx_y defined as output (Cx[y] in IOC register= 0).
Where ‘x’ refers to the bank number (0to 4); ‘y’ refers to the bit number (0to7).
Table 4. IP0 to IP4 - Input Port registers (address 00h to 04h) bit descriptionLegend: * default value ‘X’ determined by the externally applied logic level.
00h IP0 7 to 0 I0[7:0] R XXXX XXXX* Input Port register bank 0
01h IP1 7 to 0 I1[7:0] R XXXX XXXX* Input Port register bank 1
02h IP2 7 to 0 I2[7:0] R XXXX XXXX* Input Port register bank 2
03h IP3 7 to 0 I3[7:0] R XXXX XXXX* Input Port register bank 3
04h IP4 7 to 0 I4[7:0] R XXXX XXXX* Input Port register bank 4
Table 5. OP0 to OP4 - Output Port registers (address 08h to 0Ch) bit descriptionLegend: * default value.
08h OP0 7 to 0 O0[7:0] R/W 0000 0000* Output Port register bank 0
09h OP1 7 to 0 O1[7:0] R/W 0000 0000* Output Port register bank 1
0Ah OP2 7 to 0 O2[7:0] R/W 0000 0000* Output Port register bank 2
0Bh OP3 7 to 0 O3[7:0] R/W 0000 0000* Output Port register bank 3
0Ch OP4 7 to 0 O4[7:0] R/W 0000 0000* Output Port register bank 4
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
7.4.3 PI0 to PI4 - Polarity Inversion registersThese registers allow inversion of the polarity of the corresponding Input Port register.
Px[y]= 0: The corresponding Input Port register data polarity is retained.
Px[y]= 1: The corresponding Input Port register data polarity is inverted.
Where ‘x’ refers to the bank number (0to 4); ‘y’ refers to the bit number (0to7).
7.4.4 IOC0 to IOC4 - I/O Configuration registersThese registers configure the direction of the I/O pins.
Cx[y]= 0: The corresponding port pin is an output.
Cx[y]= 1: The corresponding port pin is an input.
Where ‘x’ refers to the bank number (0to 4); ‘y’ refers to the bit number (0to7).
Table 6. PI0 to PI4 - Polarity Inversion registers (address 10h to 14h) bit descriptionLegend: * default value.
10h PI0 7 to 0 P0[7:0] R/W 0000 0000* Polarity Inversion register bank 0
11h PI1 7 to 0 P1[7:0] R/W 0000 0000* Polarity Inversion register bank 1
12h PI2 7 to 0 P2[7:0] R/W 0000 0000* Polarity Inversion register bank 2
13h PI3 7 to 0 P3[7:0] R/W 0000 0000* Polarity Inversion register bank 3
14h PI4 7 to 0 P4[7:0] R/W 0000 0000* Polarity Inversion register bank 4
Table 7. IOC0 to IOC4 - I/O Configuration registers (address 18h to 1Ch) bit descriptionLegend: * default value.
18h IOC0 7 to 0 C0[7:0] R/W 1111 1111* I/O Configuration register bank 0
19h IOC1 7 to 0 C1[7:0] R/W 1111 1111* I/O Configuration register bank 1
1Ah IOC2 7 to 0 C2[7:0] R/W 1111 1111* I/O Configuration register bank 2
1Bh IOC3 7 to 0 C3[7:0] R/W 1111 1111* I/O Configuration register bank 3
1Ch IOC4 7 to 0 C4[7:0] R/W 1111 1111* I/O Configuration register bank 4
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
7.4.5 MSK0 to MSK4 - Mask interrupt registersThese registers mask the interrupt due to a change in the I/O pins configured as inputs.
‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Mx[y] = 0: A level change at the I/O will generate an interrupt if IOx_y defined as input
(Cx[y] in IOC register = 1).
Mx[y] = 1: A level change in the input port will not generate an interrupt if IOx_y defined
as input (Cx[y] in IOC register = 1).
7.4.6 OUTCONF - output structure configuration registerThis register controls the configuration of the output ports as open-drain or totem-pole.
The 4 least significant bits control the output architecture for bank 0, 2 bits at a time.
OUT001 controls the output structure for IO0_0 and IO0_1
OUT023 controls the output structure for IO0_2 and IO0_3
OUT045 controls the output structure for IO0_4 and IO0_5
OUT067 controls the output structure for IO0_6 and IO0_7
The 4 most significant bits control the output architectures for bank 1 to bank 4, each bit
controlling one bank.
OUT1 controls the output structure for bank 1 (IO1_0 to IO1_7)
OUT2 controls the output structure for bank 2 (IO2_0 to IO2_7)
OUT3 controls the output structure for bank 3 (IO3_0 to IO3_7)
OUT4 controls the output structure for bank 4 (IO4_0 to IO4_7)
OUTx = 0: The I/Os are configured with an open-drain structure.
OUTx = 1: The I/Os are configured with a totem-pole structure.
Table 8. MSK0 to MSK4 - Mask interrupt registers (address 20h to 24h) bit descriptionLegend: * default value.
20h MSK0 7 to 0 M0[7:0] R/W 1111 1111* Mask Interrupt register bank 0
21h MSK1 7 to 0 M1[7:0] R/W 1111 1111* Mask Interrupt register bank 1
22h MSK2 7 to 0 M2[7:0] R/W 1111 1111* Mask Interrupt register bank 2
23h MSK3 7 to 0 M3[7:0] R/W 1111 1111* Mask Interrupt register bank 3
24h MSK4 7 to 0 M4[7:0] R/W 1111 1111* Mask Interrupt register bank 4
Table 9. OUTCONF - output structure configuration register (address 28h) description
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
7.4.7 ALLBNK - All Bank control registerThis register allows all the I/Os configured as outputs to be programmed with the same
logic value. This programming is applied to all the banks or a selection of banks.
When this register is programmed, values in the Output Port registers are not changed
and do not reflect the states of I/Os configured as outputs anymore.
B0 to B4 controls the logic level to be applied to Bank 0 to Bank 4, respectively.
Bx = 0: All the I/Os configured as outputs in the corresponding Bank x are
programmed with 0s.
Bx = 1: All the I/Os configured as outputs in the corresponding Bank x are
programmed with 1s.
Bit 5 and bit 6 are not used and can be programmed to either ‘1’ or ‘0’.
BSEL is a filter bit that allows programming of some banks only, and not the others.
BSEL = 0:
When Bx = 0, all the I/Os configured as output in the corresponding Bank x are
programmed with 0s.
When Bx = 1, all the I/Os configured as output in the corresponding Bank x are
programmed with their actual value from the corresponding output register.
BSEL = 1:
When Bx = 0, all the I/Os configured as output in the corresponding Bank x are
programmed with their actual value from the corresponding output register.
When Bx = 1, all the I/Os configured as output in the corresponding Bank x are
programmed with 1s.
7.4.7.1 Examples If ALLBNK = 0XX0 0000:
All I/Os configured as outputs in Bank 0 to Bank 4 will be programmed with 0s,
overwriting values programmed in the five Output Port registers.
If ALLBNK = 1XX1 1111:
All I/Os configured as outputs in Bank 0 to Bank 4 will be programmed with 1s,
overwriting values programmed in the five Output Port registers.
If ALLBNK = 0XX0 0110:
All I/Os configured as outputs in Banks 0, 3, and 4 only will be programmed with 0s,
overwriting values programmed in the Output Port registers 0, 3, and 4, while I/Os
configured as outputs in Bank 1 and Bank 2 are programmed with values in Output
Port registers 1 and 2.
Table 10. ALLBNK - All Bank control register (address 29h) description
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT If ALLBNK = 1XX0 1100:
All I/Os configured as outputs in Bank 2 and 3 will be programmed with 1s, overwriting
values programmed in the Output Port registers 2 and 3, while I/Os configured as
outputs in Bank 0, 1, and 4 are programmed with values in Output Port registers 0, 1,
and 4.
7.4.8 MODE - PCA9698 mode selection registerThis register allows programming of the PCA9698 modes.
OEPOL bit controls the polarity of OE pin.
OEPOL= 0: OE pin is active LOW.
OEPOL= 1: OE pin is active HIGH (equivalent to OE pin).
OCH bit selects the I2 C-bus event where the state of the I/Os configured as outputs
change.
OCH= 0: outputs change on STOP command.
OCH = 1: outputs change on ACK.
IOAC bit controls the ability of the device to respond to a ‘GPIO All Call’ command
(see Section 7.6 “GPIO All Call” for more information), allowing programming of more
than one device at the same time.
IOAC = 0: The device cannot respond to a ‘GPIO All Call’ command.
IOAC = 1: The device can respond to a ‘GPIO All Call’ command.
Remark: The ‘GPIO ALL CALL’ command defined for the PCA9698 is different from the I2 C-bus protocol ‘General Call’ command.
SMBA bit controls the capability of the PCA9698 to respond to a SMBAlert command.
SMBA = 0: PCA9698 does not respond to an Alert Response Address.
SMBA = 1: PCA9698 responds to an Alert Response Address. Bits 5, 6 and 7 are
reserved and must be programmed with 0s.
Unused bits (bits 2, 5, 6 and 7) must be programmed with 0s for proper device
operation.
Table 11. MODE - mode selection register (address 2Ah) description
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
7.5 Device ID - PCA9698 ID fieldThe Device ID field is a 3 byte read-only (24 bits) word giving the following information:
12 bits with the manufacturer name, unique per manufacturer (e.g., NXP)
9 bits with the part identification, assigned by manufacturer (e.g., PCA9698)
3 bits with the die revision, assigned by manufacturer (e.g., RevX)
The Device ID is read-only, hard-wired in the device and can be accessed as follows: START command The master sends the Reserved Device ID I2 C-bus address followed by the R/W bit
set to ‘0’ (write): ‘1111 1000’. The master sends the I2 C-bus slave address of the slave device it needs to identify.
The LSB is a ‘Don’t care’ value. Only one device must acknowledge this byte (the one
that has the I2 C-bus slave address). The master sends a Re-START command.
Remark: A STOP command followed by a START command will reset the slave state machine and the Device ID Read cannot be performed. Also, a STOP command or a
Re-START command followed by an access to another slave device will reset the
slave state machine and the Device ID Read cannot be performed. The master sends the Reserved Device ID I2 C-bus address followed by the R/W bit
set to ‘1’ (read): ‘1111 1001’. The Device ID Read can be done, starting with the 12 manufacturer bits (first byte + MSBs of the second byte), followed by the 9 part identification bits (4 LSBs of the
second byte + 5 MSBs of the third byte), and then the 3 die revision bits (3 LSBs of
the third byte). The master ends the reading sequence by NACKing the last byte, thus resetting the
slave device state machine and allowing the master to send the STOP command.
Remark: The reading of the Device ID can be stopped anytime by sending a NACK command.
If the master continues to ACK the bytes after the third byte, the PCA9698 rolls back
to the first byte and keeps sending the Device ID sequence until a NACK has been
detected.
For the PCA9698, the Device ID is as shown in Figure 10.
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
7.6 GPIO All CallA ‘GPIO All Call’ command allows the programming of multiple advanced GPIOs with
different I2 C-bus addresses at the same time. This allows to optimize code programming
when the master needs to send the same instruction to several devices. To respond to
such a command and sequence, the PCA9698 needs to have its IOAC bit (register 2Ah,
bit 3) set to 1. Devices that have this bit set to 0 do not participate in any ‘GPIO All Call’
sequence.
The ‘GPIO All Call’ command can be performed only for a write operation and cannot be
used in conjunction with a read operation.
Master initiates a command sequence with the START command, the ‘GPIO All Call’
command associated with a Write command: Start − 1101 110 + Write
All the devices that are programmed to respond to this command will acknowledge
The master then sends the data and all the devices that are programmed to respond
acknowledge the byte(s)
The master ends the sequence by sending a STOP or Repeated START command.
If the master initiates a ‘GPIO All Call’ sequence with a Read command, none of the slave
devices acknowledge.
7.7 Output state change on ACK or STOPState change of the I/Os programmed as outputs can be done either:
during the ACK phase every time an Output Port register is modified. The output state
is then updated one-by-one (at a bank level): OCHbit= 1 (register 2Ah, bit1)
at a STOP command allowing all the outputs to change at the exact same moment:
OCHbit= 0 (register 2Ah, bit 1).
Change of the outputs at the STOP command allows synchronizing of all the programmed
banks in a single device, and also allows synchronizing outputs of more than one
PCA9698.
Example 1: Only one PCA9698 is used on the I2 C-bus and all the outputs need to change
at the same time.
OCH bit (Mode Selection Register, bit 1) must be equal to ‘0’.
The master accesses the device and programs the Output Port register(s) that has
(have) to be changed (up to 5 ports).
When done, the master must generate a STOP command.
At the STOP command, the PCA9698 will update the Output Port register(s) that has
(have) been programmed and change the output states all at the same time.
Example 2: More than one PCA9698 is used on the I2 C-bus and all the outputs need to
change at the same time.
OCH bit (Mode Selection Register, bit 1) must be equal to ‘0’ in all the devices.
The master device must access the devices one-by-one.
Access to each device must be separated by a Re-START command.
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT When all the devices have been accessed, the master must generate a STOP
command.
At the STOP command, all the PCA9698s that have been accessed will update their
Output Port registers that have been programmed and change the output states all at
the same time.
Remark: After programming a PCA9698, its state machine will be in a ‘wait-for-STOP-condition’ until a STOP condition is received to update the Output Port
registers. Since this state machine will be in a ‘wait-state’, the part will not respond to its
own address until this state machine gets out to the idle condition, which means that the
device can be programmed only once and is not addressable again until a STOP
condition has been received.
Remark: The PCA9698 has one level of buffers to store 5 bytes of data, and the actual
Output Port registers will get updated on the STOP condition. If the master sends more
than 5 bytes of data (with AI= 1), the data in the buffer will get overwritten.
7.8 Power-on resetWhen power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9698 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9698 registers and I2 C-bus/SMBus state machine will initialize to their default
states. Thereafter, VDD must be lowered below 0.2 V to reset the device.
7.9 RESET inputA reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The
PCA9698 registers and I2 C-bus state machine will be held in their default state until the
RESET input is once again HIGH.
7.10 Interrupt output (INT)The open-drain active LOW interrupt is activated when one of the port pins changes state
and the port pin is configured as an input and the interrupt on it is not masked. The
interrupt is deactivated when the port pin input returns to its previous state or the Input
Port register is read.
It is highly recommended to program the MSK register, and the IOC registers during the
initialization sequence after power-up, since any change to them during Normal mode
operation may cause undesirable interrupt events to happen.
Remark: Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register.
Only a Read of the Input Port register that contains the bit(s) image of the input(s) that
generated the interrupt clears the interrupt condition.
If more than one input register changed state before a read of the Input Port register is
initiated, the interrupt is cleared when all the input registers containing all the inputs that
changed are read.
Example: If IO0_5, IO2_3, and IO3_7 change state at the same time, the interrupt is
cleared only when INREG0, INREG2, and INREG3 are read.
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
7.11 SMBus Alert output (SMBALERT)The interrupt output pin (INT) can also be used as an Alert line (SMBALERT).
The SMBALERT pins of multiple devices with this feature can be connected together to
form a wired-AND signal and can be used in conjunction with the SMBus Alert Response
Address. ‘SMBus Alert’ message is 2 bytes long and allows the master to determine
which device generated the Alert (SMBALERT going LOW).
When SMBAbit= 1 (register 2Ah, bit 4), the PCA9698 supports the SMBus Alert function
and its INT/SMBALERT pin may be connected as an SMBus Alert signal.
When a master device senses that an ‘SMBus Alert’ condition is present on the ALERT
line (SMBALERT pin of the PCA9698 and/or other devices going LOW):
It accesses the slave device(s) through the Alert Response Address (ARA)
associated with a Read Command: Start− 0001 100+ R/W =1.
If the PCA9698 is the device that generated the ‘SMBus Alert’ condition (and its
SMBAbit= 1), it will acknowledge the SMBus Alert command and respond by
transmitting its slave address on the SDA line. The 8th bit (LSB) of the slave address
byte will be a zero.
The device will acknowledge an ARA command only if the SMBALERT signal has
been previously asserted (SMBALERT = LOW).
If more than one device pulls its SMBALERT pin LOW, the highest priority (lowest 2 C-bus address) device will win communication rights via standard I2 C-bus arbitration
during the slave address transfer.
If the PCA9698 wins the arbitration, its SMBALERT pin will become inactive (will go
HIGH) at the completion of the slave address transmission (9th clock pulse, NACK
phase).
If the PCA9698 loses the arbitration, its SMBALERT pin will remain active (will stay
LOW).
The master ends the sequence by sending a NACK and then STOP command.
If the SMBALERT is still LOW after transfer is complete, it means that more than one
device made the request. Another full transaction is then required.
Remark: If the master initiates an ‘SMBus Alert’ sequence with a Write Command, none of the slave devices acknowledge. The SMBALERT is open-drain and requires a pull-up
resistor to VDD.
Remark: If the master sends an ACK after reading the I2 C-bus slave address, the slave
device keeps sending ‘1’s until a NACK is received.
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
7.12 Output enable input (OE)The configurable active LOW or active HIGH output enable pin allows to enable or disable
all the I/Os at the same time.
When a LOW level is applied to the OE pin, with OEPOL= 0 (register 2Ah, bit 4) or a
HIGH level is applied to the OE pin, with OEPOL= 1 (register 2Ah, bit 0), all the I/Os
configured as outputs are enabled and the logic value programmed in their respective
OP registers is applied to the pins.
When a HIGH level is applied to the OE pin, with OEPOL= 0 (register 2Ah, bit 0) or a
LOW level is applied to the OE pin, with OEPOL= 1 (register 2Ah, bit 0), all the I/Os
configured as outputs are 3-stated.
For applications requiring LED blinking with brightness control, this pin can be used to
control the brightness by applying a high frequency PWM signal on the OE pin. LEDs can
be blinked using the Output Port registers and can be dimmed using the PWM signal on
the OE pin thus controlling the brightness by adjusting the duty cycle.
Default is OEPOL= 0, so if the OE pin is held HIGH, the outputs are disabled. The OE pin
needs to be pulled LOW or OEPOL changed to ‘1’ to enable the outputs.
It is recommended to define the required polarity of the OE input by programing the value
of OEPOL before programming the configuration registers (IOC register).
7.13 Live insertionThe PCA9698 is fully specified for live-insertion applications using IOFF, power-up
3-states, robust state machine, and 50 ns noise filter. The IOFF circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-states circuitry places the outputs in the high-impedance state
during power-up and power-down, which prevents driver conflict and bus contention.
The robust state machine does not respond until it sees a valid START condition and the ns noise filter will filter out any insertion glitches. The PCA9698 will not cause
corruption of active data on the bus nor will the device be damaged or cause damage to
devices already on the bus when similar featured devices are being used.
7.14 StandbyThe PCA9698 goes into standby when the I2 C-bus is idle. Standby supply current is lower
than 1.0 μA (typical).
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
7.15 Address map Table 12. PCA9698 address mapVSS SCL VSS 001 0000 20h
VSS SCL VDD 001 0001 22h
VSS SDA VSS 001 0010 24h
VSS SDA VDD 001 0011 26h
VDD SCL VSS 001 0100 28h
VDD SCL VDD 001 0101 2Ah
VDD SDA VSS 001 0110 2Ch
VDD SDA VDD 001 0111 2Eh
VSS SCL SCL 001 1000 30h
VSS SCL SDA 001 1001 32h
VSS SDA SCL 001 1010 34h
VSS SDA SDA 001 1011 36h
VDD SCL SCL 001 1100 38h
VDD SCL SDA 001 1101 3Ah
VDD SDA SCL 001 1110 3Ch
VDD SDA SDA 001 1111 3Eh
VSS VSS VSS 010 0000 40h
VSS VSS VDD 010 0001 42h
VSS VDD VSS 010 0010 44h
VSS VDD VDD 010 0011 46h
VDD VSS VSS 010 0100 48h
VDD VSS VDD 010 0101 4Ah
VDD VDD VSS 010 0110 4Ch
VDD VDD VDD 010 0111 4Eh
VSS VSS SCL 010 1000 50h
VSS VSS SDA 010 1001 52h
VSS VDD SCL 010 1010 54h
VSS VDD SDA 010 1011 56h
VDD VSS SCL 010 1100 58h
VDD VSS SDA 010 1101 5Ah
VDD VDD SCL 010 1110 5Ch
VDD VDD SDA 010 1111 5Eh
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INTSCL SCL VSS 101 0000 A0h
SCL SCL VDD 101 0001 A2h
SCL SDA VSS 101 0010 A4h
SCL SDA VDD 101 0011 A6h
SDA SCL VSS 101 0100 A8h
SDA SCL VDD 101 0101 AAh
SDA SDA VSS 101 0110 ACh
SDA SDA VDD 101 0111 AEh
SCL SCL SCL 101 1000 B0h
SCL SCL SDA 101 1001 B2h
SCL SDA SCL 101 1010 B4h
SCL SDA SDA 101 1011 B6h
SDA SCL SCL 101 1100 B8h
SDA SCL SDA 101 1101 BAh
SDA SDA SCL 101 1110 BCh
SDA SDA SDA 101 1111 BEh
SCL VSS VSS 110 0000 C0h
SCL VSS VDD 110 0001 C2h
SCL VDD VSS 110 0010 C4h
SCL VDD VDD 110 0011 C6h
SDA VSS VSS 110 0100 C8h
SDA VSS VDD 110 0101 CAh
SDA VDD VSS 110 0110 CCh
SDA VDD VDD 110 0111 CEh
SCL VSS SCL 111 0001 E0h
SCL VSS SDA 111 0010 E2h
SCL VDD SCL 111 0011 E4h
SCL VDD SDA 111 0100 E6h
SDA VSS SCL 111 0101 E8h
SDA VSS SDA 111 0110 EAh
SDA VDD SCL 111 0111 ECh
SDA VDD SDA 111 0001 EEh
Table 12. PCA9698 address map …continued
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
8. Characteristics of the I2 C-busThe I2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transferOne data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 11).
8.1.1 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 12.)
NXP Semiconductors PCA9698
40-bit Fm+ I2 C-bus advanced I/O port with RESET, OE and INT
8.2 System configurationA device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 13).
8.3 AcknowledgeThe number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
