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PCA9701HF-PCA9701PW-PCA9702PW
18 V tolerant SPI 16-bit/8-bit GPI with INT
1. General descriptionThe PCA9701/PCA9702 are low power 18 V tolerant SPI General Purpose Input (GPI)
shift register designed to monitor the status of switch inputs. It generates an interrupt
when one or more of the switch inputs change state. The input level is recognized as a
HIGH when it is greater than 0.7 VDD and as a LOW when it is less than 0.4 VDD
(minimum threshold of 2 V at 5 V node). The PCA9701 can monitor up to 16 switch inputs
and the PCA9702 can monitor up to 8 switch inputs.
The falling edge of the CS pin samples the input port status and clears the interrupt. When
CS is LOW, the rising edge of the SCLK loads the shift register and shifts the value out of
the shift register. The serial input is sampled on the falling edge of SCLK.
Each of the input ports has a 18 V breakdown ESD protection circuit. When used with a
series resistor (minimum 100 k), the input can connect to a 12 V battery and support
double battery, reverse battery, 27 V jump start and 40 V load dump conditions in
automotive applications. Higher voltages can be tolerated on the inputs depending on the
series resistor used to limit the input current.
With both the high breakdown voltage and high ESD, these devices are useful for both
automotive (AEC-Q100 compliance available) and mobile applications.
The PCA9703/PCA9704 are new pin compatible devices for the PCA9701/PCA9702
which have an interrupt masking feature allowing selected inputs to not generate
interrupts and provides higher ground offset of 0.55 VDD (minimum of 2.5 V at 5 V node)
with minimum hysteresis of 0.05 VDD (minimum of 225 mV at 5 V node).
2. Features and benefits 16 general purpose input ports (PCA9701) or 8 general purpose input ports
(PCA9702) 18 V tolerant input ports with 100 k external series resistor Input LOW threshold 0.4 VDD with minimum of 2 V at VDD =4.5V Open-drain interrupt output Interrupt enable pin (INT_EN) disables interrupt output VDD range: 2.5 V to 5.5V IDD is very low 2.5 A maximum SPI serial interface with speeds up to 5 MHz AEC-Q100 compliance available ESD protection exceeds 8 kV HBM per JESD22-A114, 350 V MM per AEC-Q100, and
1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
Rev. 6 — 14 December 2011 Product data sheet
NXP Semiconductors PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT Operating temperature range: 40Cto +125C PCA9701 offered in SO24, TSSOP24 and HWQFN24 packages PCA9702 offered in TSSOP16 package
3. Applications Body control modules Switch monitoring Industrial equipment Cellular telephones Emergency lighting SBC wake pin extension
4. Ordering information[1] PCA9701PW/Q900 is AEC-Q100 compliant. Contact i2c.support for PPAP.
Table 1. Ordering informationPCA9701D PCA9701D SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
PCA9701HF 9701 HWQFN24 plastic thermal enhanced very very thin quad flat package; leads; 24 terminals; body 44 0.75 mm
SOT994-1
PCA9701PW PCA9701PW TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
PCA9701PW/Q900[1] PCA9701/Q TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
PCA9702PW PCA9702 TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
NXP Semiconductors PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
5. Block diagramNXP Semiconductors PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
6. Pinning information
6.1 PinningNXP Semiconductors PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
6.2 Pin description[1] HWQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
Table 2. Pin descriptionSDOUT 1 22 1 output 3-state serial data output; normally high-impedance
INT 2 23 2 output open-drain interrupt output (active LOW)
INT_EN 3 24 3 input interrupt output enable
1 = interrupt is enabled
0 = interrupt is disabled and high-impedance
IN0 4 1 4 input input port0
IN1 5 2 5 input input port1
IN2 6 3 6 input input port2
IN3 7 4 7 input input port3
IN4 8 5 9 input input port4
IN5 9 6 10 input input port5
IN6 10 7 11 input input port6
IN7 11 8 12 input input port7
VSS 12 9[1] 8 ground ground supply
IN8 13 10 - input input port8
IN9 14 11 - input input port9
IN10 15 12 - input input port10
IN11 16 13 - input input port11
IN12 17 14 - input input port12
IN13 18 15 - input input port13
IN14 19 16 - input input port14
IN15 20 17 - input input port15 21 18 13 input chip select (active LOW)
SCLK 22 19 14 input serial input clock
SDIN 23 20 15 input serial data input (20 A pull-down)
VDD 24 21 16 supply supply voltage
NXP Semiconductors PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
7. Functional descriptionPCA9701 is a 16-bit General Purpose Input (GPI) with an open-drain interrupt output
designed to monitor switch status. By putting an external 100 k series resistor at the
input port, the device allows the input to tolerate momentary double 12 V battery, reverse
battery, 27 V jump start or 40 V load dump conditions. The interrupt output is asserted
when an input port status changes. The open-drain interrupt output is enabled when
INT_EN is HIGH and disabled when INT_EN is LOW. The input port status is accessed
via the 4-wire SPI interface. The PCA9702 is the 8-bit version of the PCA9701.
Multiple PCA9701 or PCA9702 devices can be serially connected for monitoring a large
number of switches by connecting the SDOUT of one device to the SDIN of the next
device. SCLK and CS must be common among all devices and interrupt outputs may be
tied together. No external logic is necessary because all the devices’ interrupt outputs are
open-drain that function as ‘wired-AND’ and can simply be connected together to a single
pull-up resistor.
7.1 SPI bus operationThe PCA9701 or PCA9702 interfaces with the controller via the 4-wire SPI bus that is
comprised of the following signals: chip select (CS), serial clock (SCLK), serial data in
(SDIN), and serial data out (SDOUT). To access the device, the controller asserts CS
LOW, then sends SCLK and SDIN. When reading/writing is complete, the controller
de-asserts CS. See Figure 6 for register access timing.
7.1.1 CS - chip selectThe CS pin is the device chip select and is an active LOW input. The falling edge of CS
captures the input port status in the input status register. If the interrupt output is asserted,
the falling edge of CS will clear the interrupt. When CS is LOW, the SPI interface is active.
When CS is HIGH, the SPI interface is disabled.
7.1.2 SCLK - serial clock inputSCLK is the serial clock input to the device. It should be LOW and remain LOW during the
falling and rising edge of CS. When CS is LOW, the first rising edge of SCLK parallel
loads the shift register from the input. The subsequent rising edges on SCLK serially shifts
data out from the shift register. The falling edge of SCLK samples the data on SDIN.
7.1.3 SDIN - serial data inputSDIN is the serial data input port. The data is sampled into the shift register on the falling
edge of SCLK. SDIN is only active when CS is LOW. This input has a 20 A pull-down
current source.
7.1.4 SDOUT - serial data outputSDOUT is the serial data output signal. SDOUT is high-impedance when CS is HIGH and
switches to low-impedance after CS goes LOW. When CS is LOW, after the first rising
edge of SCLK the most significant bit in the shift register is presented on SDOUT.
Subsequent rising edges of SCLK shift the remaining data from the shift register onto
SDOUT.
NXP Semiconductors PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
7.1.5 Register access timingFigure 6 shows the waveforms of the device operation. Initially CS is HIGH and SCLK is
LOW. On the falling edge of CS, input port status, DATA[n:0] is captured into the input
status register, and subsequently the first rising edge of SCLK parallel loads the shift
register. The falling edge of SCLK samples the data on the SDIN. The MSB from the shift
register is valid and available on the SDOUT after the first rising edge of SCLK.
7.2 Interrupt outputINT is the open-drain interrupt output and is active LOW. A pull-up resistor of
approximately 10 k is recommended. The interrupt output is asserted when the input
status is changed, and is cleared on the falling edge of CS or when the input port status
matches the input status register. When there are multiple devices, the INT outputs may
be tied together to a single pull-up.
Table 3 illustrates the state of the interrupt output versus the state of the input port and
input status register. The interrupt output is asserted when the input port and input status
register differ.
NXP Semiconductors PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT[1] Input status register is the value or content of the D flip-flops.
[2] Logic states shown for INT pin assumes 10 k pull-up resistor.
7.3 General Purpose InputsThe General Purpose Inputs (GPI) are designed to behave like a typical input in the 0 V to
5.5 V range, but are also designed to have low leakage currents at elevated voltages. The
input structure allows for elevated voltages to be applied through a series resistor. The
series resistor is required when the input voltage is above 5.5 V. The series resistor is
required for two reasons: first, to prevent damage to the input avalanche diode, and
second, to prevent the ESD protection circuitry from creating an excessive current flow.
The ESD protection circuitry includes a latch-back style device, which provides excellent
ESD protection during assembly or typical 5.5 V applications. The series resistor limits the
current flowing into the part and provides additional ESD protection. The limited current
prevents the ESD latch-back device from latching back to a low voltage, which would
cause excessive current flow and damage the part.
The minimum required series resistance for applications with input voltages above 5.5V
is 100 k. For applications requiring an applied voltage above 27 V, Equation 1 is
recommended to determine the series resistor. Failure to include the appropriate input
series resistor may result in product failure and will void the warranty.
(1)
The series resistor should be placed physically as close as possible to the connected
input to reduce the effective node capacitance. The input response time is effected by the
RC time constant of the series resistor and the input node capacitance.
Table 3. Interrupt output function truth table= HIGH; L= LOW; X= don’t care L H H L L L H H X H
NXP Semiconductors PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
7.3.1 VIL, VIH and switching pointsA minimum LOW threshold of 2.0 V is guaranteed for the logical switching points for the
inputs. See Figure 7 for details.
The VIL is specified as a maximum of 0.40 VDD and is 2.0 V at 4.5V VDD. This means
that if the user applies 2.0 V or less to the input (with VDD= 4.5 V), or as the voltage
passes this threshold, they will always see a LOW.
The VIH is specified as a minimum of 0.7 VDD. This means that if the user applies 3.15V
or more to the input (with VDD= 4.5 V), or as the voltage passes this threshold, they will
always see a HIGH.
NXP Semiconductors PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
8. Application design-in information
8.1 General application
8.2 Automotive applicationSupports:
12 V battery (8 V to 16V)
Double battery (16 V to 32V)
Reverse battery (8 V to 16V)
Jump start (27 V for 60 seconds)
Load dump (40V)
NXP Semiconductors PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
8.2.1 SBC wake port extension with cyclic biasingSystem Basis Chips (SBC) offer many functions needed for in-vehicle networking
solutions. Some of the features built into SBC are:
Transceivers (HS-CAN, LIN 2.0)
Scalable voltage regulators
Watchdog timers; wake-up function
Fail-safe function
For more information on SBC, refer to
http:///index.html#/pip/pip=[pfp=53482]|pp=[t=pfp,i=53482].
8.2.1.1 UJA106x with PCA9701, standby PCA970x fits to SBC UJA106x and UJA107xA family
PCA970x can be powered by V1 of SBC
Extends the SBC with 8/16 additional wake inputs
C can be set to stop-mode during standby to save ECU standby current. SBC with
GPI periodically monitors the wake inputs
Cyclic bias via V3
Very low system current consumption even with clamped switches
NXP Semiconductors PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
8.2.1.2 UJA106x with PCA9701, sleep Very low quiescent system current (50 A) due to disabled C and cyclically biasing
of switches
Wake-up upon change of switches or upon bus traffic (CAN and LIN)
PCA970x supplied out of cyclically biased transistor regulator
NXP Semiconductors PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
8.2.1.3 UJA107xA with PCA9701, standby UJA107xA SBC provides WBIAS pin for cyclic biasing of the inputs
Compatible with UJA107xA based ASSPs
8.2.2 Application examples including switches to batteryNXP Semiconductors PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
9. Limiting values[1] With GPI external series resistors, the inputs support double battery, reverse battery and load dump conditions. During double battery or
load dump the input pin will drain slightly higher leakage current until the input drops to 18 V. For more detail of leakage current
specification, please refer to Table 5 “Static characteristics”. See Section 7.3 for series resistor requirements.
[2]n= 15 for PCA9701; n= 7 for PCA9702.
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
Tamb= 40 Cto+125 C, unless otherwise specified.
VDD supply voltage 0.5 +6.0 V input current IN[n:0] pins with series resistor
and VI >5.5V,
[1][2] -350 A input voltage GPI pins IN[n:0]; no series resistor [1][2] 0.5 +6 V
SPI pins 0.5 +6 V
Tstg storage temperature 65 +150 C
Tj(max) maximum junction temperature operating - 125 C
