PCA9703PW ,18 V tolerant SPI 16-bit GPI with maskable INTGeneral descriptionThe PCA9703 is a low power 18 V tolerant SPI General Purpose Input (GPI) shift r ..
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PCA9703PW
18 V tolerant SPI 16-bit GPI with maskable INT
1. General descriptionThe PCA9703 is a low power 18 V tolerant SPI General Purpose Input (GPI) shift register
designed to monitor the status of switch inputs. It generates an interrupt when one or
more of the switch inputs change state but allows selected inputs to not generate
interrupts using the interrupt masking feature. The input level is recognized as a HIGH
when it is greater than 0.8 VDD and as a LOW when it is less than 0.55 VDD (minimum
LOW threshold of 2.5 V at 5 V node). The PCA9703 can monitor up to 16 switch inputs.
The falling edge of the CS pin samples the input port status and clears the interrupt. When
CS is LOW, the rising edge of the SCLK loads the shift register and shifts the value out of
the shift register. The serial input is sampled on the falling edge of SCLK. The contents of
the shift register are loaded into the interrupt mask register of the device on the rising
edge of CS.
Each of the input ports has a 18 V breakdown ESD protection circuit, which dumps the
ESD/overvoltage current to ground. When used with a series resistor (minimum 100 k),
the input can connect to a 12 V battery and support double battery, reverse battery, 27V
jump start and 40 V load dump conditions in automotive applications. Higher voltages can
be tolerated on the inputs depending on the series resistor used to limit the input current.
The INT_EN pin is used to both enable the GPI pins and to enable the INT output pin to
minimize battery drain in cyclically supplied pull-up or pull-down applications. The SDIN
pull-down prevents floating nodes when the device is used in daisy-chain applications.
With both the high breakdown voltage and high ESD, this device is useful for both
automotive (AEC-Q100 compliance available) and mobile applications.
2. Features and benefits 16 general purpose input ports 18 V tolerant input ports with 100 k external series resistor Input LOW threshold 0.55 VDD with minimum of 2.5 V at VDD =4.5V Input hysteresis 0.04 VDD with minimum of 180 mV at VDD =4.5V Open-drain interrupt output Interrupt enable pin (INT_EN) disables GPI pins and interrupt output Interrupt-masking feature allows no interrupt generation from selected inputs VDD range: 4.5 V to 5.5V IDD is very low 2.5 A maximum SPI serial interface with speeds up to 5 MHz SPI supports daisy-chain connection for large switch numbers AEC-Q100 compliance available
PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT
Rev. 3 — 17 March 2014 Product data sheet
NXP Semiconductors PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT ESD protection exceeds 5 kV HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Operating temperature range: 40Cto +125C Offered in TSSOP24 and HWQFN24 packages
3. Applications Automotive Body control modules Electronic control units (for example, for body controller) Switch monitoring SBC wake pin extension Industrial equipment Cellular telephones Emergency lighting
4. Ordering information[1] PCA9703PW/Q900 is AEC-Q100 compliant. Contact i2c.support for PPAP.
Table 1. Ordering information
NXP Semiconductors PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT
5. Block diagram
6. Pinning information
6.1 PinningNXP Semiconductors PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT
6.2 Pin description[1] HWQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
Table 2. Pin description
NXP Semiconductors PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT
7. Functional descriptionPCA9703 is a 16-bit General Purpose Input (GPI) with an open-drain interrupt output
designed to monitor switch status. By putting an external 100 k series resistor at the
input port, the device allows the input to tolerate momentary double 12 V battery, reverse
battery, 27 V jump start or 40 V load dump conditions. The interrupt output is asserted
when an input port status changes, the input is not masked and the interrupt output is
enabled. The open-drain interrupt output is enabled when INT_EN is HIGH and disabled
when INT_EN is LOW. The INT_EN also enables the GPI pins when it is HIGH. In
cyclically supplied pull-up or pull-down applications, the GPI pull-ups or pull-downs should
be active before the INT_EN is taken HIGH and the INT output should only be sampled
after transient conditions have settled. Additionally, interrupts can be disabled in software
by using the interrupt mask feature. The input port status is accessed via the 4-wire SPI
interface.
Upon power-up, the power-up reset cell clears all the registers, resulting in all zeros in
both the input status register and the interrupt mask register. Since a zero in the interrupt
mask register masks the interrupt from that pin, there will not be any interrupts generated.
After power-up it is necessary to access the PCA9703 through the SPI pins in order to
activate the interrupt for any GPI pins. When the PCA9703 is read over the SPI wires, the
input conditions are clocked into the input status register on the CS falling edge. Since the
inputs and the input status register now match, no interrupt is generated and any
pre-existing interrupt is cleared. The input status register data is parallel loaded into the
shift register on the first rising edge of the SCLK. The serial input data is captured on the
opposite clock edge so that there is a 1 ⁄2 clock cycle hold time. The set-up time is
diminished by the propagation time so the SCLK falling edge to rising edge must be long
enough to provide sufficient set-up time. Successive clock cycles on the SCLK pin clock
the data out of the PCA9703 and new data from the SDIN into the shift register. There is
no limit to the number of clock cycles that can be applied with the CS LOW, however
sufficient clock cycles should be used to both shift out all of the GPI data and shift in the
new interrupt mask data to the correct position with the MSB first before the CS rising
edge.
For cyclic switch bias applications the switch bias should be applied first, then after the
input voltage is settled the general purpose inputs are switched on by taking the INT_EN
HIGH. This also enables the interrupt output, which will only indicate an interrupt if the GPI
data does not match the input status register on a bit that is enabled by the interrupt mask
register value. If an interrupt is generated, the pull-up or pull-down source should remain
active and the INT_EN should remain active and the SPI pins are used to update the input
status register and read the data out. They are also used to store the new interrupt mask
on the rising edge of CS. After the SPI transaction is complete the INT_EN is taken LOW
to turn the inputs off and disable the INT output. Then the GPI pull-ups or pull-downs can
be turned off. The GPI pins are specifically designed so that any ESD/overstress current
flows to ground, not VDD. They are also specifically designed so that if the input voltage
returns to the same value after pull-up or pull-down bias cycling as before the input pull-up
or pull-down bias cycling, before the input is enabled it will be detected as the same state.
If the Input Status register is read when INT_EN is LOW, the input state at the INT_EN
transition will be output regardless of the actual input levels since the GPI pins are turned
off.
NXP Semiconductors PCA9703
18 V tolerant SPI 16-bit GPI with maskable INTIf the VDD falls below the 4.5 V minimum specified supply voltage, the input threshold will
move down since they are a function of the VDD voltage. The input status register and the
interrupt mask register retain their values to below VDD= 2.0 V and power-down can only
be used to generate a power-up reset if the VDD falls below 0.2 V before returning to the
operating range.
Multiple PCA9703 devices can be serially connected for monitoring a large number of
switches by connecting the SDOUT of one device to the SDIN of the next device. SCLK
and CS must be common among all devices and interrupt outputs may be tied together.
No external logic is necessary because all the devices’ interrupt outputs are open-drain
that function as ‘wired-AND’ and can simply be connected together to a single pull-up
resistor.
7.1 SPI bus operationThe PCA9703 interfaces with the controller via the 4-wire SPI bus that is comprised of the
following signals: chip select (CS), serial clock (SCLK), serial data in (SDIN), and serial
data out (SDOUT). To access the device, the controller asserts CS LOW, then sends
SCLK and SDIN. When reading is complete and the interrupt mask data is in place, the
controller de-asserts CS. See Figure 4 for register access timing.
7.1.1 CS - chip selectThe CS pin is the device chip select and is an active LOW input. The falling edge of CS
captures the input port status in the input status register. If the interrupt output is asserted,
the falling edge of CS will clear the interrupt. When CS is LOW, the SPI interface is active.
When CS transitions HIGH the interrupt mask is stored and when CS is HIGH, the SPI
interface is disabled.
7.1.2 SCLK - serial clock inputSCLK is the serial clock input to the device. It should be LOW and remain LOW during the
falling and rising edge of CS. When CS is LOW, the first rising edge of SCLK parallel
loads the shift register from the input status register. The subsequent rising edges on
SCLK serially shifts data out from the shift register. The falling edge of SCLK samples the
data on SDIN.
7.1.3 SDIN - serial data inputSDIN is the serial data input port. The data is sampled into the shift register on the falling
edge of SCLK. SDIN is only active when CS is LOW. This input has a 20 A pull-down
current source to prevent the SDIN node from floating when CS is HIGH.
7.1.4 SDOUT - serial data outputSDOUT is the serial data output signal. SDOUT is high-impedance when CS is HIGH and
switches to low-impedance after CS goes LOW. When CS is LOW, after the first rising
edge of SCLK the most significant bit in the shift register is presented on SDOUT.
Subsequent rising edges of SCLK shift the remaining data from the shift register onto
SDOUT.
NXP Semiconductors PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT
7.1.5 Register access timingFigure 4 shows the waveforms of the device operation. Initially CS is HIGH and SCLK is
LOW. On the falling edge of CS, input port status, DATA[n:0] is captured into the input
status register, and subsequently the first rising edge of SCLK parallel loads the shift
register. The falling edge of SCLK samples the data on the SDIN. The MSB from the shift
register is valid and available on the SDOUT after the first rising edge of SCLK.
7.1.6 Software reset operationSoftware reset will be activated by writing all zeroes into the shift register. This is identical
to having an interrupt mask value of 0X00. Such an operation will reset the device, clear
the input status register to zero and set the interrupt output to HIGH (no interrupt).
7.2 Interrupt outputINT is the open-drain interrupt output and is active LOW. A pull-up resistor of
approximately 10 k is recommended.
A user-defined interrupt mask bit pattern is shifted into the shift register via SDIN. The
value of bits in the mask pattern will determine which input pins will cause an interrupt.
Any bit that is = 0 will disable the input pin corresponding to that bit position from
generating an interrupt. Interrupts will be enabled for bits having value = 1. The mask bit
pattern is not automatically aligned with the desired input pins. It is the responsibility of the
programmer to shift the correct number of (mask) bits to the correct positions into the shift
NXP Semiconductors PCA9703
18 V tolerant SPI 16-bit GPI with maskable INTregister. The interrupt mask bit pattern must be positioned into the shift register prior to the
CS rising edge. Misaligned mask pattern will result in unexpected activation of the
interrupt signal.
The interrupt output is asserted when the input status is changed, and the interrupt mask
bit corresponding to the input pin that caused the change is unmasked (bit value= 1), and
is cleared on the falling edge of CS or when the input port status matches the input status
register. When there are multiple devices, the INT outputs may be tied together to a single
pull-up.
Table 3 illustrates the state of the interrupt output versus the state of the input port and
input status register. The interrupt output is asserted when the input port and input status
register differ.
[1] Input status register is the value or content of the D flip-flops.
[2] Logic states shown for INT pin assumes 10 k pull-up resistor.
7.3 Interrupt enableINT_EN is the interrupt output enable input and the general purpose input enable input. It
is an active HIGH input. When the INT_EN pin is LOW the GPI pins are turned off and the
input state is saved to minimize power loss when the input pull-ups or pull-downs are
cycled and the INT output is disabled. The cycled pull-ups or pull-downs should be active
sufficiently long before the INT_EN is taken active that the GPI pin voltage is completely
settled to prevent false or transient interrupt signals.
7.4 General Purpose InputsThe General Purpose Inputs (GPI) are designed to behave like a typical input in the 0 V to
5.5 V range, but are also designed to have low leakage currents at elevated voltages. The
input structure allows for elevated voltages to be applied through a series resistor. The
series resistor is required when the input voltage is above 5.5 V. The series resistor is
required for two reasons: first, to prevent damage to the input avalanche diode, and
second, to prevent the ESD protection circuitry from creating an excessive current flow.
The ESD protection circuitry includes a latch-back style device, which provides excellent
ESD protection during assembly or typical 5.5 V applications. The series resistor limits the
current flowing into the part and provides additional ESD protection. The limited current
prevents the ESD latch-back device from latching back to a low voltage, which would
cause excessive current flow and damage the part when the input voltage is above 5.5V.
Table 3. Interrupt output function truth table= HIGH; L= LOW; X= don’t care
NXP Semiconductors PCA9703
18 V tolerant SPI 16-bit GPI with maskable INTThe minimum required series resistance for applications with input voltages above 5.5V
is 100 k. For applications requiring an applied voltage above 27 V, Equation 1 is
recommended to determine the series resistor. Failure to include the appropriate input
series resistor may result in product failure and will void the warranty.
(1)
The series resistor should be place physically as close as possible to the connected input
to reduce the effective node capacitance. The input response time is effected by the RC
time constant of the series resistor and the input node capacitance.
7.4.1 VIL, VIH and switching pointsA minimum LOW threshold of 2.5 V is guaranteed for the logical switching points for the
inputs. See Figure 5 for details.
The VIL is specified as a maximum of 0.55 VDD and is 2.5 V at 4.5V VDD. This means
that if the user applies 2.5 V or less to the input (with VDD= 4.5 V), or as the voltage
passes this threshold, they will always see a LOW.
The VIH is specified as a minimum of 0.8 VDD. This means that if the user applies 3.6V
or more to the input (with VDD= 4.5 V), or as the voltage passes this threshold, they will
always see a HIGH.
Hysteresis minimum is specified as 180 mV at VDD= 4.5 V. This means there will always
be at least 180 mV of difference between the LOW threshold and HIGH threshold to help
prevent oscillations and handle higher noise.
NXP Semiconductors PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT
8. Application design-in information
8.1 General application
8.2 Automotive applicationSupports:
12 V battery (8 V to 16V)
Double battery (16 V to 32V)
Reverse battery (8 V to 16V)
Jump start (27 V for 60 seconds)
Load dump (40V)
NXP Semiconductors PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT
8.2.1 SBC wake port extension with cyclic biasingSystem Basis Chips (SBC) offer many functions needed for in-vehicle networking
solutions. Some of the features built into SBC are:
Transceivers (HS-CAN, LIN 2.0)
Scalable voltage regulators
Watchdog timers; wake-up function
Fail-safe function
For more information on SBC, refer to
/products/interface_and_connectivity/system_basis_chips/.
8.2.1.1 UJA106x with PCA9703, standby PCA9703 fits to SBC UJA106x and UJA107xA family
PCA9703 can be powered by V1 of SBC
Extends the SBC with 16 additional wake inputs
C can be set to stop-mode during standby to save ECU standby current. SBC with
GPI periodically monitors the wake inputs
Cyclic bias via V3
Very low system current consumption even with clamped switches
Interrupt enable control via V2
NXP Semiconductors PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT
8.2.1.2 UJA107xA with PCA9703, standby and sleep UJA107xA SBC provides WBIAS pin for cyclic biasing of the inputs
Compatible with UJA107xA based ASSPs
NXP Semiconductors PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT
8.2.2 Application examples including switches to battery
9. Limiting values[1] With GPI external series resistors, the inputs support double battery, reverse battery and load dump conditions. During double battery or
load dump the input pin will drain slightly higher leakage current until the input drops to 18 V. For more detail of leakage current
specification, please refer to Table 5 “Static characteristics”. See Section 7.4 for series resistor requirements.
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
Tamb= 40 Cto+125 C, unless otherwise specified.
NXP Semiconductors PCA9703
18 V tolerant SPI 16-bit GPI with maskable INT
10. Static characteristics[1] VDD must be lowered to 0.2 V for at least 5 s in order to reset device.
[2] Minimum VIL is 2.5 V at VDD =4.5V.
[3] Minimum Vhys is 180 mV at VDD =4.5V.
[4] For GPI pin voltages > 5.5 V, see Section 7.4.
Table 5. Static characteristicsVDD= 4.5 V to 5.5 V; VSS =0V; Tamb= 40Cto +125 C; unless otherwise specified.
