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PCD8582D-2-PCD8582D-2P-PCF8582C-2P-PCF8582E-2-PCF8582E--2-PCF8582E-2P-PCF8582E-2T
256 x 8-bit CMOS EEPROMS with I2C-bus interface
December 1994 2
Philips Semiconductors Product specification
256 x 8-bit CMOS EEPROMS
with I2 C-bus interface PCX8582X-2 Family
FEATURES Low power CMOS maximum active current 2.0 mA maximum standby current 10 μA (at6.0V),
typical4μA Non-volatile storage of 2-Kbits organized as 256× 8-bits Single supply with full operation down to 2.5V On-chip voltage multiplier Serial input/output I2C-bus Write operations byte write mode 8-byte page write mode
(minimizes total write time per byte) Read operations sequential read random read Internal timer for writing (no external components) Power-on reset High reliability by using a redundant storage code Endurance >500 k E/W-cycles at Tamb=22°C40 years non-volatile data retention time (typ.) Pin and address compatible to PCX8570, PCF8571, PCF8572 and PCF8581 PCX8494X-2, PCX8598X-2 -Family.
DESCRIPTIONThe PCX8582X-2 is a 2-Kbit (256× 8-bit) floating gate
electrically erasable programmable read only memory
(EEPROM). By using an internal redundant storage code
it is fault tolerant to single bit errors. This feature
dramatically increases reliability compared to conventional
EEPROM memories.
Power consumption is low due to the full CMOS
technology used. The programming voltage is generated
on-chip, using a voltage multiplier.
As data bytes are received and transmitted via the serial
I2C-bus, a package using eight pins is sufficient. Up to
eight PCX8582X-2 devices may be connected to the
I2C-bus. Chip select is accomplished by three address
inputs (A0, A1, A2).
Timing of the ERASE/WRITE cycle is carried out
internally, thus no external components are required. Pin7
(PTC) must be connected to either VDD or left open-circuit.
There is an option of using an external clock for timing the
length of an ERASE/WRITE cycle.
QUICK REFERENCE DATA
December 1994 3
Philips Semiconductors Product specification
256 x 8-bit CMOS EEPROMS
with I2 C-bus interface PCX8582X-2 Family
ORDERING INFORMATION
DEVICE SELECTION
Table 1 Device selection code
Note The MSB b7 is sent first.
Table 2 Endurance and data retention guarantees
Note At the time of publication of this data sheet the statistical history was not yet sufficient to guarantee 1000000000 E/W
cycle performance for these types.
December 1994 4
Philips Semiconductors Product specification
256 x 8-bit CMOS EEPROMS
with I2 C-bus interface PCX8582X-2 Family
BLOCK DIAGRAM
December 1994 6
Philips Semiconductors Product specification
256 x 8-bit CMOS EEPROMS
with I2 C-bus interface PCX8582X-2 Family
CHARACTERISTICSPCF8582C-2: VDD=2.5to6.0 V; VSS=0 V; Tamb= −40to +85 °C; unless otherwise specified.
PCD8582D-2: VDD=3.0to6.0 V; VSS=0 V; Tamb= −25to +70 °C; unless otherwise specified.
PCF8582E-2: VDD=4.5to5.5 V; VSS=0 V; Tamb= −40to +85 °C; unless otherwise specified.
PCA8582F-2: VDD=4.5to5.5 V; VSS=0 V; Tamb= −40to +125 °C; unless otherwise specified.
December 1994 7
Philips Semiconductors Product specification
256 x 8-bit CMOS EEPROMS
with I2 C-bus interface PCX8582X-2 Family
WRITE CYCLE LIMITSSelection of the chip address is achieved by connecting the A0, A1 and A2 inputs to either VSS or VDD.
December 1994 8
Philips Semiconductors Product specification
256 x 8-bit CMOS EEPROMS
with I2 C-bus interface PCX8582X-2 Family
I2C-BUS PROTOCOLThe I2C-bus is for 2-way, 2-line communication between
different ICs or modules. The serial bus consists of two
bidirectional lines: one for data signals (SDA), and one for
clock signals (SCL).
Both the SDA and SCL lines must be connected to a
positive supply voltage via a pull-up resistor.
The following protocol has been defined: Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as
control signals.
The following bus conditions have been defined:
Bus not busy: both data and clock lines remain HIGH. Start data transfer: a change in the state of the dataline, from HIGH-to-LOW, while the clock is HIGH,
defines the start condition.
Stop data transfer: a change in the state of the dataline, from LOW-to-HIGH, while the clock is HIGH,
defines the stop condition.
Data valid: the state of the data line represents validdata when, after a start condition, the data line is stable
for the duration of the HIGH period of the clock signal.
There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and
terminated with a stop condition; the number of the data
bytes, transferred between the start and stop conditions is
limited to seven bytes in the ERASE/WRITE mode and
eight bytes in the PAGE ERASE/WRITE mode. Data
transfer is unlimited in the READ mode. The information is
transmitted in bytes and each receiver acknowledges with
a ninth bit.
Within the I2C-bus specifications a low-speed mode (2 kHz
clock rate) and a high speed mode (100 kHz clock rate)
are defined.
The PCX8582X-2 operates in both modes.
By definition a device that sends a signal is called a
‘transmitter’, and the device which receives the signal is
called a ‘receive’. The device which controls the signal is
called the ‘master’. The devices that are controlled by the
master are called ‘slaves’.
Each byte is followed by one acknowledge bit. This
acknowledge bit is a HIGH level, put on the bus by the
transmitter. The master generates an extra acknowledge
related clock pulse. The slave receiver which is addressed
is obliged to generate an acknowledge after the reception
of each byte.
The master receiver must generate an acknowledge after
the reception of each byte that has been clocked out of the
slave transmitter.
The device that acknowledges has to pull down the SDA
line during the acknowledge clock pulse in such a way that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse.
Set-up and hold times must be taken into account. A
master receiver must signal an end of data to the slave
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event
the transmitter must leave the data line HIGH to enable the
master generation of the stop condition.
DEVICE ADDRESSINGFollowing a start condition the bus master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identifier
(see Fig.3). For the PCX8582X-2 this is fixed as 1010.
The next three significant bits address a particular device.
A system could have up to eight PCX8582X-2 devices on
the bus. The eight addresses are defined by the state of
the A0, A1 and A2 inputs.
The last bit of the slave address defines the operation to
be performed. When set to logic 1 a read operation is
selected.
Address bits must be connected to either VDD or VSS.
December 1994 9
Philips Semiconductors Product specification
256 x 8-bit CMOS EEPROMS
with I2 C-bus interface PCX8582X-2 Family
WRITE OPERATIONS
Byte/word writeFor a write operation the PCX8582X-2 requires a second
address field. This address field is a word address
providing access to the 256 words of memory. Upon
receipt of the word address the PCX8582X-2 responds
with an acknowledge and awaits the next eight bits of data,
again responding with an acknowledge. Word address is
automatically incremented. The master can now terminate
the transfer by generating a stop condition or transmit up
to six more bytes of data and then terminate by generating
a stop condition.
After this stop condition the ERASE/WRITE cycle starts
and the bus is free for another transmission. Its duration is ms (typ.) per byte.
During the ERASE/WRITE cycle the slave receiver does
not send an acknowledge bit if addressed via the I2 C-bus.
PAGE WRITEThe PCX8582X-2 is capable of an eight-byte page write
operation. It is initiated in the same manner as the byte
write operation. The master can transmit eight data bytes
within one transmission. After receipt of each byte the
PCX8582X-2 will respond with an acknowledge. The
typical ERASE/WRITE time in this mode is×7ms=63 ms.
After the receipt of each data byte the three low order bits
of the word address are internally incremented. The high
order five bits of the address remain unchanged. If the
master transmits more than eight bytes prior to generating
the stop condition, no acknowledge will be given on the
ninth (and following) data bytes and the whole
transmission will be ignored. As in the byte write operation,
all inputs are disabled until completion of the internal write
cycles.
December 1994 10
Philips Semiconductors Product specification
256 x 8-bit CMOS EEPROMS
with I2 C-bus interface PCX8582X-2 Family
