PCF2113DH ,LCD controller/driverFEATURES • MUX rates 1 : 18 (for normal operation) and 1 : 2(for icon-only mode)• Single-chip LCD c ..
PCF2113DH ,LCD controller/driverLIMITING VALUES8.8 Registers14 HANDLING8.9 Busy Flag15 DC CHARACTERISTICS8.10 Address Counter (AC)1 ..
PCF2113DH ,LCD controller/driverFeaturesn Single-chip LCD controller/drivern 2-line display of up to 12 characters + 120 icons, or ..
PCF2113DH/F4 ,LCD controllers/drivers
PCF2113DU/F2 ,LCD controller/driverapplicationsingle chip, including on-chip generation of LCD bias2• 4 or 8-bit parallel bus and 2-wi ..
PCF2113DU/F4 ,PCF2113x; LCD controllers/drivers
PGA205BU ,Programmable Gain INSTRUMENTATION AMPLIFIERFEATURES DESCRIPTIONThe PGA204 and PGA205 are low cost, general pur-l DIGITALLY PROGRAMMABLE GAIN:p ..
PGA206PA ,High-Speed Programmable Gain INSTRUMENTATION AMPLIFIERPGA207PGA206®PGA206PGA207High-Speed Programmable GainINSTRUMENTATION AMPLIFIER
PGA206UA ,High-Speed Programmable Gain INSTRUMENTATION AMPLIFIERPGA207PGA206®PGA206PGA207High-Speed Programmable GainINSTRUMENTATION AMPLIFIER
PGA206UAG4 ,High-Speed Programmable Gain Instrumentation Amplifier 16-SOIC PGA207PGA206®PGA206PGA207High-Speed Programmable GainINSTRUMENTATION AMPLIFIER
PGA207UA ,High-Speed Programmable Gain INSTRUMENTATION AMPLIFIERPGA207PGA206®PGA206PGA207High-Speed Programmable GainINSTRUMENTATION AMPLIFIER
PGA207UAE4 ,High-Speed Programmable Gain Instrumentation Amplifier 16-SOIC FEATURES DESCRIPTIONThe PGA206 and PGA207 are digitally programmablel DIGITALLY PROGRAMMABLE GAINS: ..
PCF2113DH-PCF2113DU/F2
LCD controller/driver
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
CONTENTS FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING PIN FUNCTIONS FUNCTIONAL DESCRIPTION
8.1 LCD supply voltage generator
8.2 Programming ranges
8.3 LCD bias voltage generator
8.4 Oscillator
8.5 External clock
8.6 Power-on reset
8.7 Power-down mode
8.8 Registers
8.9 Busy Flag
8.10 Address Counter (AC)
8.11 Display Data RAM (DDRAM)
8.12 Character Generator ROM (CGROM)
8.13 Character Generator RAM (CGRAM)
8.14 Cursor control circuit
8.15 Timing generator
8.16 LCD row and column drivers
8.17 Reset function INSTRUCTIONS
9.1 Clear display
9.2 Return home
9.3 Entry mode set
9.3.1 I/D
9.3.2 S
9.4 Display control (and partial power-down mode)
9.4.1 D
9.4.2 C
9.4.3 B
9.5 Cursor/display shift
9.6 Function set
9.6.1 DL (parallel mode only)
9.6.2 M
9.6.3 H
9.7 Set CGRAM address
9.8 Set DDRAM address
9.9 Read busy flag and address
9.10 Write data to CGRAM or DDRAM
9.11 Read data from CGRAM or DDRAM EXTENDED FUNCTION SET
INSTRUCTIONS AND FEATURES
10.1 New instructions
10.2 Icon control
10.3 IM
10.4 IB
10.5 Normal/Icon mode operation
10.6 Screen configuration
10.7 Display configuration
10.8 TC1, TC2
10.9 Set VLCD
10.10 Reducing current consumption INTERFACE TO MICROCONTROLLER
(PARALLEL INTERFACE) INTERFACE TO MICROCONTROLLER2 C-BUS INTERFACE)
12.1 Characteristics of the I2 C-bus
12.2 I2C-bus protocol
12.3 Definitions LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS TIMING CHARACTERISTICS APPLICATION INFORMATION
18.1 8-bit operation, 1-line display using internal
reset
18.2 4-bit operation, 1-line display using internal
reset
18.3 8-bit operation, 2-line display
18.4 I2 C operation, 1-line display BONDING PAD LOCATIONS PACKAGE OUTLINE SOLDERING
21.1 Introduction
21.2 Reflow soldering
21.3 Wave soldering
21.4 Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2 C COMPONENTS
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
FEATURES Single-chip LCD controller/driver 2-line display of up to 12 characters+ 120 icons,
or 1-line display of up to 24 characters+ 120 icons5×7 character format plus cursor; 5× 8 for kana
(Japanese syllabary) and user defined symbols Icon mode: reduced current consumption while
displaying icons only(1) Icon blink function On-chip: generation of LCD supply voltage, programmable by
instruction (external supply also possible) temperature compensation of on-chip generated
VLCD: −8to −12 mV/K at 5.0V
(programmable by instruction) generation of intermediate LCD bias voltages oscillator requires no external components
(external clock also possible) Display data RAM: 80 characters Character generator ROM: 240, 5×8 characters Character generator RAM: 16, 5×8 characters; characters used to drive 120 icons, 6 characters used
if icon-blink feature is used in application4or 8-bit parallel bus and 2-wireI2 C-bus interface CMOS compatible 18 row, 60 column outputs
(1) Icon mode is used to save current. When only icons
are displayed, a much lower operating voltage VLCD
can be used and the switching frequency of the LCD
outputs is reduced. In most applications it is possible
to use VDD as VLCD. Never use the voltage generator
in icon mode. MUX rates 1: 18 (for normal operation) and 1:2
(for icon-only mode) Uses common 11 code instruction set (extended) Logic supply voltage range, VDD− VSS= 1.8to 4.0V
(up to 5.5 V if external VLCD is used); chip may be driven
with two battery cells Display supply voltage range,
VLCD− VSS= 2.2to 6.5V Very low current consumption (20to 200 μA): icon mode: <25 μA power-down mode: <2.5 μA.
APPLICATIONS Telecom equipment Portable instruments Point-of-sale terminals.
GENERAL DESCRIPTIONThe PCF2113x is a low power CMOS LCD controller and
driver, designed to drive a dot matrix LCD display of 2 line 12 and 1 line by 24 characters with 5× 8 dot format.
All necessary functions for the display are provided in a
single chip, including on-chip generation of LCD bias
voltages, resulting in a minimum of external components
and lower system current consumption. The PCF2113x
interfaces to most microcontrollers via a 4 or 8-bit bus or
via the 2-wireI2 C-bus. The chip contains a character
generator and displays alphanumeric and kana
(Japanese) characters. Three character sets (A, D and E)
are currently available (see Figs 7, 8 and 9). Various other
character sets can be manufactured on request.
ORDERING INFORMATION
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
BLOCK DIAGRAM
Philips Semiconductors Product specification
LCD controller/driver PCF2113x PINNING
Notes This is the VLCD output pin, if VLCD is generated internally and has to be connected to VLCD1. If VLCD1 is generated
externally, VLCD2 has to be left open or connected to ground. This is the voltage used for the generation of LCD bias levels. This is the supply for the high voltage generator. If VLCD is generated externally, connect VDD2 to VSS.
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
Philips Semiconductors Product specification
LCD controller/driver PCF2113x PIN FUNCTIONS
Note If the 4-bit interface is used without reading out from the PCF2113x (i.e. R/W is set permanently to logic 0), the
unused ports DB0to DB3 can either be set to VSS or VDD instead of leaving them open.
Philips Semiconductors Product specification
LCD controller/driver PCF2113x FUNCTIONAL DESCRIPTION (see Fig.1)
8.1 LCD supply voltage generator
The LCD supply voltage may be generated on-chip.
The voltage generator is controlled by two internal 6-bit
registers, VA and VB. The nominal LCD operating voltage
at room temperature is given by the relationships:
VOP(nom)= [(integer valueof register)× 0.08+ 1.9]V
8.2 Programming ranges (Tref =27 °C)
Programmed value range: 1to 63.
Voltage range: 1.90to 6.84V.
Values producing more than 6.5 V at operating
temperature are not allowed. Operation above this
voltage may damage the device. When programming the
operating voltage the VLCD temperature coefficient must
be taken into account.
Values below 2.2 V are below the specified operating
range of the chip and are therefore not allowed.
Value 0 for VA and VB switches the generator off.
Usually register VA is programmed with the voltage for
character mode and register VB with the voltage for icon
mode. VB must be programmed to FF in character mode
and VA must be programmed to 00 in icon mode.
When VLCD is generated on-chip the VLCD pins should be
decoupled to VSS with a suitable capacitor. The generated
VLCD is independent of VDD and is temperature
compensated. When the generator is switched off an
external voltage may be supplied at connected pins
VLCD1,2. VLCD1,2 may be higher or lower than VDD if
external VLCD is used. If internally generated it must not
be lower than VDD and .
8.3 LCD bias voltage generator
The intermediate bias voltages for the LCD display are
also generated on-chip. This removes the need for an
external resistive bias chain and significantly reduces the
system current consumption. The optimum value of VLCD
depends on the multiplex rate, the LCD threshold voltage
(Vth) and the number of bias levels and is given by the
relationships given in Tables1 and 2. Using a 5-level bias
scheme for 1: 18 maximum rate allows VLCD<5 V for
most LCD liquids.DD 4V≤
Table 1 Optimum/maximum values for VOP (off pixels start darkening; Voff =Vth)
Table 2 Minimum values for VOP (on pixels clearly visible; Von >Vth)
8.4 Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC pin must be connected to VDD.
8.5 External clock
If an external clock is to be used this is input at the OSC
pin. The resulting display frame frequency is given by frame OSC
3072-------------=
Only in the power-down state is the clock allowed to be
stopped (OSC connected to Vss), otherwise the LCD is
frozen in a DC state.
8.6 Power-on reset
The on-chip power-on reset block initializes the chip after
power-on or power failure. This is a synchronous reset and
requires 3 OSC cycles to be executed.
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
8.7 Power-down mode
The chip can be put into power-down mode where all static
currents are switched off (no internal oscillator, no bias
level generation, all LCD-outputs are internally connected
to VSS) when PD= logic1.
During power-down, the whole chip is reset and will restart
with a clear display after power-down. Therefore, the
whole chip has to be initialized after a power-down as after
initial power- up.
The device should be put into ‘display off’ mode
(instruction ‘Display control’) before putting the chip in
power-down mode, otherwise the LCD output voltages are
not defined.
8.8 Registers
The PCF2113x has two 8-bit registers, an Instruction
Register (IR) and a Data Register (DR). The Register
Select signal (RS) determines which register will be
accessed. The instruction register stores instruction codes
such as ‘Display clear’ and ‘Cursor shift’, and address
information for the Display Data RAM (DDRAM) and
Character Generator RAM (CGRAM). The instruction
register can be written from but not read by the system
controller. The data register temporarily stores data to be
read from the DDRAM and CGRAM. When reading, data
from the DDRAM or CGRAM corresponding to the address
in the instruction register is written to the data register prior
to being read by the ‘Read data’ instruction.
8.9 Busy Flag
The Busy Flag indicates the free/busy status of the
PCF2113x. Logic 1 indicates that the chip is busy and
further instructions will not be accepted. The Busy Flag is
output to pin DB7 when RS= logic 0 and R/W= logic1.
Instructions should only be written after checking that the
Busy Flag is logic 0 or waiting for the required number of
cycles.
8.10 Address Counter (AC)
The Address Counter assigns addresses to the DDRAM
and CGRAM for reading and writing and is set by the
instructions ‘Set CGRAM address’ and
‘Set DDRAM address’. After a read/write operation the
Address Counter is automatically incremented or
decremented by 1. The Address Counter contents are
output to the bus (DB6to DB0) when RS= logic 0 and
R/W= logic1.
8.11 Display Data RAM (DDRAM)
The DDRAM stores up to 80 characters of display data
represented by 8-bit character codes. RAM locations
which are not used for storing display data can be used as
general purpose RAM. The basic DDRAM-to-display
mapping is shown in Fig.3. With no display shift the
characters represented by the codes in the first 24 RAM
locations starting at address 00 in line 1 are displayed.
Figures4 and 5 show the display mapping for right and left
shift respectively.
When data is written to or read from the DDRAM
wrap-around occurs from the end of one line to the start of
the next line. When the display is shifted each line wraps
around within itself, independently of the others. Thus all
lines are shifted and wrapped around together.
The address ranges and wrap- around operations for the
various modes are shown in Table3.
Table 3 Address space and wrap-around operation
8.12 Character Generator ROM (CGROM)
The Character Generator ROM (CGROM) generates
240 character patterns in 5×8 dot format from 8-bit
character codes. Figures 7, 8 and 9 show the character
sets that are currently implemented.
8.13 Character Generator RAM (CGRAM)
Up to 16 user defined characters may be stored in the
Character Generator RAM (CGRAM). Some CGRAM
characters (see Fig.17) are also used to drive icons (6if
icons blink and both icon rows are used in application; 3if
no blink but both icon rows are used in application; 0 if no
icons are driven by the icon rows). The CGROM and
CGRAM use a common address space, of which the first
column is reserved for the CGRAM (see Fig.7). Figure10
shows the addressing principle for the CGRAM.
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
8.14 Cursor control circuit
The cursor control circuit generates the cursor (underline
and/or cursor blink as shown in Fig.6) at the DDRAM
address contained in the Address Counter. When the
Address Counter contains the CGRAM address the cursor
will be inhibited.
8.15 Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the data buses.
8.16 LCD row and column drivers
The PCF2113x contains 18 row and 60 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display in accordance with the data to be
displayed. R17 and R18 drive the icon rows.
The bias voltages and the timing are selected
automatically when the number of lines in the display is
selected. Figures 11, 12 and 13 show typical waveforms.
Unused outputs should be left unconnected.
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
8.17 Reset function
The PCF2113x automatically initializes (resets) when power is turned on. The chip executes a reset sequence, requiring
165 OSC cycles. After the reset the chip’s functions are in the states shown in Table4.
Table 4 State after reset
Philips Semiconductors Product specification
LCD controller/driver PCF2113x INSTRUCTIONS
Only two PCF2113x registers, the Instruction Register (IR)
and the Data Register (DR) can be directly controlled by
the microcontroller. Before internal operation, control
information is stored temporarily in these registers, to
allow interface to various types of microcontrollers which
operate at different speeds or to allow interface to
peripheral control ICs.
The format for instructions when I2 C-bus control is used is
shown in Table 5. The PCF2113x operation is controlled
by the instructions shown in Table 6, which also gives
execution times in clock cycles. Details are explained in
subsequent sections.
Instructions are of 4 types, those that: Designate PCF2113x functions such as display
format, data length, etc. Set internal RAM addresses Perform data transfer with internal RAM Others.
In normal use, category 3 instructions are used most
frequently. However, automatic incrementing by1
(or decrementing by 1) of internal RAM addresses after
each data write lessens the microcontroller program load.
The display shift in particular can be performed
concurrently with display data write, enabling the designer
to develop systems in minimum time with maximum
programming efficiency.
During internal operation, no instruction other than the
‘Read busy flag and address’ instruction will be executed.
Because the Busy Flag is set to logic 1 while an instruction
is being executed, check to make sure it is on logic0
before sending the next instruction or wait for the
maximum instruction execution time, as given in Table6.
An instruction sent while the Busy Flag is logic 1 will not be
executed.
Table 5 Instruction format for I2C-bus instructions
Note R/W is set together with the slave address.
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
able 6
Instructions
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
Note 1.
don’t care.
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
Table 7 Explanations of symbols used in Table6
Table 8 Explanation of TC1 and TC2 used in Table6
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
9.1 Clear display
‘Clear display’ writes character code 20 (hexadecimal) into
all DDRAM addresses (the character pattern for character
code 20 must be blank pattern), sets the DDRAM Address
Counter to logic 0 and returns display to its original
position if it was shifted. Thus, the display disappears and
the cursor or blink position goes to the left edge of the
display. Sets entry mode I/D= logic 1 (increment mode).
S of entry mode does not change.
The instruction ‘Clear display’ requires extra execution
time. This may be allowed by checking the Busy Flag (BF)
or by waiting until the 165 clock cycles have elapsed.
The latter must be applied where no read-back options are
foreseen, as in some Chip-On-Glass (COG) applications.
9.2 Return home
‘Return home’ sets the DDRAM Address Counter to
logic 0 and returns display to its original position if it was
shifted. DDRAM contents do not change. The cursor or
blink position goes to the left of the first display line. I/D and
S of entry mode do not change.
9.3 Entry mode set
9.3.1 I/D
When I/D= logic 1 (0) the DDRAM or CGRAM address
increments (decrements) by 1 when data is written into or
read from the DDRAM or CGRAM. The cursor or blink
position moves to the right when incremented and to the
left when decremented. The cursor underline and cursor
character blink are inhibited when the CGRAM is
accessed.
9.3.2 S
When S= logic 1, the entire display shifts either to the right
(I/D= logic 0) or to the left (I/D= logic 1) during a DDRAM
write. Thus it looks as if the cursor stands still and the
display moves. The display does not shift when reading
from the DDRAM, or when writing into or reading out of the
CGRAM. When S= logic 0 the display does not shift.
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
9.4 Display control (and partial power-down mode)
9.4.1 D
The display is on when D= logic 1 and off when= logic 0. Display data in the DDRAM are not affected
and can be displayed immediately by setting D to logic1.
When the display is off (D= logic 0) the chip is in partial
power-down mode: The LCD-outputs are connected to VSS The LCD generator and bias generator are turned off. OSC cycles are required after sending the ‘Display off’
instruction to ensure all outputs are at VSS, afterwards
OSC can be stopped. If the oscillator is running during
partial power-down mode (‘Display off’) the chip can still
execute instructions. Even lower current consumption is
obtained by inhibiting the oscillator (OSC= VSS).
To ensure IDD <1 μA the parallel bus pins DB7to DB0
should be connected to VDD; RS, R/W, to VDD or left open
and PDto VDD. Recovery from power-down mode: PD
back to logic 0, if necessary OSC back to VDD, send a
‘Display control’ instruction with D= logic1.
9.4.2 C
The cursor is displayed when C= logic 1 and inhibited
when C= logic 0. Even if the cursor disappears, the
display functions I/D, etc. remain in operation during
display data write. The cursor is displayed using 5 dots in
the 8th line (see Fig.6).
9.4.3 B
The character indicated by the cursor blinks when= logic 1. The cursor character blink is displayed by
switching between display characters and all dots on with
a period of approximately 1 s, with
The cursor underline and the cursor character blink can be
set to display simultaneously.
9.5 Cursor/display shift
‘Cursor/display shift’ moves the cursor position or the
display to the right or left without writing or reading display
data. This function is used to correct a character or move
the cursor through the display. In 2-line displays, the
cursor moves to the next line when it passes the last
position (40) of the line. When the displayed data is shifted
repeatedly all lines shift at the same time; displayed
characters do not shift into the next line. BLINK OSC 224-----------------=
The Address Counter (AC) content does not change if the
only action performed is shift display, but increments or
decrements with the ‘cursor shift’.
9.6 Function set
9.6.1 DL (PARALLEL MODE ONLY)
Sets interface data width. Data is sent or received in bytes
(DB7to DB0) when DL= logic 1 or in two nibbles
(DB7to DB4) when DL= logic 0. When 4-bit width is
selected, data is transmitted in two cycles using the
parallel bus. In a 4-bit application DB3to DB0 should be
left open (internal pull-ups). Hence in the first
‘Function set’ instruction after power-on N and H are set to
logic 1. A second ‘Function set’ must then be sent nibbles) to set N and H to their required values.
‘Function set’ from I2 C-interface sets the DL bit to logic1.
9.6.2 M
Chooses either 1-line by 24 display (M= 0) or 2-line by display (M=1).
9.6.3 H
When H= logic 0 the chip can be programmed via the
standard 11 instruction codes used in the PCF2116 and
other LCD controllers.
When H= logic 1 the extended range of instructions will be
used. These are mainly for controlling the display
configuration and the icons.
9.7 Set CGRAM address
‘Set CGRAM address’ sets bits 5to 0 of the CGRAM
address (ACG in Table 6) into the Address Counter (binary
A[5]to A[0]).
Data can then be written to or read from the CGRAM.
Attention: the CGRAM address uses the same address
register as the DDRAM address and consists of 7 bits
(binary A[6]to A[0]). With the ‘Set CGRAM address’
instruction, only bits 5 down to 0 are set. Bit 6 can be set
using the ‘Set DDRAM address’ instruction first, or by
using the auto-increment feature during CGRAM write.
All of bits 6to 0 can be read using the
‘Read busy flag and address’ instruction.
When writing to the lower part of the CGRAM, make sure
that bit 6 of the address is not set (e.g. by an earlier
DDRAM write or read action).
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
9.8 Set DDRAM address
‘Set DDRAM address’ sets the DDRAM address (ADD in
Table 6) into the Address Counter (binary A[6]to A[0]).
Data can then be written to or read from the DDRAM.
9.9 Read busy flag and address
‘Read busy flag and address’ reads the Busy Flag (BF)
and Address Counter (AC). BF= logic 1 indicates that an
internal operation is in progress. The next instruction will
not be executed until BF= logic 0, so BF should be
checked before sending another instruction.
At the same time, the value of the Address Counter
expressed in binary A[6]to A[0] is read out. The Address
Counter is used by both CGRAM and DDRAM, and its
value is determined by the previous instruction.
9.10 Write data to CGRAM or DDRAM
‘Write data’ writes binary 8-bit data D[7]to D[0] to the
CGRAM or the DDRAM.
Whether the CGRAM or DDRAM is to be written into is
determined by the previous ‘Set CGRAM address’ or
‘Set DDRAM address’ instruction. After writing, the
address automatically increments or decrements by 1, in
accordance with the entry mode. Only bits D[4]to D[0] of
CGRAM data are valid, bits D[7]to D[5] are ‘don’t care’.
9.11 Read data from CGRAM or DDRAM
‘Read data’ reads binary 8-bit data D[7]to D[0] from the
CGRAM or DDRAM.
The most recent ‘Set address’ instruction determines
whether the CGRAM or DDRAM is to be read.
The ‘Read data’ instruction gates the content of the Data
Register (DR) to the bus while E is high. After E goes low
again, internal operation increments (or decrements) the
AC and stores RAM data corresponding to the new AC into
the DR.
Note: the only three instructions that update the Data
Register (DR) are: ‘Set CGRAM address’ ‘Set DDRAM address’ ‘Read data’ from CGRAM or DDRAM.
Other instructions (e.g. ‘Write data’, ‘Cursor/display shift’,
‘Clear display’, ‘Return home’) do not modify the data
register content. EXTENDED FUNCTION SET INSTRUCTIONS AND
FEATURES
10.1 New instructions= logic 1 sets the chip into alternate instruction set
mode.
10.2 Icon control
The PCF2113x can drive up to 120 icons. See Fig.17 for
CGRAM to icon mapping.
10.3 IM
When IM= logic 0 the chip is in character mode. In
character mode characters and icons are driven
(MUX1: 18). The VLCD generator, if used, produces the
VLCD voltage programmed in register VA.
When IM= logic 1 the chip is in icon mode. In icon mode
only the icons are driven (MUX1: 2) and the VLCD voltage
generator, if used, produces the VLCD voltage
programmed in register VB.
Remark: If internally generated VLCD must not be lower
than VDD (VDD≤ 4V)
10.4 IB
Icon blink control is independent of the cursor/character
blink function.
When IB= logic 0 icon blink is disabled. Icon data is stored
in CGRAM character 0to 2 (3×8×5= 120 bits for
120 icons).
When IB= logic 1 icon blink is enabled. In this case each
icon is controlled by two bits. Blink consists of two half
phases (corresponding to the cursor on and off phases
called even and odd phases hereafter).
Icon states for the even phase are stored in CGRAM
characters 0to 2 (3×8×5= 120 bits for 120 icons).
These bits also define icon state when icon blink is not
used.
Icon states for the odd phase are stored in CGRAM
character 4to 6 (another 120 bits for the 120 icons). When
icon blink is disabled CGRAM characters 4to 6 may be
used as normal CGRAM characters.
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
Table 9 Blink effect for icons and cursor character blink
Philips Semiconductors Product specification
LCD controller/driver PCF2113x
10.5 Normal/Icon mode operation
10.6 Screen configuration
L: default is L= logic0.= logic 0: the two halves of a split screen are connected
in a standard way i.e. column 1/61, 2/62to 60/120.= logic 1: the two halves of a split screen are connected
in a mirrored way i.e. column 1/120, 2/119to 60/61.
This allows single layer PCB or glass layout.
10.7 Display configuration
P, Q: default is P, Q= logic0.= logic 1 mirrors the column data.= logic 1 mirrors the row data.
10.8 TC1, TC2
Default is TC1, TC2= logic 0. This selects the default
temperature coefficient for the internally generated VLCD.
TC1,TC2= 10,01 and 11 selects alternative temperature
coefficients 1, 2 and 3 respectively.
10.9 Set VLCD
VLCD value is programmed by instruction. Two on-chip
registers hold VLCD values for character mode and icon
mode respectively (VA and VB). The generated VLCD value
is independent of VDD, allowing battery operation of the
chip. VB must be programmed to FF in character mode (i.e.
using VA) and VA must be programmed to 00 in icon mode.
Note: If internally generated VLCD must not be lower
than VDD.
Note:DD 4V≤
VLCD programming: send ‘Function set’ instruction with H=1 send ‘Set VLCD’ instruction to write to voltage register: DB7, DB6= 10: DB5to DB0 are VLCD of character
mode (VA) DB7, DB6= 11: DB5to DB0 are VLCD of icon mode
(VB) DB5to DB0= 000000 switches VLCD generator off
(when selected) During ‘display off’ and power-down VLCD
generator is also disabled send ‘Function set’ instruction with H= 0 to resume
normal programming.
10.10 Reducing current consumption
Reducing current consumption can be achieved by one of
the options mentioned in Table 10.
Table 10 Reducing current consumption
When VLCD lies outside the VDD range and must be
generated, it is usually more efficient to use the on-chip
generator than an external regulator.
Table 11 Use of the VA and VB registers
Philips Semiconductors Product specification
LCD controller/driver PCF2113x INTERFACE TO MICROCONTROLLER
(PARALLEL INTERFACE)
The PCF2113x can send data in either two 4-bit operations
or one 8-bit operation and can thus interface to 4-bit or
8-bit microcontrollers.
In 8-bit mode data is transferred as 8-bit bytes using the data lines DB7to DB0. Three further control lines E, RS,
and R/W are required. See Chapter 7.
In 4-bit mode data is transferred in two cycles of 4 bits
each using pins DB7to DB4 for transaction. The higher
order bits (corresponding to DB7to DB4 in 8-bit mode) are
sent in the first cycle and the lower order bits (DB3to DB0
in 8-bit mode) in the second. Data transfer is complete
after two 4-bit data transfers. Note that two cycles are also
required for the Busy Flag check. 4-bit operation is
selected by instruction. See Figs14to 17 for examples of
bus protocol.
In 4-bit mode pins DB3to DB0 must be left open-circuit.
They are pulled up to VDD internally. INTERFACE TO MICROCONTROLLER
(I2C-BUS INTERFACE)
12.1 Characteristics of the I2 C-bus
The I2 C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a Serial Clock Line (SCL).
Both lines must be connected to a positive supply via a
pull-up resistor. Data transfer may be initiated only when
the bus is not busy.
Each byte of eight bits is followed by an acknowledge bit.
The acknowledge bit is a HIGH level signal put on the bus
by the transmitter during which time the master generates
an extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after
the reception of each byte. Also a master receiver must
generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a STOP
condition.
12.2I2 C-bus protocol
Before any data is transmitted on the I2 C-bus, the device
which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
start procedure. The I2 C-bus configuration for the different
PCF2113x read and write cycles is shown in
Figs23 and 24. The slow down feature of the I2 C-bus
protocol (receiver holds SCL low during internal
operations) is not used in the PCF2113x.
12.3 Definitions Transmitter: the device which sends the data to the bus Receiver: the device which receives the data from the
bus Master: the device which initiates a transfer, generates
clock signals and terminates a transfer Slave: the device addressed by a master Multi-Master: more than one master can attempt to
control the bus at the same time without corrupting the
message Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted Synchronization: procedure to synchronize the clock
signals of two or more devices.
