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PCF85103C-2T
256 x 8-bit CMOS EEPROMs with I2C-bus interface
Philips Semiconductors Product specification
256 × 8-bit CMOS EEPROMs with
2 C-bus interface PCF85102C-2; PCF85103C-2
CONTENTS FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION DEVICE SELECTION BLOCK DIAGRAM PINNING
7.1 Pin description PCF85102C-2
7.2 Pin description PCF85103C-2
8I2C-BUS PROTOCOL
8.1 Bus conditions
8.2 Data transfer
8.3 Device addressing
8.3.1 Remark
8.4 Write operations
8.4.1 Byte/word write
8.4.2 Page write
8.5 Read operations
8.5.1 Remark LIMITING VALUES CHARACTERISTICS I2 C-BUS CHARACTERISTICS WRITE CYCLE LIMITS PACKAGE OUTLINES SOLDERING
14.1 Introduction
14.2 Through-hole mount packages
14.2.1 Soldering by dipping or by solder wave
14.2.2 Manual soldering
14.3 Surface mount packages
14.3.1 Reflow soldering
14.3.2 Wave soldering
14.3.3 Manual soldering DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2 C COMPONENTS
Philips Semiconductors Product specification
256 × 8-bit CMOS EEPROMs with2 C-bus interface PCF85102C-2; PCF85103C-2
FEATURES Low power CMOS: maximum operating current: 2.0 mA maximum standby current 10 μA (at 6.0V),
typical4 μA. Non-volatile storage of:2 kbits organized as 256× 8-bit. Single supply with full operation down to 2.5V On-chip voltage multiplier Serial input/output I2 C-bus Write operations: byte write mode 8-byte page write mode
(minimizes total write time per byte). Read operations: sequential read random read. Internal timer for writing (no external components) Power-on reset High reliability by using a redundant storage code Endurance: 1000000 Erase/Write (E/W) cycles at
Tamb =22°C 10 years non-volatile data retention time Standard industrial pinning (pin 7 not connected) Up to sixteen EEPROMs addressable in one I2 C-bus
using both PCF85102 and PCF85103 in combination.
GENERAL DESCRIPTIONThe PCF85102C-2 and PCF85103C-2 (further referredto
as PCF8510xC-2) are 2 kbits (256× 8-bit) floating gate
Electrically Erasable Programmable Read Only Memories
(EEPROMs). Power consumption is low due to the full
CMOS technology used. The programming voltage is
generated on-chip, using a voltage multiplier.
The PCF8510x-2 is pin compatible to widely used
industrial pinning (pin 7 not connected).
As data bytes are received and transmitted via the serial2 C-bus, a package using eight pins is sufficient. Up to
sixteen PCF8510xC-2 devices may be connected to the
I2C-bus. Thisis possible with the introductionofa second
device selection code. Chip select is accomplished by
three address inputs (A0, A1 and A2) for each
PCF8510xC-2 type.
QUICK REFERENCE DATA
Philips Semiconductors Product specification
256 × 8-bit CMOS EEPROMs with2 C-bus interface PCF85102C-2; PCF85103C-2 ORDERING INFORMATION DEVICE SELECTION
Table 1 Device selection code
Note The Most Significant Bit (MSB) ‘b7’ is sent first.
Philips Semiconductors Product specification
256 × 8-bit CMOS EEPROMs with2 C-bus interface PCF85102C-2; PCF85103C-2
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BLOCK DIAGRAM
Philips Semiconductors Product specification
256 × 8-bit CMOS EEPROMs with2 C-bus interface PCF85102C-2; PCF85103C-2 PINNING
PCF8510xC-2 has standard industrial pinning which will be compatible for most applications.
7.1 Pin description PCF85102C-2
7.2 Pin description PCF85103C-2
Philips Semiconductors Product specification
256 × 8-bit CMOS EEPROMs with2 C-bus interface PCF85102C-2; PCF85103C-22 C-BUS PROTOCOL
The I2 C-bus is designed for 2-way, 2-line communication
between different ICsor modules. The serial bus consists
of two bidirectional lines: one for data signals (SDA), and
one for clock signals (SCL).
Both the SDA and SCL lines must be connected to a
positive supply voltage via a pull-up resistor.
The following protocol has been defined: Data transfer may be initiated only when the bus is not
busy During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as
control signals.
8.1 Bus conditions
The following bus conditions have been defined: Bus not busy: both data and clock lines remain HIGH. Start data transfer: a change in the state of the data
line, from HIGH-to-LOW, while the clock is HIGH,
defines the START condition. Stop data transfer: a change in the state of the data
line, from LOW-to-HIGH, while the clock is HIGH,
defines the STOP condition. Data valid: the state of the data line represents valid
data when, after a START condition, the data line is
stable for the duration of the HIGH period of the clock
signal. There is one clock pulse per bit of data.
8.2 Data transfer
Each data transferis initiated witha START condition and
terminated witha STOP condition. The numberof the data
bytes, transferred between the START and STOP
conditions is limited to seven bytes in the E/W mode and
eight bytes in the page E/W mode.
Data transfer is unlimited in the read mode.
The information is transmitted in bytes and each receiver
acknowledges with a ninth bit.
Within the I2 C-bus specifications, a low-speed mode kHz clock rate) anda high speed mode (100 kHz clock
rate) are defined. The PCF8510xC-2 operates in both
modes.
By definition, a device that sends a signal is called a
‘transmitter’, and the device that receives the signal is
called a ‘receiver’. The device that controls the signal is
called the ‘master’. The devices that are controlledby the
master are called ‘slaves’.
Each byte is followed by one acknowledge bit, which is
placed on the bus at a HIGH level by the transmitter.
The master generatesan extra acknowledge-related clock
pulse. The slave receiver that is addressed is obliged to
generatean acknowledge after the receptionof each byte.
The master receiver must generatean acknowledge after
the receptionof each byte that has been clocked outof the
slave transmitter.
The device that acknowledges has to pull the SDA line
down during the acknowledge clock pulse in such a way
that the SDA lineis stable LOW during the HIGH periodof
the acknowledge-related clock pulse.
Set-up and hold times must be taken into account. A
master receiver must signal an end of data to the slave
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event,
the transmitter must leave the data lineHIGHto enable the
master generation of the STOP condition.
Philips Semiconductors Product specification
256 × 8-bit CMOS EEPROMs with2 C-bus interface PCF85102C-2; PCF85103C-2
8.3 Device addressing
Followinga START condition, the bus master must output
the addressof the slaveitis accessing. The four MSBsof
the slave address are the device type identifier (see Fig.4
and Fig.5). For the PCF85102C-2, this is fixed to ‘1010’,
for the PCF85103C-2 to ‘0010’.
The next three significant bits addressa particular device memory page (page= 256 bytesof memory).A system
could have up to sixteen PCF8510xC-2 devices on the
bus. This canbe achieved with eight PCF85102C devices
and eight PCF85103C devices, combinedon one I2C-bus.
The eight addresses are definedby the stateof the A0,A1
and A2 inputs per type.
The last bit of the slave address defines the operation to
be performed. When set to logic 1, a read operation is
selected.
Address bits must be connected to either VDD or VSS.
8.3.1 REMARK
TheI2 C-bus device select address ‘0010’is not exclusively
reserved for device PCF85103C-2. Therefore, multiple
use has to be checked in advance.
8.4 Write operations
8.4.1 BYTE/WORD WRITE
Fora write operation, the PCF8510xC-2 requiresa second
address field. This address field is a word address
providing accessto the 256 wordsof memory. On receipt
of the word address, the PCF8510xC-2 responds with an
acknowledge and awaits the next eight bitsof data, again
responding with an acknowledge. The word address is
automatically incremented. The master can now terminate
the transfer by generating a STOP condition or
transmitting up to six more bytes of data and then
terminating by generating a STOP condition.
After thisSTOP condition, the E/W cycle starts and the bus
is free for another transmission. The duration of the
E/W cycle is 10 ms per byte.
During the E/W cycle, the slave receiver does not sendan
acknowledge bit if addressed via the I2 C-bus.
8.4.2 PAGE WRITE
The PCF8510xC-2 is capable of an 8-byte page write
operation. It is initiated in the same manner as the byte
write operation. The master can transmit eight data bytes
within one transmission. After receipt of each byte, the
PCF8510xC-2 will respond with an acknowledge.
The typical E/W timein this modeis9× 3.5 ms= 31.5 ms.
Erasinga blockof eight bytesin page mode takesa typical
3.5 ms and sequential writingof these eight bytes another
typical 28 ms.
After the receiptof each data byte, the three low order bits
of the word address are internally incremented. The five
high order bits of the address remain unchanged.
The slave acknowledges the reception of each data byte
with an ACK. The I2 C-bus data transfer is terminated by
the master after the eighth byte with a STOP condition. the master transmits more than eight bytes prior to
generating the STOP condition, no acknowledge will be
given on the ninth (and following) data bytes. Also, the
whole transmission will be ignored and no programming
will be done. As in the byte write operation, all inputs are
disabled until completion of the internal write cycles.
Philips Semiconductors Product specification
256 × 8-bit CMOS EEPROMs with2 C-bus interface PCF85102C-2; PCF85103C-2
Philips Semiconductors Product specification
256 × 8-bit CMOS EEPROMs with2 C-bus interface PCF85102C-2; PCF85103C-2
8.5 Read operations
The read operations are initiatedin the same wayas write
operations, with the exception that the LSB of the slave
address is set to logic1.
There are three basic read operations; current address
read, random read and sequential read sequential read.
8.5.1 REMARK
The lower eight bitsof the word address are incremented
after each transmission of a data byte (read or write).
The MSB of the word address, which is defined in the
slave address, is not changed when the word address
count overflows. Thus, the word address overflows from
255to0.
