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PCF8562TT
Universal LCD driver for low multiplex rates
1. General description
The PCF8562 is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 32 segments. The PCF8562
is compatible with most microcontrollers and communicates via the two-line bidirectional 2 C-bus. Communication overheads are minimized by a display RAM with
auto-incremented addressing, by hardware subaddressing and by display memory
switching (static and duplex drive modes).
2. Features and benefits AEC-Q100 compliant (PCF8562TT/S400/2) for automotive applications Single chip LCD controller and driver Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing Selectable display bias configuration: static, 1 ⁄2, or 1⁄3 Internal LCD bias generation with voltage-follower buffers 32 segment drives: Up to sixteen 7-segment numeric characters Up to eight 14-segment alphanumeric characters Any graphics of up to 128 elements 32  4-bit RAM for display data storage Auto-incremented display data loading across device subaddress boundaries Display memory bank switching in static and duplex drive modes Versatile blinking modes Independent supplies possible for LCD and logic voltages Wide power supply range: from 1.8 V to 5.5V Wide logic LCD supply range: From 2.5 V for low-threshold LCDs Up to 6.5 V for guest-host LCDs and high-threshold twisted nematic LCDs Low power consumption 400 kHz I2 C-bus interface No external components required Manufactured in silicon gate CMOS process
PCF8562
Universal LCD driver for low multiplex rates
Rev. 6 — 16 June 2011 Product data sheet The definition of the abbreviations and acronyms used in this data sheet can be found in Section18.
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
3. Ordering information
[1] Not to be used for new designs. Replacement part is PCF85162T/1 for industrial applications.
[2] Not to be used for new designs. Replacement part is PCA85162T/Q900/1 for automotive applications.
4. Marking
Table 1. Ordering information
PCF8562TT/2[1] TSSOP48 plastic thin shrink small outline package; 48 leads;
body width 6.1 mm
SOT362-1
PCF8562TT/S400/2[2] TSSOP48 plastic thin shrink small outline package; 48 leads;
body width 6.1 mm
SOT362-1
Table 2. Marking codes
PCF8562TT/2 PCF8562TT
PCF8562TT/S400/2 PCF8562TT/S400
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
5. Block diagram
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
6.2 Pin description Table 3. Pin description
SDA 10 input/output I2 C-bus serial data line
SCL 11 input I2 C-bus serial clock
SYNC 12 input/output cascade synchronization
CLK 13 input/output clock line
VDD 14 supply supply voltage
OSC 15 input internal oscillator enabletoA2 16 to 18 input subaddress inputs
SA0 19 input I2 C-bus address input
VSS 20 supply ground supply voltage
VLCD 21 supply LCD supply voltage
BP0 to BP3 22 to 25 output LCD backplane outputsto S22,
S23 to S31
26 to 48,
1 to 9
output LCD segment outputs
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
7. Functional description
The PCF8562 is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 3). It
can directly drive any static or multiplexed LCD containing up to four backplanes and up to segments.
The possible display configurations of the PCF8562 depend on the number of active
backplane outputs required. A selection of display configurations is shown in Table 4. All
of these configurations can be implemented in the typical system shown in Figure4.
Table 4. Selection of possible display configurations
Number of 128 16 8 128 dots (4  32)
396 12 6 96 dots (3  32)
264 8 464 dots (2  32)
132 4 232 dots (1 32)
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
The host microcontroller maintains the 2-line I2 C-bus communication channel with the
PCF8562. The internal oscillator is enabled by connecting pin OSCto pin VSS. The
appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.
The only other connections required to complete the system are to the power supplies
(VDD, VSS, and VLCD) and the LCD panel chosen for the application.
7.1 Power-On Reset (POR)
At power-on the PCF8562 resets to the following starting conditions: All backplane and segment outputs are set to VLCD The selected drive mode is: 1:4 multiplex with 1 ⁄3 bias Blinking is switched off Input and output bank selectors are reset The I2 C-bus interface is initialized The data pointer and the subaddress counter are cleared (set to logic 0) Display is disabled
Remark: Do not transfer data on the I2 C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of
three impedances connected in series between VLCD and VSS. The center impedance is
bypassed by switch if the 1 ⁄2 bias voltage level for the 1:2 multiplex drive mode
configuration is selected. The LCD voltage can be temperature compensated externally,
using the supply to pin VLCD.
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
VLCD and the resulting discrimination ratios (D) are given in Table5.
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
Discrimination is a term which is defined as the ratio of the on and off RMS voltage across
a segment. It can be thought of as a measurement of contrast.
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode a suitable choice is VLCD >3Vth(off).
Multiplex drive modes of 1:3 and 1:4 with 1 ⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
Bias is calculated by
a = 1 for 1 ⁄2 bias
a = 2 for 1 ⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation1:
(1)
where the values for n are= 1 for static drive mode= 2 for 1:2 multiplex drive mode= 3 for 1:3 multiplex drive mode= 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation2:
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation3:
(3)
Table 5. Biasing characteristics
static 1 2 static 0 1 
1:2 multiplex2 3 1⁄2 0.354 0.791 2.236
1:2 multiplex2 4 1⁄3 0.333 0.745 2.236
1:3 multiplex3 4 1⁄3 0.333 0.638 1.915
1:4 multiplex4 4 1⁄3 0.333 0.577 1.732
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with ⁄2 biasis⁄2 bias is
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows: 1:3 multiplex (1 ⁄2 bias): 1:4 multiplex (1 ⁄2 bias):
These compare with 1 ⁄3 bias is used.
It should be noted that VLCD is sometimes referred as the LCD operating voltage.
7.3.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of
the pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 5. For a good contrast performance, the following rules should be followed:
(4)
(5)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a, n (see Equation 1 to Equation 3) and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. The
backplane (BPn) and segment (Sn) drive waveforms for this mode are shown in Figure6.
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCF8562 allows the use of 1 ⁄2 bias or 1 ⁄3 bias in this mode as shown in Figure 7 and
Figure8.
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as
shown in Figure9.
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
7.4.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as
shown in Figure 10.
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
7.5 Oscillator
7.5.1 Internal clock
The internal logic of the PCF8562 and its LCD drive signals are timed either by its internal
oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC
to pin VSS.
7.5.2 External clock
Pin CLK is enabled as an external clock input by connecting pin OSC to VDD.
The LCD frame signal frequency is determined by the clock frequency (fclk).
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.6 Timing
The PCF8562 timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. The timing
also generates the LCD frame signal whose frequency is derived from the clock
frequency. The frame signal frequency is a fixed division of the clock frequency from either
the internal or an external clock:
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
7.8 Segment outputs
The LCD drive section includes 32 segment outputs S0to S31 which should be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display latch. When
less than 32 segment outputs are required, the unused segment outputs should be left
open-circuit.
7.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outputs can be left open-circuit. In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these
two adjacent outputs can be tied together to give enhanced drive capabilities. In the 1:2 multiplex drive mode, BP0 and BP2, respectively, BP1 and BP3 carry the
same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and
they can be connected in parallel for very high drive requirements.
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
7.10 Display RAM
The display RAM is a static 32  4-bit RAM which stores LCD data. There is a one-to-one
correspondence between the bits in the RAM bitmap and the LCD elements the RAM columns and the segment outputs the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
The display RAM bit map Figure 11 shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 31 which correspond with the
segment outputs S0 to S31. In multiplexed LCD applications the segment data of the first,
second, third, and fourth row of the display RAM are time-multiplexed with BP0, BP1,
BP2, and BP3 respectively.
When display data is transmitted to the PCF8562, the display bytes received are stored in
the display RAM in accordance with the selected LCD drive mode. The data is stored as it
arrives and depending on the current multiplex drive mode the bits are stored singularly, in
pairs, triples or quadruples. To illustrate the filling order, an example of a 7-segment
numeric display showing all drive modes is given in Figure 12; the RAM filling organization
depicted applies equally to other LCD types.
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NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
The following applies to Figure 12: In static drive mode the eight transmitted data bits are placed in row 0 as one byte. In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row0 and 1 as two successive 4-bit RAM words. In 1:3 multiplex drive mode the eight bits are placed in triples into row0,1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted (see Section 7.10.3). In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row0,1, 2, and 3 as two successive 4-bit RAM words.
7.10.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 12). Following this command,
an arriving data byte is stored at the display RAM address indicated by the data pointer.
The filling order is shown in Figure 12.
After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode: In static drive mode by eight In 1:2 multiplex drive mode by four In 1:3 multiplex drive mode by three In 1:4 multiplex drive mode by two
If an I2 C-bus data access is terminated early then the state of the data pointer is unknown.
The data pointer should be re-written prior to further RAM accesses.
7.10.2 Subaddress counter
The storage of display data is determined by the content of the subaddress counter.
Storage is allowed to take place only when the content of the subaddress counter
matches with the hardware subaddress applied to A0, A1, and A2. The subaddress
counter value is defined by the device-select command (see Table 13). If the content of
the subaddress counter and the hardware subaddress do not match then data storage is
inhibited but the data pointer is incremented as if data storage had taken place. The
subaddress counter is also incremented when the data pointer overflows.
The hardware subaddress must not be changed while the device is being accessed on the 2 C-bus interface.
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates
7.10.3 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 6 (see Figure 12 as
well).
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table7.
In the case described in Table 7 the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a
combination of writing and rewriting the RAM like follows: In the first write to the RAM, bits a7 to a0 are written. In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6. In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6.
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some elements remain unused or can be used, but it has to be considered in the module
layout process as well as in the driver software design.
7.10.4 Output bank selector
The output bank selector (see Table 14) selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the
particular LCD drive mode in operation and on the instant in the multiplex sequence. In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the content of row 1, 2, and then 3 In 1:3 multiplex mode, rows0,1, and 2 are selected sequentially
Table 6. Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.
Table 7. Entire RAM filling by rewriting in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.
NXP Semiconductors PCF8562
Universal LCD driver for low multiplex rates In 1:2 multiplex mode, rows0 and 1 are selected In static mode, row 0 is selected
The PCF8562 includes a RAM bank switching feature in the static and 1:2 multiplex drive
modes. In the static drive mode, the bank-select command may request the content of
row 2 to be selected for display instead of the content of row 0. In the 1:2 multiplex mode,
the content of rows2 and 3 may be selected instead of rows0 and 1. This gives the
provision for preparing display information in an alternative bank and to be able to switch
to it once it is assembled.
7.10.5 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration.
The bank-select command (see Table 14) can be used to load display data in row 2 in
static drive mode or in rows2 and 3 in 1:2 mode. The input bank selector functions are
independent of the output bank selector.
7.11 Blinking
The display blinking capabilities of the PCF8562 are very versatile. The whole display can
blink at frequencies selected by the blink-select command (see Table 15). The blink
frequencies are fractions of the clock frequency. The ratio between the clock and blink
frequencies depends on the blink mode selected (see Table8).
An additional feature is for an arbitrary selection of LCD elements to blink. This applies to
the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the blink frequency. This mode can
also be specified by the blink-select command.
In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups of
LCD elements can blink by selectively changing the display RAM data at fixed time
intervals.
[1] Blink modes 1, 2, and 3 and the nominal blink frequencies 0.5 Hz, 1Hz, and2 Hz correspond to an
oscillator frequency (fclk) of 1536 Hz (see Section 12).
The entire display can blink at a frequency other than the nominal blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 11).
Table 8. Blinking frequencies[1]
off - blinking off
12 Hz
21 Hz 0.5 Hz

Partno	Mfg	Dc	Qty	Available	Descript
PCF8562TT	PHI	N/a	300	avai	Universal LCD driver for low multiplex rates