PCF8563P-PCF8563T-PCF8563TS Fast Delivery |IC PHOENIX CO.,LIMITED

PCF8563TS ,Real-time clock/calendarFeatures■ Provides year, month, day, weekday, hours, minutes and seconds based on32.768 kHz quartz ..
PCF8566 ,Universal LCD driver for low multiplex rates
PCF8566T ,Universal LCD driver for low multiplex ratesapplicationsn Space-saving 40-lead plastic very small outline package (VSO40; SOT158-1)n Manufactur ..
PCF8566T- ,Universal LCD driver for low multiplex rates
PCF8566U/F1 ,PCF8566; Universal LCD driver for low multiplex rates
PCF8570P ,256 x 8-bit static low-voltage RAM with I2C-bus interfaceAPPLICATIONSread data byte. Three address pins, A0, A1 and A2 are• Telephony: used to define the ha ..
PH4330L , N-channel TrenchMOS logic level FET
PH4530L ,PH4530L; N-channel TrenchMOS(tm) logic level FET
PH4530L ,PH4530L; N-channel TrenchMOS(tm) logic level FET
PH4840S ,PH4840S; N-channel Trenchmos (tm) intermediate level FET
PH5502B2NA1-E4 , Ambient Illuminance Sensor
PH600S280-24 , Simple function, 50 to 600W DC-DC converters

PCF8563P-PCF8563T-PCF8563TS
Real-time clock/calendar
PCF8563
Real-time clock/calendar
16 April 1999 Product speciﬁcation General description
The PCF8563 is a CMOS real-time clock/calendar optimized for low power
consumption.A programmable clock output, interrupt output and voltage-low detector
are also provided. All address and data are transferred serially via a two-line
bidirectional I2 C-bus. Maximum bus speed is 400 kbits/s. The built-in word address
register is incremented automatically after each written or read data byte. Features Provides year, month, day, weekday, hours, minutes and seconds based on
32.768 kHz quartz crystal Century ﬂag Wide operating supply voltage range: 1.0to 5.5V Low back-up current; typical 0.25 μA at VDD= 3.0 V and Tamb =25°C 400 kHz two-wire I2 C-bus interface (at VDD= 1.8to 5.5V) Programmable clock output for peripheral devices: 32.768 kHz, 1024 Hz, Hz and1 Hz Alarm and timer functions Voltage-low detector Integrated oscillator capacitor Internal power-on resetI2 C-bus slave address: read A3H; write A2H Open drain interrupt pin. Applications Mobile telephones Portable instruments Fax machines Battery powered products.
Philips Semiconductors PCF8563
Real-time clock/calendar Quick reference data Ordering information Block diagram
Table 1: Quick reference data
VDD supply voltage operating mode I2 C-bus inactive; Tamb =25°C 1.0 5.5 V2 C-bus active; fSCL= 400 kHz;
Tamb= −40to +85°C
1.8 5.5 V
IDD supply current; timer and CLKOUT
disabled
fSCL= 400 kHz - 800 μA
fSCL= 100 kHz - 200 μA
fSCL=0 Hz; Tamb=25°C
VDD=5V - 550 nA
VDD=2V - 450 nA
Tamb operating ambient temperature −40 +85 °C
Tstg storage temperature −65 +150 °C
Table 2: Ordering information
PCF8563P DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1
PCF8563T SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PCF8563TS TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3.0 mm SOT505-1
Philips Semiconductors PCF8563
Real-time clock/calendar Pinning information
7.1 Pinning
7.2 Pin description
Table 3: Pin description
OSCI 1 oscillator input
OSCO 2 oscillator output
INT 3 interrupt output (open-drain; active LOW)
VSS 4 ground
SDA 5 serial data I/O
SCL 6 serial clock input
CLKOUT 7 clock output (open-drain)
VDD 8 positive supply
Philips Semiconductors PCF8563
Real-time clock/calendar Functional description
The PCF8563 contains sixteen 8-bit registers with an auto-incrementing address
register, an on-chip 32.768 kHz oscillator with an integrated capacitor, a frequency
divider which provides the source clock for the Real-Time Clock (RTC), a
programmable clock output, a timer, an alarm, a voltage-low detector and a 400 kHz2 C-bus interface.
All 16 registers are designed as addressable 8-bit parallel registers although not all
bits are implemented. The ﬁrst two registers (memory address 00H and 01H) are
usedas control and/or status registers. The memory addresses 02H through 08H are
used as counters for the clock function (seconds up to year counters). Address
locations 09H through 0CH contain alarm registers which deﬁne the conditionsforan
alarm. Address 0DH controls the CLKOUT output frequency. 0EH and 0FH are the
timer control and timer registers, respectively.
The Seconds, Minutes, Hours, Days, Months, Years as well as the Minute alarm,
Hour alarm and Day alarm registers areall codedin BCD format. The Weekdays and
Weekday alarm register are not coded in BCD format.
When one of the RTC registers is read the contents of all counters are frozen.
Therefore, faulty reading of the clock/calendar during a carry condition is prevented.
8.1 Alarm function modes
By clearing the MSB (bit AE = Alarm Enable) of one or more of the alarm registers,
the corresponding alarm condition(s) will be active. In this way an alarm can be
generated from once per minute up to once per week. The alarm condition sets the
alarm ﬂag, AF (bit 3 of Control/Status 2 register). The asserted AF can be used to
generate an interrupt (INT). Bit AF can only be cleared by software.
8.2 Timer
The 8-bit countdown timer (address 0FH) is controlled by the Timer Control register
(address 0EH; see Table 25). The Timer Control register selects one of 4 source
clock frequencies for the timer (4096, 64,1,or1⁄60 Hz), and enables/disables the
timer. The timer counts down froma software-loaded 8-bit binary value.At the endof
every countdown, the timer sets the timer ﬂagTF (see Table 7). The timer ﬂag TF can
only be cleared by software. The asserted timer ﬂag TF can be used to generate an
interrupt (INT). The interrupt may be generated as a pulsed signal every countdown
periodorasa permanently active signal which follows the conditionof TF. TI/TP (see
Table 7) is used to control this mode selection. When reading the timer, the current
countdown value is returned.
8.3 CLKOUT output programmable square waveis availableat the CLKOUT pin. Operationis controlled
by the CLKOUT frequency register (address 0DH; see Table 23). Frequencies of
32.768 kHz (default), 1024,32 and1 Hz canbe generatedfor useasa system clock,
microcontroller clock, input to a charge pump, or for calibration of the oscillator.
CLKOUT is an open-drain output and enabled at power-on. If disabled it becomes
high-impedance.
Philips Semiconductors PCF8563
Real-time clock/calendar
8.4 Reset
The PCF8563 includesan internal reset circuit whichis active whenever the oscillator stopped.In the reset state theI2 C-bus logicis initialized andall registers, including
the address pointer, are cleared with the exceptionof bits FE, VL, TD1, TD0, TESTC
and AE which are set to logic1.
8.5 Voltage-low detector and clock monitor
The PCF8563 has an on-chip voltage-low detector. When VDD drops below Vlow the
VL bit (Voltage Low, bit 7 in the Seconds register) is set to indicate that reliable
clock/calendar information is no longer guaranteed. The VL ﬂag can only be cleared
by software.
The VL bit is intended to detect the situation when VDD is decreasing slowly for
example under battery operation. Should VDD reach Vlow before poweris re-asserted
then the VL bit will be set. This will indicate that the time may be corrupted.
8.6 Register organization
Table 4: Registers overview
Bit positions labelled as ‘−’are not implemented; those labelled with ‘0’ should always be written with logic0.
Philips Semiconductors PCF8563
Real-time clock/calendar
[1] Not coded in BCD.
8.6.1 Control/Status 1 register
Table 5: BCD formatted registers overview
Bit positions labelled as ‘−’are not implemented.
Table 6: Control/Status 1 register bits description (address 00H) TEST1 TEST1= 0; normal mode.
TEST1= 1; EXT_CLK test mode; see Section 8.7. STOP STOP= 0; RTC source clock runs.
STOP= 1; all RTC divider chain ﬂip-ﬂops are asynchronously set logic 0; the RTC clock is stopped (CLKOUT at 32.768 kHz is still
available). TESTC TESTC= 0; power-on reset override facility is disabled (set to logic0
for normal operation).
TESTC= 1; power-on reset override is enabled.
6, 4, 2to00 By default set to logic0.
Philips Semiconductors PCF8563
Real-time clock/calendar
8.6.2 Control/Status 2 register
[1] TF and INT become active simultaneously.
[2]n= loaded countdown timer value. Timer stopped when n=0.
Table 7: Description of Control/Status 2 register bits description (address 01H)to5 0 By default set to logic0. TI/TP TI/TP=0: INTis active whenTFis active (subjectto the statusof TIE).
TI/TP=1: INT pulses active accordingto Table8 (subjectto the status TIE). Note thatifAF and AIE are active then INTwillbe permanently
active. AF When an alarm occurs, AF is set to logic 1. Similarly, at the end of a
timer countdown, TF is set to logic 1. These bits maintain their value
until overwritten by software. If both timer and alarm interrupts are
required in the application, the source of the interrupt can be
determined by reading these bits. To prevent one ﬂag being
overwritten while clearing another, a logic AND is performed during a
write access. See Table 9 for the value descriptions of bits AF and TF.
2TF AIE Bits AIE and TIE activate or deactivate the generation of an interrupt
whenAForTFis asserted, respectively. The interruptisthe logical OR
of these two conditions when both AIE and TIE are set.
AIE= 0: alarm interrupt disabled; AIE = 1: alarm interrupt enabled.
TIE= 0: timer interrupt disabled; TIE= 1: timer interrupt enabled. TIE
Table 8: INT operation (bit TI/TP=1)
4096 1 ⁄8192 1 ⁄4096 1⁄128 1⁄64 1⁄64 1⁄64⁄60 1⁄64 1⁄64
Table 9: Value descriptions for bits AF and TF
Read 0 alarm ﬂag inactive 0 timer ﬂag inactive alarm ﬂag active 1 timer ﬂag active
Write 0 alarm ﬂag is cleared 0 timer ﬂag is cleared alarm ﬂag remains unchanged 1 timer ﬂag remains unchanged
Philips Semiconductors PCF8563
Real-time clock/calendar
8.6.3 Seconds, Minutes and Hours registers
8.6.4 Days, Weekdays, Months/Century and Years registers
Table 10: Seconds/VL register bits description (address 02H) VL VL= 0: reliable clock/calendar information is guaranteed;= 1: reliable clock/calendar information is no longer
guaranteed.to0 These bits represent the current seconds value coded in BCD
format; value=00to 59.
Example: = 101 1001, represents the value59s.
Table 11: Minutes register bits description (address 03H) − not implementedto0 These bits represent the current minutes value coded in BCD
format; value=00to 59.
Table 12: Hours register bits description (address 04H)
7 to6 − not implementedto0 These bits represent the current hours value codedin BCD format;
value=00to23.
Table 13: Days register bits description (address 05H)
7 to6 − not implementedto0 These bits represent the current day value coded in BCD format;
value=01 to 31.
The PCF8563 compensatesfor leap yearsby addinga 29th dayto
February if the year counter contains a value which is exactly
divisible by 4, including the year ‘00’.
Table 14: Weekdays register bits description (address 06H)
7 to3 − not implementedto0 These bits represent the current weekday value0to6;
see Table 15.
These bits may be re-assigned by the user.
Philips Semiconductors PCF8563
Real-time clock/calendar
Table 15: Weekday assignments
Sunday 0 0 0
Monday 0 0 1
Tuesday 0 1 0
Wednesday 0 1 1
Thursday 1 0 0
Friday 1 0 1
Saturday 1 1 0
Table 16: Months/Century register bits description (address 07H) C Century bit. C= 0; indicates the century is 20xx.=1; indicatesthe centuryis 19xx. ‘xx’ indicates the value heldin the ears register; see Table 18.
This bit is toggled when the Years register overﬂows from 99to 00.
These bits may be re-assigned by the user.
6to5 − not implementedto0 These bits represents the current month value coded in BCD format;
value=01to 12; see Table 17.
Table 17: Month assignments
January 00001
February 00010
March 00011
April 00100
May 00101
June 00110
July 00111
August 01000
September 01001
October 10000
November 10001
December 10010
Table 18: Years register bits description (address 08H)to0 This register represents the current year value coded in BCD
format; value=00to 99.
Philips Semiconductors PCF8563
Real-time clock/calendar
8.6.5 Alarm registers
When oneor moreof the alarm registers are loaded witha valid minute, hour, dayor
weekday and its corresponding AE (Alarm Enable) bit is a logic 0, then that
information will be compared with the current minute, hour, day and weekday. When
all enabled comparisons ﬁrst match, the bit AF (Alarm Flag) is set. will remain set until clearedby software. Once AF has been clearedit will onlybe
set again when the time increments to match the alarm condition once more. Alarm
registers which have their AE bit set at logic 1 will be ignored.
Table 19: Minute alarm register bits description (address 09H) AE AE= 0; minute alarm is enabled. AE= 1; minute alarm is disabled.to0 These bits represents the minute alarm information coded in BCD
format; value=00to 59.
Table 20: Hour alarm register bits description (address 0AH) AE AE= 0; hour alarm is enabled. AE= 1; hour alarm is disabled.to0 These bits represents the hour alarm information coded in BCD
format; value=00to 23.
Table 21: Day alarm register bits description (address 0BH) AE AE= 0; day alarm is enabled. AE= 1; day alarm is disabled.to0 These bits represents the day alarm information coded in BCD
format; value=01to 31.
Table 22: Weekday alarm register bits description (address 0CH) AE AE= 0; weekday alarm is enabled.= 1; weekday alarm is disabled.to0 These bits represents the weekday alarm information
value0to6.
Philips Semiconductors PCF8563
Real-time clock/calendar
8.6.6 CLKOUT frequency register
8.6.7 Countdown timer registers
The Timer register is an 8-bit binary countdown timer. It is enabled and disabled via
the Timer control registerbit TE. The source clockfor the timeris also selectedby the
Timer control register. Other timer properties, e.g. interrupt generation, are controlled
via the Control/status2 register. For accurate read back of the countdown value, the2 C-bus clock SCL must be operating at a frequency of at least twice the selected
timer clock.
Table 23: CLKOUT frequency register bits description (address 0DH) FE FE=0; the CLKOUT outputis inhibited and the CLKOUT outputis
set to high-impedance. FE = 1; the CLKOUT output is activated.
6to2 − not implemented FD1 These bits control the frequency output (fCLKOUT) on the CLKOUT
pin; see Table 24.0 FD0
Table 24: CLKOUT frequency selection 0 32.768 kHz 1 1024Hz 0 32Hz 1Hz
Table 25: Timer control register bits description (address 0EH) TE TE= 0; timer is disabled. TE = 1; timer is enabled.
6to2 − not implemented TD1 Timer source clock frequency selection bits. These bits determine
the source clock for the countdown timer, see Table 26. When not
in use, TD1 and TD0 should be set to ‘11’ (1⁄60 Hz) for power
saving. TD0
Table 26: Timer source clock frequency selection 0 4096 64 1 1⁄60
Table 27: Timer countdown value register bits description (address 0FH)to0 This register holds the loaded countdown value ‘n’.
Countdown period n
Source clock frequency----------------------------------------------------------=
Philips Semiconductors PCF8563
Real-time clock/calendar
8.7 EXT_CLK test mode
A test mode is available which allows for on-board testing. In this mode it is possible
to set up test conditions and control the operation of the RTC.
The test mode is entered by setting bit TEST1 in the Control/Status1 register. The
CLKOUT pin then becomes an input. The test mode replaces the internal 64 Hz
signal with the signal that is applied to the CLKOUT pin. Every 64 positive edges
applied to CLKOUT will then generate an increment of one second.
The signal appliedto the CLKOUT pin should havea minimum pulse widthof 300ns
and a minimum period of 1000 ns. The internal 64 Hz clock, now sourced from
CLKOUT, is divided down to 1 Hz by a 26 divide chain called a pre-scaler. The
pre-scaler canbe set intoa known stateby using the STOP bit. When the STOPbitis
set, the pre-scaler is reset to 0. STOP must be cleared before the pre-scaler can
operate again. From a STOP condition, the ﬁrst 1 s increment will take place after positive edges on CLKOUT. Thereafter, every 64 positive edges will cause a 1s
increment.
Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz
clock. When entering the test mode, no assumption as to the state of the pre-scaler
can be made.
8.7.1 Operation example Enter the EXT_CLK test mode; set bit 7 of Control/Status1 register (TEST=1) Set bit 5 of Control/Status1 register (STOP=1) Clear bit 5 of Control/Status1 register (STOP=0) Set time registers (Seconds, Minutes, Hours, Days, Weekdays, Months/Century
and Y ears) to desired value Apply 32 clock pulses to CLKOUT Read time registers to see the ﬁrst change Apply 64 clock pulses to CLKOUT Read time registers to see the second change.
Repeat steps 7 and 8 for additional increments.
8.8 Power-On Reset (POR) override mode
The POR duration is directly related to the crystal oscillator start-up time. Due to the
long start-up times experienced by these types of circuits, a mechanism has been
built in to disable the POR and hence speed up on-board test of the device. The
setting of this mode requires that the I2 C-bus pins, SDA and SCL, be toggled in a
speciﬁc order as shown in Figure 5. All timing values are required minimum.
Once the override mode has been entered, the chip immediately stops being reset
and normal operation starts i.e. entry into the EXT_CLK test mode via I2 C-bus
access. The override modeis clearedby writinga logic0tobit TESTC. Re-entry into
the override mode is only possible after TESTC is set to logic 1. Setting TESTC to
logic 0 during normal operation has no effect except to prevent entry into the POR
override mode.
Philips Semiconductors PCF8563
Real-time clock/calendar
8.9 Serial interface
The serial interface of the PCF8563 is the I2 C-bus. A detailed description of the2 C-bus speciﬁcation, including applications, is given in the brochure: The I2 C-bus
and howto useit, order no. 9398 393 40011orI2C Peripherals Data Handbook IC12.
8.9.1 Characteristics of the I2 C-bus
The I2 C-bus is for bidirectional, two-line communication between different ICs or
modules. The two lines area serial data line (SDA) anda serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up resistor. Data transfer may
be initiated only when the bus is not busy.
The I2 C-bus system conﬁguration is shown in Figure 6. A device generating a
messageisa ‘transmitter’,a device receivinga messageis the ‘receiver’. The device
that controls the messageis the ‘master’ and the devices which are controlledby the
master are the ‘slaves’.
8.9.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transitionof the data line, while the clockis HIGHis deﬁnedas the start condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the
stop condition (P); see Figure7.
Philips Semiconductors PCF8563
Real-time clock/calendar
8.9.3 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must
remain stable during the HIGH periodof the clock pulseas changesin the data lineat
this time will be interpreted as a control signal; see Figure8.
8.9.4 Acknowledge
The numberof data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the
transmitter during which time the master generates an extra acknowledge related
clock pulse.
A slave receiver which is addressed must generate an acknowledge after the
reception of each byte. Also a master receiver must generate an acknowledge after
the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledgeon the last byte that has been clocked outof the slave.In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Philips Semiconductors PCF8563
Real-time clock/calendar
8.9.5I2 C-bus protocol
Addressing: Before any data is transmitted on the I2 C-bus, the device which should
respond is addressed ﬁrst. The addressing is always carried out with the ﬁrst byte
transmitted after the start procedure.
The PCF8563 actsasa slave receiveror slave transmitter. Therefore the clock signal
SCL is only an input signal, but the data signal SDA is a bidirectional line.
The PCF8563 slave address is shown in Figure 10.
Clock/calendar read/write cycles: The I2 C-bus conﬁguration for the different
PCF8563 read and write cycles are shown in Figure 11, 12 and 13. The word
address is a four bit value that deﬁnes which register is to be accessed next. The
upper four bits of the word address are not used.

Partno	Mfg	Dc	Qty	Available	Descript
PCF8563P	PHILIPS	N/a	650	avai	Real-time clock/calendar
PCF8563T	PHILPS	N/a	528	avai	Real-time clock/calendar
PCF8563TS	PHILIPS	N/a	791	avai	Real-time clock/calendar