PCF8576DT ,Universal LCD driver for low multiplex ratesapplications Single chip LCD controller and driver Selectable backplane drive configuration: stat ..
PCF8576DT/2 ,PCF8576D; Universal LCD driver for low multiplex rates
PCF8576DT/2 ,PCF8576D; Universal LCD driver for low multiplex rates
PCF8576DU/2DA/2 ,PCF8576D; Universal LCD driver for low multiplex rates
PCF8576DU/DA/2 ,PCF8576D; Universal LCD driver for low multiplex rates
PCF8576DU/DA/2 ,PCF8576D; Universal LCD driver for low multiplex rates
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PCF8576DT
Universal LCD driver for low multiplex rates
1. General descriptionThe PCF8576D is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily
cascaded for larger LCD applications. The PCF8576D is compatible with most
microcontrollers and communicates via the two-line bidirectional I2 C-bus. Communication
overheads are minimized by a display RAM with auto-incremented addressing, by
hardware subaddressing and by display memory switching (static and duplex drive
modes).
PCF8576DT/2 should not be used for new design-ins. Replacement part is
PCF85176T/1 for industrial applications
PCF8576DT/S400/2 should not be used for new design-ins. Replacement part is
PCA85176T/Q900/1 for automotive applications
2. Features and benefits AEC-Q100 compliant (PCF8576DT/S400/2) for automotive applications Single chip LCD controller and driver Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing Selectable display bias configuration: static, 1 ⁄2, or 1⁄3 Internal LCD bias generation with voltage-follower buffers 40 segment drives: Up to 20 7-segment numeric characters Up to 10 14-segment alphanumeric characters Any graphics of up to 160 elements 40 4-bit RAM for display data storage Auto-incremented display data loading across device subaddress boundaries Display memory bank switching in static and duplex drive modes Versatile blinking modes Independent supplies possible for LCD and logic voltages Wide power supply range: from 1.8 V to 5.5V Wide logic LCD supply range: From 2.5 V for low-threshold LCDs Up to 6.5 V for high-threshold twisted nematic LCDs Low power consumption 400 kHz I2 C-bus interface
PCF8576D
Universal LCD driver for low multiplex rates
Rev. 14 — 10 June 2013 Product data sheet The definition of the abbreviations and acronyms used in this data sheet can be found in Section20.
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates May be cascaded for large LCD applications (up to 2560 elements possible) No external components required Compatible with chip-on-glass and chip-on-board technology Manufactured in silicon gate CMOS process
3. Ordering information[1] Not to be used for new designs. Replacement part is PCF85176T/1 for industrial applications.
[2] Not to be used for new designs. Replacement part is PCA85176T/Q900/1 for automotive applications.
3.1 Ordering options
4. Marking
Table 1. Ordering informationPCF8576DT/2[1] TSSOP56 plastic thin shrink small outline package, 56 leads;
body width 6.1 mm
SOT364-1
PCF8576DT/S400/2[2] TSSOP56 plastic thin shrink small outline package, 56 leads;
body width 6.1 mm
SOT364-1
PCF8576DU/DA/2 wire bond die 59 bonding pads PCF8576DU/DA
PCF8576DU/2DA/2 bare die 59 bumps PCF8576DU/2DA
Table 2. Ordering optionsPCF8576DT/2 935276166118 PCF8576DT/2,118 2 tape and reel, 13 inch
PCF8576DT/S400/2 935287131118 PCF8576DT/S400/2,1 2 tape and reel, 13 inch
PCF8576DU/DA/2 935276239026 PCF8576DU/DA/2,026 2 chips in tray
PCF8576DU/2DA/2 935276249026 PCF8576DU/2DA/2,02 2 chips in tray
Table 3. Marking codesPCF8576DT/2 PCF8576DT
PCF8576DT/S400/2 PCF8576DT/S400
PCF8576DU/DA/2 PC8576D-2
PCF8576DU/2DA/2 PC8576D-2
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
5. Block diagramNXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 PinningNXP Semiconductors PCF8576D
Universal LCD driver for low multiplex ratesNXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
6.2 Pin description[1] The substrate (rear side of the die) is connected to VSS and should be electrically isolated.
Table 4. Pin descriptionSDA 44 1, 58, 59 I2 C-bus serial data input and output
SCL 45 2, 3 I2 C-bus serial clock input
CLK 47 5 external clock input or output
VDD 48 6 supply voltage
SYNC 46 4 cascade synchronization input or output
OSC 49 7 internal oscillator enable input
A0 to A2 50 to 52 8to10 subaddress inputs
SA0 53 11 I2 C-bus address input; bit0
VSS 54 12[1] ground supply voltage
VLCD 55 13 LCD supply voltage
BP0, BP2,
BP1, BP3
56, 1, 2, 3 14to17 LCD backplane outputs
S0 to S39 4 to 43 18to57 LCD segment outputs
n.c. - - not connected
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7. Functional descriptionThe PCF8576D is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 4). It
can directly drive any static or multiplexed LCD containing up to four backplanes and up to segments.
The possible display configurations of the PCF8576D depend on the number of active
backplane outputs required. A selection of display configurations is shown in Table 5. All
of these configurations can be implemented in the typical system shown in Figure5.
[1] 7 segment display has 8 elements including the decimal point.
[2] 14 segment display has 16 elements including decimal point and accent dot.
Table 5. Selection of possible display configurations
Number of 160 20 10 160 (4 40) 120 15 7 120 (3 40)
280 10 580 (2 40)
140 5240 (1 40)
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex ratesThe host microcontroller maintains the 2-line I2 C-bus communication channel with the
PCF8576D. The internal oscillator is enabled by connecting pin OSCto pin VSS. The
appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.
The only other connections required to complete the system are to the power supplies
(VDD, VSS, and VLCD) and the LCD panel chosen for the application.
7.1 Power-On Reset (POR)At power-on the PCF8576D resets to the following starting conditions:
All backplane and segment outputs are set to VLCD
The selected drive mode is: 1:4 multiplex with 1 ⁄3 bias
Blinking is switched off
Input and output bank selectors are reset
The I2 C-bus interface is initialized
The data pointer and the subaddress counter are cleared (set to logic 0)
The display is disabled (bit E= 0, see Table 12)
Remark: Do not transfer data on the I2 C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2 LCD bias generatorFractional LCD biasing voltages are obtained from an internal voltage divider of three
impedances connected between pins VLCD and VSS. The center impedance is bypassed
by switch if the 1⁄2 bias voltage level for the 1:2 multiplex drive mode configuration is
selected. The LCD voltage can be temperature compensated externally using the supply
to pin VLCD.
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.3 LCD voltage selectorThe LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
VLCD and the resulting discrimination ratios (D) are given in Table6.
Discrimination is a term which is defined as the ratio of the on and off RMS voltage across
a segment. It can be thought of as a measurement of contrast.
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode a suitable choice is VLCD >3Vth(off).
Multiplex drive modes of 1:3 and 1:4 with 1 ⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
Bias is calculated by
a = 1 for 1 ⁄2 bias
a = 2 for 1 ⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation1:
(1)
where the values for n are= 1 for static drive mode= 2 for 1:2 multiplex drive mode= 3 for 1:3 multiplex drive mode= 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation2:
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation3:
Table 6. Biasing characteristicsstatic 1 2 static 0 1
1:2 multiplex2 3 1⁄2 0.354 0.791 2.236
1:2 multiplex2 4 1⁄3 0.333 0.745 2.236
1:3 multiplex3 4 1⁄3 0.333 0.638 1.915
1:4 multiplex4 4 1⁄3 0.333 0.577 1.732
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates(3)
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with ⁄2 biasis⁄2 bias is
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
1:3 multiplex (1 ⁄2 bias):
1:4 multiplex (1 ⁄2 bias):
These compare with 1 ⁄3 bias is used.
It should be noted that VLCD is sometimes referred as the LCD operating voltage.
7.3.1 Electro-optical performanceSuitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of
the pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 6. For a good contrast performance, the following rules should be followed:
(4)
(5)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a, n (see Equation 1 to Equation 3) and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes just named Vth. Vth(on) is sometimes named saturation
voltage Vsat.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex ratesNXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive modeThe static LCD drive mode is used when a single backplane is provided in the LCD. The
backplane (BPn) and segment drive (Sn) waveforms for this mode are shown in Figure7.
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive modeThe 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This
mode allows fractional LCD bias voltages of 1 ⁄2 bias or 1 ⁄3 bias as shown in Figure 8 and
Figure9.
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex ratesNXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive modeWhen three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies
(see Figure 10).
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.4.4 1:4 Multiplex drive modeWhen four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies (see
Figure 11).
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.5 Oscillator
7.5.1 Internal clockThe internal logic of the PCF8576D and its LCD drive signals are timed either by its
internal oscillator or by an external clock. The internal oscillator is enabled by connecting
pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used
as the clock signal for several PCF8576Ds in the system that are connected in cascade.
7.5.2 External clockPin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD
frame signal frequency is determined by the clock frequency (fclk).
Remark: A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.6 TimingThe PCF8576D timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. In cascaded
applications, the correct timing relationship between each PCF8576D in the system is
maintained by the synchronization signal at pin SYNC. The timing also generates the LCD
frame signal whose frequency is derived from the clock frequency. The frame signal
frequency is a fixed division of the clock frequency from either the internal or an external
clock: .
7.7 Display registerThe display latch holds the display data while the corresponding multiplex signals are
generated.
7.8 Segment outputsThe LCD drive section includes 40 segment outputs S0to S39 which should be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display latch. When
less than 40 segment outputs are required, the unused segment outputs should be left
open-circuit.
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.9 Backplane outputsThe LCD drive section includes four backplane outputs BP0to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outputs can be left open-circuit.
In 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
In 1:2 multiplex drive mode, BP0 and BP2, respectively, BP1 and BP3 all carry the
same signals and may also be paired to increase the drive capabilities.
In static drive mode the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
7.10 Display RAMThe display RAM is a static 40 4-bit RAM which stores LCD data.
There is a one-to-one correspondence between
the bits in the RAM bitmap and the LCD elements
the RAM columns and the segment outputs
the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
The display RAM bit map, Figure 12, shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the
segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,
second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2,
and BP3 respectively.
When display data is transmitted to the PCF8576D, the received display bytes are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and depending on the current multiplex drive mode the bits are stored singularly,
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex ratesin pairs, triples, or quadruples. To illustrate the filling order, an example of a 7-segment
display showing all drive modes is given in Figure 13; the RAM filling organization
depicted applies equally to other LCD types.
The following applies to Figure 13:
In static drive mode the eight transmitted data bits are placed into row 0 as one byte.
In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row0 and 1 as two successive 4-bit RAM words.
In 1:3 multiplex drive mode the eight bits are placed in triples into row0,1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address, but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted (see Section 7.10.3).
In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row0,1,2, and 3 as two successive 4-bit RAM words.
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NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.10.1 Data pointerThe addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 13). Following this command,
an arriving data byte is stored at the display RAM address indicated by the data pointer.
The filling order is shown in Figure 13. After each byte is stored, the content of the data
pointer is automatically incremented by a value dependent on the selected LCD drive
mode:
In static drive mode by eight.
In 1:2 multiplex drive mode by four.
In 1:3 multiplex drive mode by three.
In 1:4 multiplex drive mode by two.
If an I2 C-bus data access terminates early then the state of the data pointer is unknown.
Consequently, the data pointer must be rewritten prior to further RAM accesses.
7.10.2 Subaddress counterThe storage of display data is determined by the contents of the subaddress counter.
Storage is allowed only when the content of the subaddress counter match with the
hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined
by the device-select command (see Table 14). If the content of the subaddress counter
and the hardware subaddress do not match then data storage is inhibited but the data
pointer is incremented as if data storage had taken place. The subaddress counter is also
incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF8576D occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character.
The hardware subaddress must not be changed while the device is being accessed on the 2 C-bus interface.
7.10.3 RAM writing in 1:3 multiplex drive modeIn 1:3 multiplex drive mode, the RAM is written as shown in Table 7 (see Figure 13 as
well).
Table 7. Standard RAM filling in 1:3 multiplex drive modeAssumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex ratesIf the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table8.
In the case described in Table 8 the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a
combination of writing and rewriting the RAM like follows:
In the first write to the RAM, bits a7 to a0 are written.
In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6.
In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6.
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some elements remain unused or can be used, but it has to be considered in the module
layout process as well as in the driver software design.
7.10.4 Writing over the RAM address boundaryIn all multiplex drive modes, depending on the setting of the data pointer, it is possible to
fill the RAM over the RAM address boundary. If the PCF8576D is part of a cascade the
additional bits fall into the next device that also generates the acknowledge signal. If the
PCF8576D is a single device or the last device in a cascade the additional bits will be
discarded and no acknowledge signal will be generated.
7.10.5 Output bank selectorThe output bank selector (see Table 15) selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the
selected LCD drive mode in operation and on the instant in the multiplex sequence.
In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the contents of row 1, 2, and then 3
In 1:3 multiplex mode, rows0,1, and 2 are selected sequentially
In 1:2 multiplex mode, rows0 and 1 are selected
In static mode, row 0 is selected
The PCF8576D includes a RAM bank switching feature in the static and 1:2 multiplex
drive modes. In the static drive mode, the bank-select command may request the contents
of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex
Table 8. Entire RAM filling by rewriting in 1:3 multiplex drive modeAssumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex ratesmode, the contents of rows2 and 3 may be selected instead of rows0 and 1. This gives
the provision for preparing display information in an alternative bank and to be able to
switch to it once it is assembled.
7.10.6 Input bank selectorThe input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode
or in rows2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see
Table 15). The input bank selector functions independently to the output bank selector.
7.11 BlinkingThe display blinking capabilities of the PCF8576D are very versatile. The whole display
can blink at frequencies selected by the blink-select command (see Table 16). The blink
frequencies are derived from the clock frequency. The ratio between the clock and blink
frequencies depends on the blink mode selected (see Table 16).
An additional feature is for an arbitrary selection of LCD elements to blink. This applies to
the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the blink frequency. This mode can
also be specified by the blink-select command.
In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups of
LCD elements can blink by selectively changing the display RAM data at fixed time
intervals.
The entire display can blink at a frequency other than the nominal blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 12).
[1] Blink modes 1, 2 and 3 and the nominal blink frequencies 0.5 Hz, 1Hz and2 Hz correspond to an oscillator
frequency (fclk) of 1536 Hz (see Section 12).
Table 9. Blinking frequenciesoff - blinking off
12 Hz
21 Hz 0.5 Hz
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
7.12 Command decoderThe command decoder identifies command bytes that arrive on the I2 C-bus. The
commands available to the PCF8576D are defined in Table 10.
[1] Not used.
All available commands carry a continuation bit C in their most significant bit position as
shown in Figure 19. When this bit is set logic 1, it indicates that the next byte of the
transfer to arrive will also represent a command. If this bit is set logic 0, it indicates that
the command byte is the last in the transfer. Further bytes will be regarded as display data
(see Table 11).
Table 10. Definition of PCF8576D commands
Table 11. C bit description continue bit last control byte in the transfer; next byte will be regarded as display data control bytes continue; next byte will be a command too
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates[1] The possibility to disable the display allows implementation of blinking under external control.
[2] Default value.
[3] The display is disabled by setting all backplane and segment outputs to VLCD.
[4] Not applicable for static drive mode.
[1] Default value.
[1] Default value.
Table 12. Mode-set command bit description 0, 1see Table11
6, 5 - 10 fixed value - - unused
display status[1][2] disabled (blank)[3] enabled
LCD bias configuration[4][2] 1 ⁄3 bias 1 ⁄2 bias
1 to 0 M[1:0]
LCD drive mode selection static; BP0 1:2 multiplex; BP0, BP1 1:3 multiplex; BP0, BP1, BP2[2] 1:4 multiplex; BP0, BP1, BP2, BP3
Table 13. Load-data-pointer command bit descriptionSee Section 7.10.1. 0, 1see Table11 - 0 fixed value
5 to 0 P[5:0] 000000[1]
6 bit binary value, 0 to 39; transferred to the data pointer to
define one of forty display RAM addresses
Table 14. Device-select command bit descriptionSee Section 7.10.2. 0, 1see Table11
6 to 3 - 1100 fixed value
2 to 0 A[2:0] 000[1] 3 bit binary value, 0 to 7; transferred to the subaddress
counter to define oneof eight hardware subaddresses
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
[2] Default value.
[1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
[2] Default value.
[3] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
7.13 Display controllerThe display controller executes the commands identified by the command decoder. It
contains the device’s status registers and coordinates their effects. The display controller
is also responsible for loading display data into the display RAM in the correct filling order.
Table 15. Bank-select command bit descriptionSee Section 7.10.5 and Section 7.10.6. C 0, 1 see Table11
6 to 2 - 11110 fixed value
input bank selection; storage of arriving display data[2] RAM row 0 RAM rows 0 and 1 RAM row 2 RAM rows 2 and 3
output bank selection; retrieval of LCD display data[2] RAM row 0 RAM rows 0 and 1 RAM row 2 RAM rows 2 and 3
Table 16. Blink-select command bit descriptionSee Section 7.11. 0, 1see Table11
6 to 3 - 1110 fixed value
2AB
blink mode selection[2] normal blinking[1] alternate RAM bank blinking[3]
1 to 0 BF[1:0]
blink frequency selection[2] off 1 2 3
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
8. Characteristics of the I2 C-busThe I2 C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transferOne data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 14).
8.1.1 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S. LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P.
The START and STOP conditions are illustrated in Figure 15.
8.2 System configurationA device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 16.
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
8.3 AcknowledgeThe number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2 C-bus is illustrated in Figure 17.
NXP Semiconductors PCF8576D
Universal LCD driver for low multiplex rates
8.4I2 C-bus controllerThe PCF8576D acts as an I2 C-bus slave receiver. It does not initiate I2 C-bus transfers or
transmit data to an I2 C-bus master receiver. The only data output from the PCF8576D are
the acknowledge signals of the selected devices. Device selection depends on the 2 C-bus slave address, on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress inputs A0, A1, and A2 are
normally tied to VSS which defines the hardware subaddress 0. In multiple device
applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme, so that
no two devices with a common I2 C-bus slave address have the same hardware
subaddress.
8.5 Input filtersTo enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.6I2 C-bus protocolTwo I2 C-bus slave addresses (0111 000 and 0111 001) are used to address the
PCF8576D. The entire I2 C-bus slave address byte is shown in Table 17.
The PCF8576D is a write-only device and will not respond to a read access, therefore bit
0 should always be logic 0. Bit 1 of the slave address byte that a PCF8576D will respond
to, is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).
Having two reserved slave addresses allows the following on the same I2 C-bus:
Up to 16 PCF8576D for very large LCD applications
The use of two types of LCD multiplex drive
The I2 C-bus protocol is shown in Figure 18. The sequence is initiated with a START
condition (S) from the I2 C-bus master which is followed by one of two possible PCF8576D
slave addresses available. All PCF8576Ds whose SA0 inputs correspond to bit 0 of the
slave address respond by asserting an acknowledge in parallel. This I2 C-bus transfer is
ignored by all PCF8576Ds whose SA0 inputs are set to the alternative level.
Table 17.I2 C slave address byte 11 00 SA0 R/W
