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PCF8578T
LCD row/column driver for dot matrix graphic displays
General descriptionThe PCF8578 is a low power CMOS1 LCD row and column driver, designed to drive dot
matrix graphic displays at multiplex rates of 1:8, 1:16, 1:24 or 1:32. The device has outputs, of which 24 are programmable and configurable for the following ratios of
rows/columns:32⁄8,24⁄16,16 ⁄24 or8 ⁄32. The PCF8578 can function as a stand-alone LCD
controller and driver for use in small systems. For larger systems it can be used in
conjunction with up to 32 PCF8579s for which it has been optimized. Together these two
devices forma general purpose LCD dot matrix driver chip set, capableof driving displays
of up to 40960 dots. The PCF8578 is compatible with most microcontrollers and
communicates via a two-line bidirectional bus (I2 C-bus). Communication overhead is
minimized by a display RAM with auto-incremented addressing and display bank
switching.
Features Single chip LCD controller and driver Stand-alone or may be used with up to 32 PCF8579s (40960 dots possible) 40 driver outputs, configurablefor several ratiosof rows/columns:32⁄8,24⁄16,16⁄24or8⁄32 Selectable multiplex rates: 1:8, 1:16, 1:24 or 1:32 Externally selectable bias configuration, 5 or 6 levels 1280-bit RAM for display data storage and scratch pad Display memory bank switching Auto-incremented data loading across hardware subaddress boundaries (with
PCF8579) Provides display synchronization for PCF8579 On-chip oscillator, requires only 1 external resistor Power-On Reset (POR) blanks display Logic voltage supply range 2.5Vto6V Maximum LCD supply voltage 9V Low power consumptionI2 C-bus interface Compatible with most microcontrollers Optimized pinning for single plane wiring in multiple device applications (with
PCF8579) Space saving 56-lead small outline package and 64 pin quad flat pack
PCF8578
LCD row/column driver for dot matrix graphic displays
Rev. 06 — 5 May 2009 Product data sheet The definition of the abbreviations and acronyms used in this data sheet can be found in Section15.
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays Applications Automotive information systems Telecommunication systems Point-of-sale terminals Industrial computer terminals Instrumentation
Ordering information[1] Should not be used for new designs.
Marking
Table 1. Ordering informationPCF8578T/1 VSO56 plastic very small outline package; 56 leads SOT190-1
PCF8578H/1 LQFP64 plastic low profile quad flat package; 64 leads; body×10× 1.4 mm[1] SOT314-2
PCF8578HT/1 TQFP64 plastic thin quad flat package; 64 leads;
body10×10× 1.0 mm
SOT357-1
Table 2. Marking codesPCF8578T/1 PCF8578T
PCF8578H/1 PCF8578H
PCF8578HT/1 PCF8578HT
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays Block diagram
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays Pinning information
7.1 Pinning
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays
7.2 Pin description[1] The TEST pin must be connected to VSS.
Table 3. Pin descriptionSDA 1 7 I2 C-bus serial data input/output
SCL 2 8 I2 C-bus serial clock input
SYNC 3 9 cascade synchronization output
CLK 4 10 external clock input/output
VSS 5 11 ground
TEST[1] 6 12 test pin
SA0 7 13 I2 C-bus slave address input (bit0)
OSC 8 16 oscillator input
VDD 9 20 supply voltage
V2 to V5 10to13 21to24 LCD bias voltage inputs
VLCD 14 25 LCD supply voltage
n.c. 15, 16 14, 15,to 19,to 28, 36,
not connected
C39 to C32 17to24 29to 35, 37 LCD column driver outputs
R31/C31 to R8/C8 25to48 38to 46,to62
LCD row and column driver outputs
R7 to R0 49to56 63, 64, 1to6 LCD row driver outputs
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays Functional description
8.1 Display configurationsThe PCF8578 row and column driver is designed for use in one of three ways:
Stand-alone row and column driver for small displays (mixed mode)
Row and column driver with cascaded PCF8579s (mixed mode)
Row driver with cascaded PCF8579s (mixed mode and row mode)
[1] Using 15 PCF8579s.
[2] Using 16 PCF8579s.
In mixed mode, the device functions as both a row and column driver. It can be used in
small stand-alone applications, or for larger displays with up to 15 PCF8579s
(31 PCF8579s when two slave addresses are used). See Table 4 for common display
configurations.
In row mode, the device functions as a row driver with up to 32 row outputs and provides
the clock and synchronization signalsfor the PCF8579. Upto16 PCF8579s can normally
be cascaded (32 when two slave addresses are used).
Timing signals are derived from the on-chip oscillator, whose frequency is determined by
the value of the resistor connected between pin OSC and pin VSS.
Five commands are available to configure and control the operation of the device.
Communication is made via a two-line bidirectional I2 C-bus. The device may have one of
two slave addresses. The only difference between these slave addresses is the least
significant bit, which is set by the logic level applied to SA0. The PCF8578 and PCF8579
have different subaddresses. The subaddress of the PCF8578 is only defined in mixed
mode and is fixed at 0111 100 (see Section 8.8.7 on page 19). The RAM may only be
accessed in mixed mode and data is loaded as described for the PCF8579.
Bias levels maybe generatedbyan external potential divider with appropriate decoupling
capacitors. For large displays, bias sources with high drive capability should be used. A
typical mixed mode system operating with up to 15 PCF8579s is shown in Figure 5 (a
stand-alone system would be identical but without the PCF8579).
Table 4. Possible display configurationsstand alone 1:8 8 32 - - small digital or
alphanumeric displays1:16 16 24 - -
1:24 24 16 - -
1:32 32 8 - -
with
PCF8579
1:8 8[1] 632[1] 8×4[2] 640[2] alphanumeric displays
and dot matrix graphic
displays1:16 16[1] 624[1] 16×2[2] 640[2]
1:24 24[1] 616[1] 24[2] 640[2]
1:32 32[1] 608[1] 32[2] 640[2]
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NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displaysTable 5 shows the relative values of the resistors required in the configuration of Figure5
to produce the standard multiplex rates.
8.2 Power-on resetAt power-on the PCF8578 resets to a defined starting condition as follows: Display blank 1:32 multiplex rate, row mode Start bank 0 selected Data pointer is set to X, Y address0,0 Character mode Subaddress counter is set to 0I2 C-bus interface is initialized
Remark: Do not transfer data on the I2 C-bus for at least 1 ms after power-on to allow the
reset action to complete.
8.3 Multiplexed LCD bias generationThe bias levels required to produce maximum contrast depend on the multiplex rate and
the LCD threshold voltage (Vth). Vth is typically defined as the RMS voltage at which the
LCD exhibits 10 % contrast.T able 6 shows the optimum voltage bias levels and Table7
the discrimination ratios (D) for the different multiplex rates as functions of Voper.
(1)
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with the equation
(2)
and the RMS off-state voltage (Voff(RMS)) with the equation
(3)
Table 5. Multiplex rates and resistor values for Figure5 R R R– ()R– ()R– ()R oper VDD V LCD–=on RMS()Voper=off RMS()Voper=
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displayswhere the values for n are determined by the multiplex rate (1:n). Valid values for n are:= 8 for 1:8 multiplex= 16 for 1:16 multiplex= 24 for 1:24 multiplex= 32 for 1:32 multiplex
Figure 6 shows the values of Table 6 as graphs.
Table 6. Optimum LCD voltages0.739 0.800 0.830 0.850
0.522 0.600 0.661 0.700
0.478 0.400 0.339 0.300
0.261 0.200 0.170 0.150
Table 7. Discrimination ratios0.297 0.245 0.214 0.193
0.430 0.316 0.263 0.230
1.447 1.291 1.230 1.196
3.370 4.080 4.680 5.1902 oper
--------------3 oper
--------------4 oper
--------------5 oper
--------------off RMS() oper
-------------------------on RMS() oper
----------------------- operth
--------------
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays
8.4 LCD drive mode waveforms
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays
8.5 Oscillator
8.5.1 Internal clockThe clock signalfor the system maybe generatedby the internal oscillator and prescaler.
The frequency is determined by the value of the resistor Rext(OSC), see Figure 10. For
normal use a value of 330 kΩ is recommended. The clock signal, for cascaded
PCF8579s,is outputat CLK and hasa frequencyof1⁄6 (multiplex rate 1:8, 1:16 and 1:32)1 ⁄8 (multiplex rate 1:24) of the oscillator frequency.
8.5.2 External clockIf an external clock is used, OSC must be connected to VDD and the external clock signal
to CLK. Table 8 summarizes the nominal CLK and SYNC frequencies.
[1] A clock signal must always be present, otherwise the LCD may be frozen in a DC state.
[2] Rext(OSC)= 330kΩ.
8.6 Timing generatorThe timing generator of the PCF8578 organizes the internal data flow of the device and
generates the LCD frame synchronization pulse SYNC, whose period is an integer
multiple of the clock period. In cascaded applications, this signal maintains the correct
timing relationship between the PCF8578 and PCF8579s in the system.
Table 8. Signal frequencies required for nominal 64 Hz frame frequency[1]12288 64 1:8, 1:16, 1:326 2048
12288 64 1:24 8 1536
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays
8.7 Row and column driversOutputs R0to R7 and C32to C39 are fixed as row and column drivers respectively. The
remaining 24 outputs R8/C8to R31/C31 are programmable and may be configured (in
blocks of 8) to be either row or column drivers. The row select signal is produced
sequentially at each output from R0 up to the number defined by the multiplex rate (see
Table 4).In mixed mode the remaining outputs are configuredas columns.In row modeall
programmable outputs (R8/C8to R31/C31) are defined as row drivers and the outputs
C32to C39 should be left open-circuit.
Usinga 1:16 multiplex rate, two setsof row outputs are driven, thus facilitating split-screen
configurations, i.e.a row select pulse appears simultaneouslyat R0 and R16/C16, R1 and
R17/C17 etc. Similarly, using a multiplex rate of 1:8, four sets of row outputs are driven
simultaneously. Driver outputs must be connected directly to the LCD. Unused outputs
should be left open circuit.
Depending on the multiplex rate the following outputs are rows:
In MUX 1:8 R0to R7
In MUX 1:16 R0to R15/C15
In MUX 1:24 R0to R23/C23
In MUX 1:32 R0to R31/C31
The configuration of the outputs (row or column) and the selection of the appropriate
driver waveforms are controlled by the display mode controller.
8.8 Characteristics of the I2 C-busTheI2 C-busisfor bidirectional, two-line communication between different ICsor modules.
The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL) which must be
connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
8.8.1 Bit transferOne databitis transferred during each clock pulse. The dataon the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this
moment will be interpreted as control signals.
8.8.2 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is defined as the START condition (S). LOW-to-HIGH transitionof the data line while the clockis HIGH,is definedas the STOP
condition (P).
8.8.3 System configurationA device transmitting a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message flow is the master and the devices which
are controlled by the master are the slaves.
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays
8.8.4 AcknowledgeThe number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each data byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generatesan extra acknowledge related clock pulse.A slave receiver
which is addressed must generate an acknowledge after the reception of each byte. Also
a master must generate an acknowledge after the reception of each byte that has been
clocked out of the slave transmitter. The device that acknowledges must pull down the
SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge related clock pulse (set-up and hold times must be
taken into consideration).A master receiver must signal the endofa data transmissionto
the transmitter by
not generating an acknowledge on the last byte that has been clockedout of the slave. In this event the transmitter must leave the data line HIGH to enable the
master to generate a STOP condition.
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays
8.8.5I2 C-bus controllerTheI2 C-bus controller detects theI2 C-bus protocol, slave address, commands and display
data bytes. It performs the conversion of the data input (serial-to-parallel) and the data
output (parallel-to-serial). The PCF8578 acts as an I2 C-bus slave transmitter/receiver in
mixed mode, and as a slave receiver in row mode. A slave device cannot control bus
communication.
8.8.6 Input filtersTo enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.8.7I2 C-bus protocolTwo 7-bit slave addresses (0111 100 and 0111 101) are reserved for both the PCF8578
and PCF8579. The least significantbitof the slave addressis setby connecting input SA0 either logic0 (VSS)or logic1 (VDD). Therefore, two typesof PCF8578or PCF8579 can
be distinguished on the same I2 C-bus which allows: One PCF8578to operate withupto32 PCF8579son the sameI2 C-busfor very large
applications. The use of two types of LCD multiplex schemes on the same I2 C-bus.
In most applications the PCF8578 will have the same slave address as the PCF8579.
TheI2 C-bus protocolis shownin Figure 15.All communications are initiated witha START
condition (S) from theI2 C-bus master, whichis followedby the desired slave address and
read/write bit.All devices with this slave address acknowledgein parallel.All other devices
ignore the bus transfer.
In WRITE mode (indicated by setting the read/write bit LOW) one or more commands
follow the slave address acknowledgement. The commands are also acknowledgedbyall
addressed devices on the bus. The last command must clear the continuation bitC.
After the last command a series of data bytes may follow. The acknowledgement after
each byteis made onlyby the (A0, A1, A2 and A3) addressed PCF8579or PCF8578 with
its implicit subaddress 0. After the last data byte has been acknowledged, the I2 C-bus
master issues a STOP condition (P).
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays READ mode, indicatedby setting the read/writebit HIGH, data bytes maybe read from
the RAM following the slave address acknowledgement. After this acknowledgement the
master transmitter becomes a master receiver and the PCF8578 becomes a slave
transmitter. The master receiver must acknowledge the receptionof each bytein turn. The
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displaysmaster receiver must signal an end of data to the slave transmitter, by not generating an
acknowledge on the last byte clocked out of the slave. The slave transmitter then leaves
the data line HIGH, enabling the master to generate a STOP condition (P).
Display bytes are written into, or read from the RAM at the address specified by the data
pointer and subaddress counter. Both the data pointer and subaddress counter are
automatically incremented, enabling a stream of data to be transferred either to, or from
the intended devices. multiple device applications, the hardware subaddress pinsof the PCF8579s (A0to A3)
are connectedto VSSor VDDto represent the desired hardware subaddress code.If twoor
more devices share the same slave address, then each device
must be allocated to aunique hardware subaddress.
8.9 Display RAMThe PCF8578 contains a 32× 40-bit static RAM which stores the display data. The RAM
is divided into 4 banks of40 bytes(4×8×40 bits). During RAM access, data is
transferred to and from the RAM via the I2 C-bus. The first eight columns of data (0to7)
cannot be displayed but are available for general data storage and provide compatibility
with the PCF8579. There is a direct correspondence between X-address and column
output number.
8.9.1 Data pointerThe addressing mechanism for the display RAM is realized using the data pointer. This
allowsan individual data byteora seriesof data bytestobe written into,or read from, the
display RAM, controlled by commands sent on the I2 C-bus.
8.9.2 Subaddress counterThe storage and retrieval of display data is dependent on the content of the subaddress
counter. Storage takes place only when the contents of the subaddress counter match
with the hardware subaddress. The hardware subaddressof the PCF8578, validin mixed
mode only, is fixed at 0000.
8.10 Command decoderThe command decoder identifies command bytes that arrive on the I2 C-bus.
The five commands available to the PCF8578 are defined in Table9.
The most-significant bit of a command is the continuation bit C (see Table 10 and
Figure 16). Commands are transferred in WRITE mode only.
Table 9. Definition of PCF8578 commands
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays
Table 10. C bit description C continue bit last control byte in the transfer; next byte will be regarded
as display data control bytes continue; next byte will be a command too
Table 11. Set-mode - command bit description C 0, 1 see Table10
6, 5 - 10 fixed value T display mode row mode mixed mode
3, 2 E[1:0] display status blank normal all segments on inverse video
1, 0 M[1:0] LCD drive mode 1:8 MUX (8 rows) 1:16 MUX (16 rows) 1:24 MUX (24 rows) 1:32 MUX (32 rows)
NXP Semiconductors PCF8578
LCD row/column driver for dot matrix graphic displays[1] Useful for scrolling, pseudo-motion and background preparation of new display content.
[1] Values shown in decimal.
[1] See operation code for set-start-bank in Table12.
[2] Values shown in decimal.
Table 12. Set-start-bank - command bit description C 0, 1 see Table10
6 to 2 - 11111 fixed value
1, 0 B[1:0] start bank pointer (see Figure 20)[1] bank 0 bank 1 bank 2 bank 3
Table 13. Device-select - command bit description C 0, 1 see Table10
6 to 4 - 110 fixed value
3 to 0 A[3:0] 0 to 15[1] hardware subaddress;
4 bit binary value; transferred to the subaddress
counter to define oneof sixteen hardware
subaddresses
Table 14. RAM-access - command bit description C 0, 1 see Table10
6 to 4 - 111 fixed value
3, 2 G[1:0] RAM access mode;
defines the auto-increment behavior of the
address for RAM access (see Figure 18) character half-graphic full-graphic not allowed[1]
1, 0 Y[1:0] 0 to 3[2] RAM row address;
two bits of immediate data, transferred to the
Y-address pointer to define one of four display
RAM rows (see Figure 17)
