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PCF8583P-PCF8583T-PCF8583T-
Clock/calendar with 240 x 8-bit RAM
Philips Semiconductors Product specification
Clock/calendar with 240×
8-bit RAM PCF8583
CONTENTS FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION
7.1 Counter function modes
7.2 Alarm function modes
7.3 Control/status register
7.4 Counter registers
7.5 Alarm control register
7.6 Alarm registers
7.7 Timer
7.8 Event counter mode
7.9 Interrupt output
7.10 Oscillator and divider
7.11 Initialization CHARACTERISTICS OF THE I2 C-BUS
8.1 Bit transfer
8.2 Start and stop conditions
8.3 System configuration
8.4 Acknowledge2 C-BUS PROTOCOL
9.1 Addressing
9.2 Clock/calendar READ/WRITE cycles LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION
14.1 Quartz frequency adjustment
14.1.1 Method 1: fixed osci capacitor
14.1.2 Method 2: OSCI Trimmer
14.1.3 Method 3: PACKAGE OUTLINES SOLDERING
16.1 Introduction
16.2 DIP
16.2.1 Soldering by dipping or by wave
16.2.2 Repairing soldered joints
16.3 SO
16.3.1 Reflow soldering
16.3.2 Wave soldering
16.3.3 Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
Philips Semiconductors Product specification
Clock/calendar with 240× 8-bit RAM PCF8583
FEATURESI2 C-bus interface operating supply voltage: 2.5 V to 6 V Clock operating supply voltage (0to +70 °C):
1.0 V to 6.0 V 240× 8-bit low-voltage RAM Data retention voltage: 1.0 V to 6 V Operating current (at fSCL = 0 Hz): max. 50μA Clock function with four year calendar Universal timer with alarm and overflow indication 24or12 hour format 32.768 kHz or 50 Hz time base Serial input/output bus (I2C) Automatic word address incrementing Programmable alarm, timer and interrupt function Slave address: READ: A1 or A3 WRITE: A0 or A2.
GENERAL DESCRIPTIONThe PCF8583 is a clock/calendar circuit based on a
2048-bit static CMOS RAM organized as 256 words by bits. Addresses and data are transferred serially via the
two-line bidirectional I2C-bus. The built-in word address
register is incremented automatically after each written or
read data byte. Address pin A0 is used for programming
the hardware address, allowing the connection of two
devices to the bus without additional hardware.
The built-in 32.768 kHz oscillator circuit and the first bytes of the RAM are used for the clock/calendar and
counter functions. The next 8 bytes may be programmed
as alarm registers or used as free RAM space.
The remaining 240 bytes are free RAM locations.
QUICK REFERENCE DATA ORDERING INFORMATION
Philips Semiconductors Product specification
Clock/calendar with 240× 8-bit RAM PCF8583
BLOCK DIAGRAM PINNING
Philips Semiconductors Product specification
Clock/calendar with 240× 8-bit RAM PCF8583 FUNCTIONAL DESCRIPTION
The PCF8583 contains a 256 by 8-bit RAM with an 8-bit
auto-increment address register, an on-chip 32.768 kHz
oscillator circuit, a frequency divider, a serial two-line
bidirectional I2C-bus interface and a power-on reset circuit.
The first 16 bytes of the RAM (memory addressesto 0F) are designed as addressable 8-bit parallel
special function registers. The first register (memory
address 00) is used as a control/status register.
The memory addresses 01to 07 are used as counters for
the clock function. The memory addresses 08to 0F may
be programmed as alarm registers or used as free RAM
locations, when the alarm is disabled.
7.1 Counter function modes
When the control/status register is programmed, a
32.768 kHz clock mode, a 50 Hz clock mode or an
event-counter mode can be selected.
In the clock modes the hundredths of a second, seconds,
minutes, hours, date, month (four year calendar) and
weekday are stored in a BCD format. The timer register
stores up to 99 days. The event counter mode is used to
count pulses applied to the oscillator input (OSCO left
open-circuit). The event counter stores up to 6 digits of
data.
When one of the counters is read (memory locationsto 07), the contents of all counters are strobed into
capture latches at the beginning of a read cycle. Therefore,
faulty reading of the count during a carry condition is
prevented.
When a counter is written, other counters are not affected.
7.2 Alarm function modes
By setting the alarm enable bit of the control/status register
the alarm control register (address 08) is activated.
By setting the alarm control register a dated alarm, a daily
alarm, a weekday alarm or a timer alarm may be
programmed. In the clock modes, the timer register
(address 07) may be programmed to count hundredths of
a second, seconds, minutes, hours or days. Days are
counted when an alarm is not programmed.
Whenever an alarm event occurs the alarm flag of the
control/status register is set. A timer alarm event will set
the alarm flag and an overflow condition of the timer will set
the timer flag. The open drain interrupt output is switched
on (active LOW) when the alarm or timer flag is set
(enabled). The flags remain set until directly reset by a
write operation.
When the alarm is disabled (Bit 2 of control/status
register= 0) the alarm registers at addresses 08to0F
may be used as free RAM.
7.3 Control/status register
The control/status register is defined as the memory
location 00 with free access for reading and writing via the2 C-bus. All functions and options are controlled by the
contents of the control/status register (see Fig.3).
7.4 Counter registers
In the clock modes 24 h or 12 h format can be selected by
setting the most significant bit of the hours counter
register. The format of the hours counter is shown in Fig.5.
The year and date are packed into memory location 05
(see Fig.6). The weekdays and months are packed into
memory location 06 (see Fig.7). When reading these
memory locations the year and weekdays are masked out
when the mask flag of the control/status register is set.
This allows the user to read the date and month count
directly.
In the event-counter mode events are stored in BCD
format. D5 is the most significant and D0 the least
significant digit. The divider is by-passed.
In the different modes the counter registers are
programmed and arranged as shown in Fig.4. Counter
cycles are listed in Table1.
Philips Semiconductors Product specification
Clock/calendar with 240× 8-bit RAM PCF8583
Philips Semiconductors Product specification
Clock/calendar with 240× 8-bit RAM PCF8583
Philips Semiconductors Product specification
Clock/calendar with 240× 8-bit RAM PCF8583
Philips Semiconductors Product specification
Clock/calendar with 240× 8-bit RAM PCF8583
Table 1 Cycle length of the time counters, clock modes
7.5 Alarm control register
When the alarm enable bit of the control/status register is
set (address 00, bit 2) the alarm control register (address
08) is activated. All alarm, timer, and interrupt output
functions are controlled by the contents of the alarm
control register (see Fig.8).
7.6 Alarm registers
All alarm registers are allocated with a constant address
offset of hexadecimal 08 to the corresponding counter
registers (see Fig.4, Register arrangement).
An alarm signal is generated when the contents of the
alarm registers matches bit-by-bit the contents of the
involved counter registers. The year and weekday bits are
ignored in a dated alarm. A daily alarm ignores the month
and date bits. When a weekday alarm is selected, the
contents of the alarm weekday/month register will select
the weekdays on which an alarm is activated (see Fig.9).
Remark: In the 12 h mode, bits 6 and 7 of the alarm hours
register must be the same as the hours counter.
Philips Semiconductors Product specification
Clock/calendar with 240× 8-bit RAM PCF8583
Philips Semiconductors Product specification
Clock/calendar with 240× 8-bit RAM PCF8583
7.7 Timer
The timer (location 07) is enabled by setting the
control/status register = XX0X X1XX. The timer counts up
from 0 (or a programmed value) to 99. On overflow, the
timer resets to 0. The timer flag (LSB of control/status
register) is set on overflow of the timer. This flag must be
reset by software. The inverted value of this flag can be
transferred to the external interrupt by setting bit 3 of the
alarm control register.
Additionally, a timer alarm can be programmed by setting
the timer alarm enable (bit 6 of the alarm control register).
When the value of the timer equals a pre-programmed
value in the alarm timer register (location 0F), the alarm
flag is set (bit 1 of the control/status register). The inverted
value of the alarm flag can be transferred to the external
interrupt by enabling the alarm interrupt (bit 6 of the alarm
control register).
Resolution of the timer is programmed via the 3 LSBs of
the alarm control register (see Fig.11, Alarm and timer
Interrupt logic diagram).
7.8 Event counter mode
Event counter mode is selected by bits 4 and 5 which are
logic1, 0 in the control/status register. The event counter
mode is used to count pulses externally applied to the
oscillator input (OSCO left open-circuit).
The event counter stores up to 6 digits of data, which are
stored as 6 hexadecimal values located in locations1,2,
and 3. Thus, up to 1 million events may be recorded.
An event counter alarm occurs when the event counter
registers match the value programmed in locations 9, A,
and B, and the event alarm is enabled (bits 4 and 5 which
are logic0, 1 in the alarm control register). In this event,
the alarm flag (bit 1 of the control/status register) is set.
The inverted value of this flag can be transferred to the
interrupt pin (pin 7) by setting the alarm interrupt enable in
the alarm control register. In this mode, the timer
(location 07) increments once for every one, one-hundred,
ten thousand, or 1 million events, depending on the value
programmed in bits0, 1 and 2 of the alarm control register.
In all other events, the timer functions are as in the clock
mode.
7.9 Interrupt output
The conditions for activating the open-drain n-channel
interrupt output INT (active LOW) are determined by
appropriate programming of the alarm control register.
These conditions are clock alarm, timer alarm, timer
overflow, and event counter alarm. An interrupt occurs
when the alarm flag or the timer flag is set, and the
corresponding interrupt is enabled. In all events, the
interrupt is cleared only by software resetting of the flag
which initiated the interrupt.
Philips Semiconductors Product specification
Clock/calendar with 240× 8-bit RAM PCF8583
In the clock mode, if the alarm enable is not activated
(alarm enable bit of control/status register is logic 0), the
interrupt output toggles at 1 Hz with a 50% duty cycle (may
be used for calibration). This is the default power-on state
of the device. The OFF voltage of the interrupt output may
exceed the supply voltage, up to a maximum of 6.0V.
A logic diagram of the interrupt output is shown in Fig.11.
7.10 Oscillator and divider
A 32.768 kHz quartz crystal has to be connected to OSCI
(pin 1) and OSCO (pin 2). A trimmer capacitor between
OSCI and VDD is used for tuning the oscillator (see quartz
frequency adjustment). A 100 Hz clock signal is derived
from the quartz oscillator for the clock counters.
In the 50 Hz clock mode or event-counter mode the
oscillator is disabled and the oscillator input is switched to
a high impedance state.
This allows the user to feed the 50 Hz reference frequency
or an external high speed event signal into the input OSCI.
7.11 Initialization
When power-up occurs the I2 C-bus interface, the
control/status register and all clock counters are reset.
The device starts time-keeping in the 32.768 kHz clock
mode with the 24 h format on the first of January at
0.00.00: 00. A 1 Hz square wave with 50% duty cycle
appears at the interrupt output pin (starts HIGH).
It is recommended to set the stop counting flag of the
control/status register before loading the actual time into
the counters. Loading of illegal states may lead to a
temporary clock malfunction.
Philips Semiconductors Product specification
Clock/calendar with 240× 8-bit RAM PCF8583
Philips Semiconductors Product specification
Clock/calendar with 240× 8-bit RAM PCF8583 CHARACTERISTICS OF THE I2C-BUS
The I2 C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data
transfer may be initiated only when the bus is not busy.
8.1 Bit transfer (see Fig.12)
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period
of the clock pulse as changes in the data line at this time will be interpreted as a control signal.
8.2 Start and stop conditions (see Fig.13)
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is
defined as the stop condition (P).
