PCF8584T ,I2C-bus controllerINTEGRATED CIRCUITSDATA SHEETPCF85842I C-bus controller1997 Oct 21Product specificationSupersedes da ..
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Philips Semiconductors Product specification2 C-bus controller PCF8584
CONTENTS FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION
6.1 General
6.2 Interface Mode Control (IMC)
6.3 Set-up registers S0', S2 and S3
6.4 Own address register S0'
6.5 Clock registerS2
6.6 Interrupt vectorS3
6.7 Data shift register/read bufferS0
6.8 Control/status registerS1
6.8.1 Register S1 control section
6.8.1.1 PIN (Pending Interrupt Not)
6.8.1.2 ESO (Enable Serial Output)
6.8.1.3 ES1 and ES2
6.8.1.4 ENI
6.8.1.5 STA and STO
6.8.1.6 ACK
6.8.2 Register S1 status section
6.8.2.1 PIN bit
6.8.2.2 STS
6.8.2.3 BER
6.8.2.4 LRB/AD0
6.8.2.5 AAS
6.8.2.6 LAB
6.8.2.7 BB
6.9 Multi-master operation
6.10 Reset
6.11 Comparison to the MAB8400 I2 C-bus interface
6.11.1 Deleted functions
6.11.2 added functions
6.12 Special function modes
6.12.1 Strobe
6.12.2 Long-distance mode
6.12.3 Monitor mode SOFTWARE FLOWCHART EXAMPLES
7.1 Initialization
7.2 Implementation2 C-BUS TIMING DIAGRAMS LIMITING VALUES HANDLING DC CHARACTERISTICS I2C-BUS TIMING SPECIFICATIONS PARALLEL INTERFACE TIMING APPLICATION INFORMATION
14.1 Application Notes PACKAGE OUTLINES SOLDERING
16.1 Introduction
16.2 DIP
16.2.1 Soldering by dipping or by wave
16.2.2 Repairing soldered joints
16.3 SO
16.3.1 Reflow soldering
16.3.2 Wave soldering
16.3.3 Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2 C COMPONENTS
Philips Semiconductors Product specification2 C-bus controller PCF8584
FEATURES Parallel-bus to I2 C-bus protocol converter and interface Compatible with most parallel-bus
microcontrollers/microprocessors including 8049, 8051,
6800, 68000 and Z80 Both master and slave functions Automatic detection and adaption to bus interface type Programmable interrupt vector Multi-master capabilityI2 C-bus monitor mode Long-distance mode (4-wire) Operating supply voltage 4.5to 5.5V Operating temperature range: −40to +85 °C.
GENERAL DESCRIPTIONThe PCF8584 is an integrated circuit designed in CMOS
technology which serves as an interface between most
standard parallel-bus microcontrollers/microprocessors
and the serial I2C-bus. The PCF8584 provides both master
and slave functions.
Communication with the I2 C-bus is carried out on a
byte-wise basis using interrupt or polled handshake.
It controls all the I2C-bus specific sequences, protocol,
arbitration and timing. The PCF8584 allows parallel-bus
systems to communicate bidirectionally with the I2 C-bus.
ORDERING INFORMATION
Philips Semiconductors Product specification2 C-bus controller PCF8584
BLOCK DIAGRAM
Philips Semiconductors Product specification2 C-bus controller PCF8584
PINNING
Philips Semiconductors Product specification2 C-bus controller PCF8584 FUNCTIONAL DESCRIPTION
6.1 General
The PCF8584 acts as an interface device between
standard high-speed parallel buses and the serial I2 C-bus.
On the I2 C-bus, it can act either as master or slave.
Bidirectional data transfer between the I2 C-bus and the
parallel-bus microcontroller is carried out on a byte-wise
basis, using either an interrupt or polled handshake.
Interface to either 80XX-type (e.g. 8048, 8051, Z80) or
68000-type buses is possible. Selection of bus type is
automatically performed (see Section 6.2).
Table 1 Control signals utilized by the PCF8584 for
microcontroller/microprocessor interfacing
The structure of the PCF8584 is similar to that of the2 C-bus interface section of the Philips’
MABXXXX/PCF84(C)XX-series of microcontrollers, but
with a modified control structure. The PCF8584 has five
internal register locations. Three of these (own address
register S0', clock register S2 and interrupt vector S3) are
used for initialization of the PCF8584. Normally they are
only written once directly after resetting of the PCF8584.
The remaining two registers function as double registers
(data buffer/shift register S0, and control/status
register S1) which are used during actual data
transmission/reception. By using these double registers,
which are separately write and read accessible, overhead
for register access is reduced. Register S0 is a
combination of a shift register and data buffer.
Register S0 performs all serial-to-parallel interfacing with
the I2 C-bus.
Register S1 contains I2 C-bus status information required
for bus access and/or monitoring.
6.2 Interface Mode Control (IMC)
Selection of either an 80XX mode or 68000 mode
interface is achieved by detection of the first WR-CS signal
sequence. The concept takes advantage of the fact that
the write control input is common for both types of
interfaces. An 80XX-type interface is default. If a
HIGH-to-LOW transition ofWR (R/W) is detected while CS
is HIGH, the 68000-type interface mode is selected and
the DTACK output is enabled. Care must be taken thatWR
and CS are stable after reset.
Philips Semiconductors Product specification2 C-bus controller PCF8584
Philips Semiconductors Product specification2 C-bus controller PCF8584
6.3 Set-up registers S0', S2 and S3
Registers S0', S2 and S3 are used for initialization of the
PCF8584 (see Fig.5 ‘Initialization sequence’ flowchart).
6.4 Own address register S0'
When the PCF8584 is addressed as slave, this register
must be loaded with the 7-bit I2C-bus address to which the
PCF8584 is to respond. During initialization, the own
address register S0' must be written to, regardless
whether it is later used. The Addressed As Slave (AAS) bit
in status register S1 is set when this address is received
(the value in S0 is compared with the value in S0'). Note
that the S0 and S0' registers are offset by one bit; hence,
programming the own address register S0' with a value of
55H will result in the value AAH being recognized as the
PCF8584’s slave address (see Fig.1).
Programming of S0' is accomplished via the parallel-bus
when A0 is LOW, with the appropriate bit combinations set
in control status register S1 (S1 is written when
pinA0= HIGH). Bit combinations for accessing all
registers are given in Table 5. After reset, S0' has default
address 00H (PCF8584 is thus initially in monitor mode,
see Section 6.12.3).
6.5 Clock registerS2
Register S2 provides control over chip clock frequency
and SCL clock frequency. S20 and S21 provide a selection
of 4 different I2 C-bus SCL frequencies which are shown in
Table 2. Note that these SCL frequencies are only
obtained when bits S24, S23 and S22 are programmed to
the correct input clock frequency (fclk).
Table 2 Register S2 selection of SCL frequency
S22, S23 and S24 are used for control of the internal clock
prescaler. Due to the possibility of varying microcontroller
clock signals, the prescaler can be programmed to adapt
to 5 different clock rates, thus providing a constant internal
clock. This is required to provide a stable time base for the
SCL generator and the digital filters associated with the2 C-bus signals SCL and SDA. Selection for adaption to
external clock rates is shown in Table3.
Programming of S2 is accomplished via the parallel-bus
when A0= LOW, with the appropriate bit combinations set
in control status register S1 (S1 is written when= HIGH). Bit combinations for accessing all registers
are given in Table5.
Table 3 Register S2 selection of clock frequency
Note X= don’t care.
6.6 Interrupt vector S3
The interrupt vector register provides an 8-bit
user-programmable vector for vectored-interrupt
microcontrollers. The vector is sent to the bus port
(DB7to DB0) when an interrupt acknowledge signal is
asserted and the ENI (enable interrupt) flag is set. Default
vector values are: Vector is ‘00H’ in 80XX mode Vector is ‘0FH’ in 68000 mode.
On reset the PCF8584 is in the 80XX mode, thus the
default interrupt vector is ‘00H’.
6.7 Data shift register/read buffer S0
Register S0 acts as serial shift register and read buffer
interfacing to the I2 C-bus. All read and write operations
to/from the I2 C-bus are done via this register. S0 is a
combination of a shift register and a data buffer; parallel
data is always written to the shift register, and read from
the data buffer. I2C-bus data is always shifted in or out of
shift register S0.
Philips Semiconductors Product specification2 C-bus controller PCF8584
In receiver mode the data from the shift register is copied to the read buffer during the acknowledge phase. Further
reception of data is inhibited (SCL held LOW) until the S0 read buffer is read (see Section 6.8.1.1).
In the transmitter mode data is transmitted to the I2C-bus as soon as it is written to the S0 shift register if the serial I/O is
enabled (ESO=1).
Remarks: A minimum of 6 clock cycles must elapse between consecutive parallel-bus accesses to the PCF8584 when the2 C-bus controller operates at 8or12 MHz. This may be reduced to 3 clock cycles for lower operating frequencies. To start a read operation immediately after a write, it is necessary to read the S0 read buffer in order to invoke
reception of the first byte (‘dummy read’ of the address). Immediately after the acknowledgement, this first byte will
be transferred from the shift register to the read buffer. The next read will then transfer the correct value of the first
byte to the microcontroller bus (see Fig.7).
6.8 Control/status registerS1
Register S1 controls I2 C-bus operation and provides I2 C-bus status information. Register S1 is accessed by a HIGH
signal on register select input A0. For more efficient communication between microcontroller/processor and the I2 C-bus,
register S1 has separate read and write functions for all bit positions (see Fig.3). The write-only section provides register
access control and control over I2 C-bus signals, while the read-only section provides I2 C-bus status information.
Table 4 Control/status register S1
Notes For further information see Section 6.8.1. For further information see Section 6.8.2. Logic 1 if not-initialized.
Philips Semiconductors Product specification2 C-bus controller PCF8584
6.8.1 REGISTERS1 CONTROL SECTION
The write-only section of S1 enables access to registers S0, S0', S1, S2 and S3, and controls I2 C-bus operation; see
Table4.
6.8.1.1 PIN (Pending Interrupt Not)
When the PIN bit is written with a logic 1, all status bits are reset to logic 0. This may serve as a software reset function
(see Figs5to 9). PIN is the only bit in S1 which may be both read and written to. PIN is mostly used as a status bit for
synchronizing serial communication, see Section 6.8.2.
6.8.1.2 ESO (Enable Serial Output)
ESO enables or disables the serial I2 C-bus I/O. When ESO is LOW, register access for initialization is possible. When
ESO is HIGH, I2 C-bus communication is enabled; communication with serial shift register S0 is enabled and the S1 bus
status bits are made available for reading.
Table 5 Register access control; ESO= 0 (serial interface off) and ESO= 1 (serial interface on)
Notes With ESO= 0, bits ENI, STA, STO and ACK of S1 can be read for test purposes. ‘X’ if ENI=0.
6.8.1.3 ES1 and ES2
ES1 and ES2 control selection of other registers for initialization and control of normal operation. After these bits are
programmed for access to the desired register (shown in Table 5), the register is selected by a logic LOW level on
register select pin A0.
6.8.1.4 ENI
This bit enables the external interrupt output INT, which is generated when the PIN bit is active (logic0).
This bit must be set to logic 0 before entering the long-distance mode, and remain at logic 0 during operation in
long-distance mode.
Philips Semiconductors Product specification2 C-bus controller PCF8584
6.8.1.5 STA and STO
These bits control the generation of the I2 C-bus START condition and transmission of slave address and R/W bit,
generation of repeated START condition, and generation of the STOP condition (see Table7).
Table 6 Register access control; ESO= 1 (serial interface on) and ES1= 1; long-distance (4-wire) mode; note1
Note Trying to read from or write to registers other than S0 and S1 (setting ESO= 0) brings the PCF8584 out of the
long-distance mode.
Table 7 Instruction table for serial bus control
Notes In master receiver mode, the last byte must be terminated with ACK bit HIGH (‘negative acknowledge’). If both STA and STO are set HIGH simultaneously in master mode, a STOP condition followed by a START
condition+ address will be generated. This allows ‘chaining’ of transmissions without relinquishing bus control. All other STA and STO mode combinations not mentioned in Table 7 are NOPs.
6.8.1.6 ACK
This bit must be set normally to a logic 1. This causes the I2C-bus controller to send an acknowledge automatically after
each byte (this occurs during the 9th clock pulse). The bit must be reset (to logic 0) when the I2 C-bus controller is
operating in master/receiver mode and requires no further data to be sent from the slave transmitter. This causes a
negative acknowledge on the I2 C-bus, which halts further transmission from the slave device.
6.8.2 REGISTERS1 STATUS SECTION
The read-only section of S1 enables access to I2 C-bus status information; see Table4.
Philips Semiconductors Product specification2 C-bus controller PCF8584
6.8.2.1 PIN bit
‘Pending Interrupt Not’ (MSB of register S1) is a status flag
which is used to synchronize serial communication and is
set to logic 0 whenever the PCF8584 requires servicing.
The PIN bit is normally read in polled applications to
determine when an I2 C-bus byte transmission/reception is
completed. The PIN bit may also be written, see
Section 6.8.1.
Each time a serial data transmission is initiated (by setting
the STA bit in the same register), the PIN bit will be set to
logic 1 automatically (inactive). When acting as
transmitter, PIN is also set to logic 1 (inactive) each time
S0 is written. In receiver mode, the PIN bit is automatically
set to logic 1 (inactive) each time the data register S0 is
read.
After transmission or reception of one byte on the I2 C-bus clock pulses, including acknowledge), the PIN bit will be
automatically reset to logic 0 (active) indicating a complete
byte transmission/reception. When the PIN bit is
subsequently set to logic 1 (inactive), all status bits will be
reset to logic 0. PIN is also set to zero on a BER (bus error)
condition.
In polled applications, the PIN bit is tested to determine
when a serial transmission/reception has been completed.
When the ENI bit (bit 4 of write-only section of register S1)
is also set to logic 1 the hardware interrupt is enabled.
In this case, the PIN flag also triggers an external interrupt
(active LOW) via the INT output each time PIN is reset to
logic 0 (active).
When acting as slave transmitter or slave receiver, while
PIN= 0, the PCF8584 will suspend I2 C-bus transmission
by holding the SCL line LOW until the PIN bit is set to
logic 1 (inactive). This prevents further data from being
transmitted or received until the current data byte in S0 has
been read (when acting as slave receiver) or the next data
byte is written to S0 (when acting as slave transmitter).
PIN bit summary: The PIN bit can be used in polled applications to test
when a serial transmission has been completed. When
the ENI bit is also set, the PIN flag sets the external
interrupt via the INT output. Setting the STA bit (start bit) will set PIN= 1 (inactive). In transmitter mode, after successful transmission of
one byte on the I2 C-bus the PIN bit will be automatically
reset to logic 0 (active) indicating a complete byte
transmission. In transmitter mode, PIN is set to logic 1 (inactive) each
time register S0 is written. In receiver mode, PIN is set to logic 0 (active) on
completion of each received byte. Subsequently, the
SCL line will be held LOW until PIN is set to logic1. In receiver mode, when register S0 is read, PIN is set to
logic 1 (inactive). In slave receiver mode, an I2 C-bus STOP condition will
set PIN= 0 (active). PIN= 0 if a bus error (BER) occurs.
6.8.2.2 STS
When in slave receiver mode, this flag is asserted when an
externally generated STOP condition is detected (used
only in slave receiver mode).
6.8.2.3 BER
Bus error; a misplaced START or STOP condition has
been detected. Resets BB (to logic 1; inactive), sets
PIN= 0 (active).
6.8.2.4 LRB/AD0
‘Last Received Bit’ or ‘Address 0 (General Call) bit’. This
status bit serves a dual function, and is valid only while
PIN=0: LRB holds the value of the last received bit over the
I2C-bus while AAS= 0 (not addressed as slave).
Normally this will be the value of the slave
acknowledgement; thus checking for slave
acknowledgement is done via testing of the LRB. AD0; when AAS= 1 (‘Addressed As Slave’ condition),
the I2 C-bus controller has been addressed as a slave.
Under this condition, this bit becomes the ‘AD0’ bit and
will be set to logic 1 if the slave address received was
the ‘general call’ (00H) address, or logic 0 if it was the2 C-bus controller’s own slave address.
6.8.2.5 AAS
‘Addressed As Slave’ bit. Valid only when PIN= 0. When
acting as slave receiver, this flag is set when an incoming
address over the I2 C-bus matches the value in own
address register S0' (shifted by one bit, see Section 6.4),
or if the I2 C-bus ‘General Call’ address (00H) has been
received (‘General Call’ is indicated when AD0 status bit is
also set to logic 1, see Section 6.8.2.4).
6.8.2.6 LAB
‘Lost Arbitration’ Bit. This bit is set when, in multi-master
operation, arbitration is lost to another master on the
I2C-bus.
Philips Semiconductors Product specification2 C-bus controller PCF8584
6.8.2.7 BB
‘Bus Busy’ bit. This is a read-only flag indicating when the2 C-bus is in use. A zero indicates that the bus is busy, and
access is not possible. This bit is set/reset (logic 1/logic0)
by STOP/START conditions.
6.9 Multi-master operation
To avoid conflict between data and repeated START and
STOP operations, multi-master systems have some
limitations: When powering up multiple PCF8584s in multi-master
systems, the possibility exists that one node may power
up slightly after another node has already begun an2 C-bus transmission; the Bus Busy condition will thus
not have been detected. To avoid this condition, a delay
should be introduced in the initialization sequence of
each PCF8584 equal to the longest I2 C-bus
transmission, see flowchart ‘PCF8584 initialization’
(Fig.5).
6.10 Reset
A LOW level pulse on the RESET (CLK must run) input
forces the I2 C-bus controller into a well-defined state.
All flags in S1 are reset to logic 0, except the PIN flag and
the BB flag, which are set to logic 1. S0' and S3 are set 00H.
The RESET pin is also used for the STROBE output
signal. Both functions are separated on-chip by a digital
filter. The reset input signal has to be sufficiently long
(minimum 30 clock cycles) to pass through the filter.
The STROBE output signal is sufficiently short (8 clock
cycles) to be blocked by the filter. For more detailed
information on the strobe function see Section 6.12.
6.11 Comparison to the MAB8400 I2C-bus interface
The structure of the PCF8584 is similar to that of the
MAB8400 series of microcontrollers, but with a modified
control structure. Access to all I2 C-bus control and status
registers is done via the parallel-bus port in conjunction
with register select input A0, and control bits ESO, ES1
and ES2.
6.11.1 DELETED FUNCTIONS
The following functions are not available in the PCF8584: Always selected (ALS flag) Access to the bit counter (BC0to BC2) Full SCL frequency selection (2 bits instead of 5 bits) The non-acknowledge mode (ACK flag) Asymmetrical clock (ASC flag).
6.11.2 ADDED FUNCTIONS
The following functions either replace the deleted
functions or are completely new: Chip clock prescaler Assert acknowledge bit (ACK flag) Register selection bits (ES1 and ES2 flags) Additional status flags (BER, ‘bus error’) Automatic interface control between 80XX and
68000-type microcontrollers Programmable interrupt vector Strobe generator Bus monitor function Long-distance mode [non-I2 C-bus mode (4-wire); only
for communication between parallel-bus processors
using the PCF8584 at each interface point].
6.12 Special function modes
6.12.1 STROBE
When the I2 C-bus controller receives its own address (or
the ‘00H’ general call address) followed immediately by a
STOP condition (i.e. no further data transmitted after the
address), a strobe output signal is generated at the
RESET/STROBE pin (pin 19). The STROBE signal
consists of a monostable output pulse (active LOW), clock cycles long (see Fig.9). It is generated after the
STOP condition is received, preceded by the correct slave
address. This output can be used as a bus access
controller for multi-master parallel-bus systems.
Philips Semiconductors Product specification2 C-bus controller PCF8584
6.12.2 LONG-DISTANCE MODE
The long-distance mode provides the possibility of
longer-distance serial communication between parallel
processors via two I2 C-bus controllers. This mode is
selected by setting ES1 to logic 1 while the serial interface
is enabled (ESO=1).
In this mode the I2 C-bus protocol is transmitted over unidirectional lines, SDA OUT, SCL IN, SDA IN and
SCL IN (pins2,3,4 and 5). These communication lines
should be connected to line drivers/receivers
(example: RS422) for long-distance applications.
Hardware characteristics for long-distance transmission
are then given by the chosen standard. Control of data
transmission is the same as in normal I2C-bus mode. After
reading or writing data to shift register S0, long-distance
mode must be initialized by setting ESO and ES1 to
logic 1. Because the interrupt output INT is not available in
this operating mode, synchronization of data
transmission/reception must be polled via the PIN bit.
Remarks:
Before entering the long-distance mode, ENI must be
set to logic0.
When powering up an PCF8584-node in long-distance
mode, the PCF8584 must be isolated from the 4-wire
bus via 3-state line drivers/receivers until the PCF8584
is properly initialized for long-distance mode. Failure to
implement this precaution will result in system
malfunction.
6.12.3 MONITOR MODE
When the 7-bit own address register S0' is loaded with all
zeros, the I2 C-bus controller acts as a passive I2 C monitor.
The main features of the monitor mode are: The controller is always selected. The controller is always in the slave receiver mode. The controller never generates an acknowledge. The controller never generates an interrupt request. A pending interrupt condition does not force SCL LOW. BB is set to logic 0 after detection of a START condition,
and reset to logic 1 after a STOP condition. Received data is automatically transferred to the read
buffer. Bus traffic is monitored by the PIN bit, which is reset to
logic 0 after the acknowledge bit of an incoming byte has
been received, and is set to logic 1 as soon as the first
bit of the next incoming byte is detected. Reading the
data buffer S0 sets the PIN bit to logic 1. Data in the read
buffer is valid from PIN= 0 and during the next 8 clock
pulses (until next acknowledge). AAS is set to logic 1 at every START condition, and
reset at every 9th clock pulse. SOFTWARE FLOWCHART EXAMPLES
7.1 Initialization
The flowchart of Fig.5 gives an example of a proper
initialization sequence of the PCF8584.
7.2 Implementation
The flowcharts (Figs6to 9) illustrate proper programming
sequences for implementing master transmitter, master
receive, and master transmitter, repeated start and master
receiver modes in polled applications.
Philips Semiconductors Product specification2 C-bus controller PCF8584
Philips Semiconductors Product specification2 C-bus controller PCF8584
Philips Semiconductors Product specification2 C-bus controller PCF8584
Philips Semiconductors Product specification2 C-bus controller PCF8584
Philips Semiconductors Product specification2 C-bus controller PCF8584
Philips Semiconductors Product specification2 C-bus controller PCF8584
8I2C-BUS TIMING DIAGRAMS
The diagrams (Figs10to 13) illustrate typical timing diagrams for the PCF8584 in master/slave functions. For detailed
description of the I2 C-bus protocol, please refer to “The I2 C-bus and how to use it”; Philips document
ordering number 9398 393 40011.
