PEB22320N V2.1-PEB22320NV2.1-PEB22320NV2.1 .. Fast Delivery |IC PHOENIX CO.,LIMITED

PEB22320NV2.1 .. ,PRACT (Primary Rate Access Clock Gene...characteristics apply at T =25°C and the given supply voltage.AOperating RangeIn the operating rang ..
PEB2245NV1.2 ,MUSAC (Multipoint Switching and Confe...Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PEB22522FV2.1 ,MULTI BIT RATE INTEGRATED CIRCUIT MDSL (Medium bit rate Digital Using the ..
PEB22522FV2.1 ,MULTI BIT RATE INTEGRATED CIRCUITFeatures

PEB22320N V2.1-PEB22320NV2.1-PEB22320NV2.1 ..
PRACT (Primary Rate Access Clock Gene...
Data Sheet04.95
Data Classification
Maximum Ratings
Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible
damage to the integrated circuit.
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit. Typical
characteristics specify mean values expected over the production spread. If not otherwise specified,
typical characteristics apply at TA=25°C and the given supply voltage.
Operating Range
In the operating range the functions given in the circuit description are fulfilled.
For detailed technical information about “Processing Guidelines” and “Quality Assurance” for
ICs, see our Product Overview “ICs for Communications”
PEB 22320
General Information
Table of ContentsPageFeatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.2Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.3System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.1Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.1.1Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.1.2Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1.3Input Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1.4Jitter Attenuator and Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.2Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.2.1Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.2.2Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.3Local Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.4Remote Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.5Bypass Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.6Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.7Receiver Loss of Signal Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.8Master/Slave Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.1Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.1.1Reset with CS Pin Fixed to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.1.2Reset Using CS Pin to Latch Programming (a controller is used) . . . . . . . . .26
3.2Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.2Delay Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.2.1Delay from XDIP/XDIN to XL1/XL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.2.2Delay from RL1/RL2 to RDOP/RDON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.3DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.4Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.5Recommended Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.6AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.6.1Dual Rail Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.6.2System Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4.6.3Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
PEB 22320
4.7Pulse Templates - Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.8Overvoltage Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Primary Rate Access Clock Generator
and Transceiver
PRACT
PEB 22320FeaturesISDN line interface for 1544 and 2048 kbit/s (T1 and
CEPT)Data and clock recoveryTransparent to ternary codesLow transmitter output impedance for a high return
loss with reasonable protection resistors (CCITT
G.703 requirements for the line input return loss
fulfilled)Adaptively controlled receiver thresholdProgrammable pulse shape for T1 applicationsJitter specifications of CCITT I.431 and BELLCORE
TR-NWT-000499 publications metWander and jitter attenuationJitter tolerance of receiver: 0.5 UI sImplements local and remote loops for diagnostic purposesMonolithic line driver for a minimum of external componentsLow power, reliable CMOS technologyLoss of signal indication for receiverClock generator for system clocks

The Primary Rate Access Clock Generator and Transceiver PRACT (PEB 22320) is a
monolithic CMOS device which implements the analog receive and transmit line
interface functions to primary rate PCM carriers. It may be programmed or hard wired to
operate in 1.544-Mbit/s (T1) or 2.048-Mbit/s (CEPT) carrier systems.
The PRACT recovers clock and data using an adaptively controlled receiver threshold.
It will meet the requirement of CCITT I.431 and Bellcore TR-NWT-000499 Issue 5,
December 1993 (Transport System Generic Requirements) in case of pulse shape, jitter
tolerance and jitter transfer characteristic.
PEB 22320
Features
Specially designed line interface circuits simplify the tedious task of protecting the device
against overvoltage damage while still meeting the return loss requirements.
The PRACT is suitable for use in a wide range of voice and data applications such as for
connections of digital switches and PBX’s to host computers, for implementations of
primary ISDN subscriber loops as well as for terminal applications. The maximum range
is determined by the maximum allowable attenuation.
In the T1 case the PRACT’s power consumption is mainly determined by the line length
and type of the cable.

PEB 22320
Features
1.2Pin Definitions and Functions

Pin Definitions and Functions
PEB 22320
Features
Pin Definitions and Functions (cont’d)
PEB 22320
Features
1.3System Integration
Figure1 shows the architecture of a primary access board for data transmission. It
exhibits the following functions:Line Interface (PEB 22320, PRACT)Clock and Data Recovery (PEB 22320, PRACT)Jitter Attenuation (PEB 22320, PRACT)Clock Generation (PEB 22320, PRACT)Coding/Decoding (PEB 2035, ACFA)Framing (PEB 2035, ACFA)Elastic Buffer (PEB 2035, ACFA)Multichannel Protocol Controller (PEB 20320, MUNICH32)System Adaptation (PEB 20320, MUNICH32)μP Interface (all devices)

Figure 1
PEB 22320
Functional DescriptionFunctional Description
Figure 2
PEB 22320
Functional Description
2.1Receiver
2.1.1Basic Functionality
The receiver recovers data from the ternary coded signal at the ternary interface and
outputs it as 2 unipolar signals at the dual rail interface. One of the lines carries the
positive pulses, the other the negative pulses of the ternary signal.
The signal at the ternary interface is received at both ends of a center-tapped
transformer as shown in figure3.
Figure 3
Receiver Configuration
The transformer is center-tapped at the PRACT side. The recommended transmission
factors for the different line characteristic impedances are listed in table1.
Table 1
Recommended Receiver Configuration Values
Wired in this way the receiver has a return loss
ar > 12 dBfor0.025 fb≤ f ≤0.05 fb,
ar > 18 dBfor0.05 fb≤ f ≤1.0 fb and
ar > 14 dBfor1.0 fb≤ f ≤1.5 fb,
PEB 22320
Functional Description
The receiver is transparent to the logical 1’s polarity and outputs positive logical 1’s on
RDOP and negative logical 1’s on RDON. RDON and RDOP are active low and fully
bauded. The comparator threshold to detect logical 1’s and logical 0’s is automatically
adjusted to be 45% of the peak signal level.
Provided the noise is below 10 μV/√Hz the bit error rate will be less than 10–7.
2.1.2Clock and Data Recovery
An analog PLL extracts the internal recovered route clock RRCLK from the data stream
received at the RL1 and RL2 lines. The PLL uses as a reference the system clock
CLK16M for CEPT and CLK12M for T1 applications. The clock and data recovery is
tolerant to long strings of consecutive zeros, because the data sampler will continuously
sample data based on its last input. A block diagram of the clock and data recovery
circuit is shown in figure 4.

Figure 4
PEB 22320
Functional Description
2.1.3Input Jitter Tolerance
The PRACT receiver’s tolerance to input jitter complies to CCITT and Bellcore
requirements for CEPT and T1 application.
Figure 5 shows the curves of the different input jitter specifications stated above as well
as the PRACT performance for the various line codes used at the S1/S2 interfaces.
In figure 5 the curves show that the PRACT at low frequencies has more than 20dB/
decade fall off, and at high frequencies is in a steady state of 0.5 UI (horizontal).
Figure 5
Comparison of Input Jitter Specification and PRACT Performance

PEB 22320
Functional Description
2.1.4Jitter Attenuator and Clock Generator
The jitter attenuator reduces wander and jitter in the recovered clock which are produced
by the line-, clock- and data-recovery characteristics. The attenuator consists of one PLL
with a tunable crystal oscillator and a 288-bit FIFO. To provide for T1 mode a 1.544-MHz
clock (XCLK) and a 2.048-MHz clock (CLK2M) for the system, a second PLL is placed
in series with the first one (refer to figure 6).
If the JATT pin is set to low the FIFO is bypassed and the propagation delay from RL1,2
to RDOP/RDON is reduced by the pass time of the FIFO.
After loss of signal detection, the internal PLL is synchronized to the 2.048 MHz (CEPT)
provided at the SYNC pin (1.544 MHz in the case of T1). If this SYNC pin is not
connected or connected to logical zero, the PRACT switches automatically to master
operating mode (refer to table 3).
With the MODE pin a master selection is provided. That means if the MODE pin is set to
high the master function is selected in which the VCO’s of the jitter attenuator are
centered (±50ppm of the crystal frequencies). If a clock is detected at the SYNC pin the
Table 2
Jitter Input Tolerance
PEB 22320
Functional Description
The jitter attenuator meets the jitter transfer requirements of the Bellcore
TR-NWT 000 499 and Rec. I.431 (refer to figure 7 and table 4).
The amount of generated output jitter when no input jitter is shown in table 5.
Figure 6
PEB 22320
Functional Description
Table 3
Clock and Synchronization Table
=
Ji
ter at
uat
or
enabl
12
M =
352 MH
K =
rnal
recovered
rout
= 0
Sl
ave
sel
= 0:
pass
jitt
er at
enuat
or
16 M
= 16.
384
= 0:
Input
ied t
E =
: M
er
mode sel
4 M
= 4.
= 2 M
Input
conn
ect
ed t
2 M
k

=
0 kH
S =
0:
nput
abo
ve recei
M =
8 MH
=
5 M:
Input
connect
ed
1.
5 M
= d
S =
1:
nput
bel
recei
sho
M
= 1.
544
= N
onnect
PEB 22320
Functional Description

Figure 7
Jitter Attenuation Characteristics

Table 4
Jitter Transfer Characteristics
PEB 22320
Functional Description
Table 5
Generated Output Jitter
Table 4
Jitter Transfer Characteristics (cont’d)
PEB 22320
Functional Description
2.2Transmitter
2.2.1Basic Functionality
The transmitter transforms unipolar data to ternary (alternate bipolar) return to zero
signals of the appropriate shape. The unipolar data is provided at XDIP (positive pulses)
and XDIN (negative pulses), synchronously with the transmit clock XCLK. XDIP and
XDIN are active low and full bauded. Data is sampled on the falling edge of the input
clock (XCLK). The input clock (XCLK) must be derived from the (system) clocks
generated by the PRACT. This ensures the recommended fixed relationship between
XLCK and internal generated clock (4 times XCLK) for the pulse shaper.
The transmitter includes a programmable pulse shaper to satisfy the requirements of the
AT&T Technical Advisory # 34 at the cross connect point for T1 applications. The pulse
shaper is programmed via the line length selection pins LS0, LS1 and LS2.
For T1 application the line length selection supports both low capacitance cable with a
characteristic line capacitance of C’ ≤40 nF/km = 65 nF/mile (e.g. MAT, ICOT) and
higher capacitance cable with a characteristic line capacitance of 40nF/≤C’≤54nF/km (65 nF/mile ≤ C’ ≤87 nF/mile) e.g. ABAM, PIC and PULP cables.
This ensures that for various cable types the signal at the DSX-1 cross connect point
complies with the pulse shape of the AT&T Technical Advisory # 34.
The line length is selected programming the LS0, LS1 and LS2 pins as shown for typical
values in table 6.
Table 6
Line Length Selection
Note:* For ICOT-cable the characteristic impedance is 140 Ω
By selecting an all-zero code for LS0, LS1 and LS2 the PRACT can be adapted for
CEPT applications.
PEB 22320
Functional Description
The pulse shape according to CCIT G.703 (1544-kbit/s interface) is achieved by using
the same line length selection code as for the lowest T1 cable range. To switch the
device into a low power dissipation mode, XDIP and XDIN should be held high.
The transmitter requires an external step up transformer to drive the line. The
transmission factor and the source serial resistor values can be seen in figure 8 and
table 7 for the various applications.
Figure 8
Transmitter Configuration
Table 7
Transmitter Configuration Values
Wired in this way the transmitter has a return lossr > 8 dBfor0.025 fb≤ f ≤0.05 fb,
ar > 14 dBfor0.05 fb≤ f ≤1.0 fb andr > 10 dBfor1.0 fb≤ f ≤1.5 fb,
with fb being 2048 kHz (CEPT applications). A termination resistor of 120 Ω is assumed.
In T1 applications the return loss is higher than 10 dB.
Please note, that the transformer ratio at the receiver is half of that at the transmitter. The
same type of transformer can thus be used at the receiver and at the transmitter. At the
transmitter the two windings are connected in parallel, at the receiver in series. Thus,
unbalances are avoided.
PEB 22320
Functional Description
2.2.2Output Jitter
In the absence of any input jitter the PRACT generates the output jitter, which is specified
in table 5.
Note:The generated output jitter on the line is the same as the output jitter of the system
clocks.
2.3Local Loopback
The local loopback mode disconnects the receive lines RL1 and RL2 from the receiver.
Instead of the signals coming from the line the data provided at XTIP and XTIN are
routed through the receiver. The XDIN and XDIP signals continue to be transmitted on
the line. The local loopback occurs in response to LL going high.
2.4Remote Loopback
In the remote loopback mode the clock and data recovered from the line inputs RL1 and
RL2 are routed back to the line outputs XL1 and XL2 via the transmitter. As in normal
mode they are also output at RDOP and RDON. XDIP and XDIN are disconnected from
the transmitter.
The remote loopback mode is selected by a high RL signal.
2.5Bypass Jitter Attenuator
If the JATT pin is set to low the jitter attenuator (FIFO) is bypassed and the propagation
delay from the line to the dual rail interface is reduced by the path time of the FIFO. Also
in this mode the jitter in the system clocks (CLK2M, CLK4M, FSC) is attenuated.
2.6Microprocessor Interface
The PRACT is fully controlled by six parallel data lines (LS0, LS1, LS2, LL, RL and JATT)
and one control line (CS). To adapt the device to a standard microprocessor interface
the low state of CS is decoded from the microprocessor address, CS, WR and ALE lines.
To hardwire the chip, CS must be fixed to ground.
2.7Receiver Loss of Signal Indication
In the case that the signal at the line receiver input (pins RL1, RL2) becomes smaller
than Vin≤0.3VOP loss of signal is indicated. This voltage value corresponds to a line
attenuation of about 14 dB in the CEPT case. This is performed by turning both signals
RDOP, RDON after at least 32 bits simultaneously to 5V, i.e. a logical 0 on both lines.
The following ACFA processes this indication for the system. In this mode the PRACT
synchronizes to the clock at the SYNC pin.
PEB 22320
Functional Description
2.8Master/Slave Selection
If the MODE pin is set to high and the SYNC pin is not connected or connected to VSS the
PRACT works as a master for the system. The VCO’s of the jitter attenuator are centered
(± 50 ppm of the crystal frequencies) and the system clocks are stable (divided from the
VCO frequencies). If a clock (2.048 MHz for CEPT, 1.544 MHz for T1) is detected at the
SYNC pin the PRACT synchronizes automatically to this clock. In master mode, the
PRACT is independent from the receiver loss of signal detection.
Note:The MODE pin can not be controlled by the μP interface and requires CMOS
levels as input signals. It must always be connected either to VDD or VSS.
A voltage of 2.5 V at the MODE Pin switch the PRACT into test mode.

Partno	Mfg	Dc	Qty	Available	Descript
PEB22320N V2.1 \|PEB22320NV21		N/a	25	avai	PRACT (Primary Rate Access Clock Gene...
PEB22320N V2.1 \|PEB22320NV21	SIEMENS	N/a	25	avai	PRACT (Primary Rate Access Clock Gene...
PEB22320NV2.1 \|PEB22320NV21	SIEMENS	N/a	43	avai	PRACT (Primary Rate Access Clock Gene...
PEB22320NV2.1 \|PEB22320NV21	INFINEON	N/a	459	avai	PRACT (Primary Rate Access Clock Gene...
PEB22320NV2.1 .. \|PEB22320NV21	SIEMENS	N/a	880	avai	PRACT (Primary Rate Access Clock Gene...