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PEF2015TV1.2
MICO (Mini IOM-2 Controller)
ICs for Communications
Mini IOM®-2 Controller
MICO
PEF 2015 Version 1.1
Data Sheet12.97
DS 1
Edition 12.97
This edition was realized using the software system FrameMaker.
Published by Siemens AG,
HL DT CE© Siemens AG 1997.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will
take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incur-
red.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express
written approval of the Semiconductor Group of Siemens AG.A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-
PEF 2015Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.2Pinning Diagram
(top view) 8
1.3Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.4Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.5Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1Configurable Interface CFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.2Serial PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.3Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.4Memory Structure and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.5Pre-processed Channels, Layer-1 Support . . . . . . . . . . . . . . . . . . . . . . . .17
2.6Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.1Microprocessor Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.2Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.3Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.4MICO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.4.1PCM-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.4.2Configurable Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.4.3Switching Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.4.4Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.5Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.5.1Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.5.2MICO Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.5.2.1Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.5.2.2Control Memory Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.5.2.3Initialization of Pre-processed Channels . . . . . . . . . . . . . . . . . . . . .30
3.5.2.4Initialization of the Upstream Data Memory (DM) Tristate Field . . . .31
3.5.3Activation of the PCM- and CFI-Interfaces . . . . . . . . . . . . . . . . . . . . . .32Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
4.1Register Address Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
4.2Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.2.1PCM-Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.2.1.1PCM-Mode Register (PMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.2.1.2Bit Number per PCM-Frame (PBNR) . . . . . . . . . . . . . . . . . . . . . . . .36
4.2.1.3PCM-Offset Downstream Register (POFD) . . . . . . . . . . . . . . . . . . .36
4.2.1.4PCM-Offset Upstream Register (POFU) . . . . . . . . . . . . . . . . . . . . .37
4.2.1.5PCM-Clock Shift Register (PCSR) . . . . . . . . . . . . . . . . . . . . . . . . . .38
PEF 2015
4.2.2Configurable Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.2.2.1Configurable Interface Mode Register 1 (CMD1) . . . . . . . . . . . . . . .39
4.2.2.2Configurable Interface Mode Register 2 (CMD2) . . . . . . . . . . . . . . .41
4.2.2.3Configurable Interface Bit Number Register (CBNR) . . . . . . . . . . . .44
4.2.2.4Configurable Interface Time Slot Adjustment Register (CTAR) . . . .44
4.2.2.5Configurable Interface Bit Shift Register (CBSR) . . . . . . . . . . . . . . .45
4.2.2.6Configurable Interface Subchannel Register (CSCR) . . . . . . . . . . .47
4.2.3Memory Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.2.3.1Memory Access Control Register (MACR) . . . . . . . . . . . . . . . . . . . .48
4.2.3.2Memory Access Address Register (MAAR) . . . . . . . . . . . . . . . . . . .52
4.2.3.3Memory Access Data Register (MADR) . . . . . . . . . . . . . . . . . . . . . .53
4.2.4Synchronous Transfer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.2.4.1Synchronous Transfer Data Register (STDA) . . . . . . . . . . . . . . . . .54
4.2.4.2Synchronous Transfer Data Register B (STDB) . . . . . . . . . . . . . . . .54
4.2.4.3Synchronous Transfer Receive Address Register A (SARA) . . . . . .55
4.2.4.4Synchronous Transfer Receive Address Register B (SARB) . . . . . .56
4.2.4.5Synchronous Transfer Transmit Address Register A (SAXA) . . . . .56
4.2.4.6Synchronous Transfer Transmit Address Register B (SAXB) . . . . .57
4.2.4.7Synchronous Transfer Control Register (STCR) . . . . . . . . . . . . . . .57
4.2.5Monitor/Feature Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
4.2.5.1MF-Channel Active Indication Register (MFAIR) . . . . . . . . . . . . . . .58
4.2.5.2MF-Channel Subscriber Address Register (MFSAR) . . . . . . . . . . . .59
4.2.5.3Monitor/Feature Control Channel FIFO (MFFIFO) . . . . . . . . . . . . . .60
4.2.6Status/Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
4.2.6.1Signaling FIFO (CIFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
4.2.6.2Timer Register (TIMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.2.6.3Status Register (STAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
4.2.6.4Command Register (CMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4.2.6.5Interrupt Status Register (ISTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
4.2.6.6Mask Register MICO (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
4.2.6.7Operation Mode Register (OMDR) . . . . . . . . . . . . . . . . . . . . . . . . . .67
4.2.6.8Version Number Status Register (VNSR) . . . . . . . . . . . . . . . . . . . .69
4.3Register Changes compared to the EPIC . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.1PMOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.2PCSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.3PICM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.4CMD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.5CSCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.6ISTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.7MASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.8VSNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
PEF 2015
5.1Access Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Partno	Mfg	Dc	Qty	Available	Descript
PEF2015TV1.2 \|PEF2015TV12	Infineon	N/a	1000	avai	MICO (Mini IOM-2 Controller)