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PEF20450HV1.3 |PEF20450HV13INFINEONN/a26avaiMTSI (Memory Time Slot Interchangers)
PEF20470HV1.3 |PEF20470HV13infineonN/a16avaiMTSI-L (Memory Time Slot Interchanger...


PEF20450HV1.3 ,MTSI (Memory Time Slot Interchangers)Preliminary Data Sheet, DS 1, Nov. 2001SWITISwitching ICPEF 20450 MTSIPEF 20470 MTSI-LPEF 244 ..
PEF20470HV1.3 ,MTSI-L (Memory Time Slot Interchanger...Preliminary Data Sheet, DS 1, Nov. 2001SWITISwitching ICPEF 20450 MTSIPEF 20470 MTSI-LPEF 244 ..
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PEF20450HV1.3-PEF20470HV1.3
MTSI (Memory Time Slot Interchangers)
SWITI
Switching IC
PEF 20450 MTSI
PEF 20470 MTSI-L
PEF 24470 MTSI-XL
Version 1.3

SWITI
Switching IC
PEF 20450 MTSI
PEF 20470 MTSI-L
PEF 24470 MTSI-XL
Version 1.3
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
PEF 20450 / 20470 / 24470
PRELIMINARY
Revision History:2001-11-20DS 1

Previous Version:
PEF 20450 / 20470 / 24470 V1.2, Preliminary Data Sheet DS1, 2001-04-04
1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1Overview of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2Features in Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4Standard PBX or CO Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1Pin Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1Local Bus Interface (PCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2General Purpose Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.3Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.4JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.5Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.6Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Architectural Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2Overview of Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3Switching Factory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.1Switching Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.1.1Minimum and Constant Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.1.2Subchannel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.1.3Multipoint Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.1.4Broadcast Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.1.5Bidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.1.6Message Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.2Parallel Mode for Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.3Switching Block Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.4Analyze Connection and Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4Clock Generator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.1General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.2Analog PLL (APLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4.2.1Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4.2.2Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.3Phase Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.4PLL Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.6Read SWITI Configuration with Indirect Register Addressing . . . . . . . . . . 27
3.7Power-On and Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7.1Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7.2Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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