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PEF22554HT
Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
DS1, 2003-07-02Revision History: Previous Version:
Major Changes:
QuadFALC®
Quad E1/T1/J1 Framer and Line Interface Component
for Long- and Short-Haul Applications
PEF 22554HT/E, Version 2.1
AbstractThis document is an Addendum to the PEF 22554HT/E, QuadFALC®, Version 2.1 Data
Sheet DS1, release date 2002-09. It describes data that has to be changed or added.
ReferencedStandards
Page 5, Related DocumentationIn addition to the standards listed in the Data Sheet, the device complies also with:ITU-T G.705ITU-TG.733ITU-JTG.733
Revision History: Previous Version: -/-
Major Changes: -/-
LogicSymbolforBGAPackagePage 23, Chapter 1.2, Logic SymbolDue to the slight difference (number of power supply and ground connections) between
the TQFP package and the BGA package, a separate drawing is provided for the BGA.
Figure 1ALogic Symbol (BGA Package)
JTAG Ball NamesPage 52, Chapter 2.2, Pin Definitions and FunctionsThe BGA ball numbers are missing for the JTAG pins. They are as shown below.
Table 5Pin Definitions - Miscellaneous
Boundary Scan/Joint Test Access Group (JTAG)
BoundaryScan4.1JTAG Instructions
Page 63, Chapter 3.4.2, Boundary Scan InterfaceThe TAP controller instruction codes 01010101B and 01010100B have been added. Both
are reserved for device tests and shall not be used.
4.2JTAG ID
Page 427, Chapter 11.4.2, JTAG Boundary Scan InterfaceThe correct Boundary Scan IDCODE field is:
0001 0000 0000 1000 1110 0000 1000 0011 (Version=1H, Part Number=008EH)
RCLKClockMultiplexing
Page 65/124, Chapter 4.1/5.1, Receive Path in E1 or T1/J1 ModeSome details have been added to the figure showing the clock multiplexing options for
RCLK.
Figure17/46Receive Clock Selection (E1/T1/J1)
Bipolar Violation DetectionPage 68, Chapter 4.1.6, Receive Line Coding in E1 ModeThe HDB3 line code or the AMI coding is provided for the data received from the ternary
or the dual rail interface. All code violations that do not correspond to zero substitution
rules are detected, resulting in an increment of the 16-bit code violation counter. If a bit
error causes a code violation that leads to a valid substitution pattern, this code violation
is neither detected nor counted and the substitution pattern is replaced by the
corresponding zero pattern.
In case of the optical interface a selection between the NRZ code and the CMI Code
(1T2B) with HDB3 or AMI postprocessing is provided. If CMI code is selected the receive
route clock is recovered from the data stream. The CMI decoder does not correct any
errors. In case of NRZ coding data is latched with the falling edge of signal RCLKI. The
HDB3 code is used along with double violation detection or extended code violation
detection (selectable by FMR0.EXZE). In AMI code all code violations are detected. The
detected errors increment the code violation counter (16 bits length).
Page 127, Chapter 5.1.6, Receive Line Coding in T1/J1 ModeThe B8ZS line code or the AMI (ZCS, zero code suppression) coding is provided for the
data received from the ternary or the dual rail interface. All code violations that do not
correspond to zero substitution rules are detected, resulting in an increment of the 16-bit
code violation counter. If a bit error causes a code violation that leads to a valid
substitution pattern, this code violation is neither detected nor counted and the
substitution pattern is replaced by the corresponding zero pattern. The detected errors
increment the code violation counter (16 bits length).
SignalingMarkerDiagramsPage 180/181, Chapter 5.5.2, Transmit System InterfaceThe following diagrams have been modified for clarity.
Figure711.544 MHz Transmit Signaling Highway (T1/J1)
Figure72Signaling Marker for CAS/CAS-CC Applications (T1/J1)
Clock Mode SelectionPage 194/200, Chapter 6.3 and Chapter 7.3, Device Initialization E1 and T1/J1The following text has been added:
The clock mode must be programmed according to the selected MCLK frequency before
any XL1/2 output is enabled (while the outputs are not yet activated by selection of the
line coding). Otherwise the output pulse width might not match the pulse mask
requirements.
Page 277, Chapter 9.2 and Page 384, Chapter 10.2, Clock Mode Register
programming for E1 and T1/J1The following text has been added/corrected (for E1 and T1/J1 operation):
Attention:Write operations to GCM5 and/or GCM6 register initiate a PLL reset (see
below) and must be performed before any port configuration is done. If
this is not possible set LIM01.DRS (if not set) of every channel
separately before writing to these registers and reset LIM01.DRS (if it
was not set before) after these write operations.Device Initialization
Page 192, Table 46, Initial Values after Reset (E1)The second row shall read:
2.048 8.192 MHz system clocking rate...
Page 194, Table 47, Initialization Parameters (E1)The row “Framing additions” shall read:
RC0RC1.ASY4, RC0RC1.SWD
HDLC Handling
Page 221/321, Chapter 9.2/10.2, Register bit CMDR.RMCConfirmation from CPU to QuadFALC that the current frame or data block has been
fetched following an RPF or RME interrupt, thus the occupied space in the RFIFO can
be released. While the FIFO is empty, RMC must not be set. If RMC is given while RFIFO
is already cleared, the next incoming data block is cleared instantly, although interrupts
are generated. This might lead to incorrect software behaviour.
