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PHB18NQ10T-PHB18NQ20T-PHD18NQ10T-PHP18NQ10T
N-channel TrenchMOS(tm) transistor
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHP18NQ10T, PHB18NQ10T
PHD18NQ10T
FEATURES SYMBOL QUICK REFERENCE DATA• ’Trench’ technology
• Low on-state resistance VDSS = 100 V
• Fast switching
• Low thermal resistance ID = 18 A
RDS(ON) ≤ 90 mΩ
GENERAL DESCRIPTIONN-channel enhancement mode field-effect power transistorina plastic envelope using ’trench’ technology.
Applications:- d.c.to d.c. converters switched mode power supplies
The PHP18NQ10Tis suppliedin the SOT78 (TO220AB) conventional leaded package.
The PHB18NQ10Tis suppliedin the SOT404(D2 PAK) surface mounting package.
The PHD18NQ10Tis suppliedin the SOT428 (DPAK) surface mounting package.
PINNING SOT78 (TO220AB) SOT404 (D2 PAK) SOT428 (DPAK)
PIN DESCRIPTION gate drain 1 source
tab drain
LIMITING VALUESLimiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNITVDSS Drain-source voltage Tj = 25 ˚C to 175˚C - 100 V
VDGR Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ - 100 V
VGS Gate-source voltage - ± 20 V Continuous drain current Tmb = 25 ˚C; VGS = 10 V - 18 A
Tmb = 100 ˚C; VGS = 10 V - 13 A
IDM Pulsed drain current Tmb = 25 ˚C - 72 A Total power dissipation Tmb = 25 ˚C - 79 W
Tj, Tstg Operating junction and - 55 175 ˚C
storage temperature3
tab
tab
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHP18NQ10T, PHB18NQ10T
PHD18NQ10T
AVALANCHE ENERGY LIMITING VALUESLimiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNITEAS Non-repetitive avalanche Unclamped inductive load, IAS = 11 A; - 70 mJ
energy tp = 100 μs; Tj prior to avalanche = 25˚C;
VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; refer
to fig:15
IAS Peak non-repetitive - 18 A
avalanche current
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT th j-mb Thermal resistance junction - - 1.9 K/W
to mounting base
Rth j-a Thermal resistance junction SOT78 package, in free air - 60 - K/W
to ambient SOT404 & SOT428 packages, pcb - 50 - K/W
mounted, minimum footprint
ELECTRICAL CHARACTERISTICSTj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITV(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 100 - - V
voltage Tj = -55˚C 89 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 2 3 4 V
Tj = 175˚C 1 - - V
Tj = -55˚C - 6 V
RDS(ON) Drain-source on-state VGS = 10 V; ID = 9 A - 80 90 mΩ
resistance Tj = 175˚C - - 243 mΩ
IGSS Gate source leakage current VGS = ± 10 V; VDS = 0 V - 10 100 nA
IDSS Zero gate voltage drain VDS = 100 V; VGS = 0 V - 0.05 10 μA
current Tj = 175˚C - - 500 μA
Qg(tot) Total gate charge ID = 18 A; VDD = 80 V; VGS = 10 V - 21 - nC
Qgs Gate-source charge - 4 - nC
Qgd Gate-drain (Miller) charge - 8 - nC
td on Turn-on delay time VDD = 50 V; RD = 2.7 Ω;- 6 - ns Turn-on rise time VGS = 10 V; RG = 5.6 Ω -36 - nsd off Turn-off delay time Resistive load - 18 - ns Turn-off fall time - 12 - ns Internal drain inductance Measured tab to centre of die - 3.5 - nH Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH
(SOT78 package only) Internal source inductance Measured from source lead to source - 7.5 - nH
bond pad
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 633 - pF
Coss Output capacitance - 103 - pF
Crss Feedback capacitance - 61 - pF
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHP18NQ10T, PHB18NQ10T
PHD18NQ10T
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICSTj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Continuous source current - - 18 A
(body diode)
ISM Pulsed source current (body - - 72 A
diode)
VSD Diode forward voltage IF = 18 A; VGS = 0 V - 0.92 1.2 V
trr Reverse recovery time IF = 18 A; -dIF/dt = 100 A/μs; - 55 - ns
Qrr Reverse recovery charge VGS = 0 V; VR = 25 V - 135 - nC
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHP18NQ10T, PHB18NQ10T
PHD18NQ10T
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS)
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
Normalised Power Derating, PD (%)
100 25 50 75 100 125 150 175
Mounting Base temperature, Tmb (C)
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00
Pulse width, tp (s)
Transient thermal impedance, Zth j-mb (K/W)
Normalised Current Derating, ID (%)
100 25 50 75 100 125 150 175
Mounting Base temperature, Tmb (C) 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
Peak Pulsed Drain Current, IDM (A)
0.2 2 4 6 8 1012 1416 1820Drain Current, ID (A)
Drain-Source On Resistance, RDS(on) (Ohms)
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHP18NQ10T, PHB18NQ10T
PHD18NQ10T
Fig.7. Typical transfer characteristics.
ID = f(VGS)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
Fig.9. Normalised drain-source on-state resistance.
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.12. Typical capacitances, Ciss, Coss, Crss.
012345 6789 10
Gate-source voltage, VGS (V)
Drain current, ID (A)
Threshold Voltage, VGS(TO) (V)
-60 -40 -200 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
02468 10 12 14 16 18 20
Drain current, ID (A)
Transconductance, gfs (S)
Drain current, ID (A)
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Gate-source voltage, VGS (V)
Normalised On-state Resistance
-60 -40 -200 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
0.1 1 10 100
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHP18NQ10T, PHB18NQ10T
PHD18NQ10T
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tAV);
unclamped inductive load
49142468 1012 1416 1820 2224 262830
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
0.001 0.01 0.1 1 10
Avalanche time, tAV (ms)
Maximum Avalanche Current, IAS (A) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.91 1.1 1.2
Source-Drain Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
