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PHB21N06LT-PHD21N06LT-PHP21N06LT
N-channel TrenchMOS(tm) transistor Logic level FET
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT
Logic level FET PHD21N06LT
FEATURES SYMBOL QUICK REFERENCE DATA• ’Trench’ technology VDSS = 55 V
• Low on-state resistance
• Fast switching ID = 19 A
• Logic level compatible RDS(ON) ≤ 75 mΩ (VGS = 5 V)
RDS(ON) ≤ 70 mΩ (VGS = 10 V)
GENERAL DESCRIPTIONN-channel enhancement mode, logic level, field-effect power transistorina plastic envelope using ’trench’ technology.
Applications:- d.c.to d.c. converters switched mode power supplies
The PHP21N06LTis suppliedin the SOT78 (TO220AB) conventional leaded package.
The PHB21N06LTis suppliedin the SOT404(D2 PAK) surface mounting package.
The PHD21N06LTis suppliedin the SOT428 (DPAK) surface mounting package.
PINNING SOT78 (TO220AB) SOT404 (D2 PAK) SOT428 (DPAK)
PIN DESCRIPTION gate drain 1 source
tab drain
LIMITING VALUESLimiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNITVDSS Drain-source voltage Tj = 25 ˚C to 175˚C - 55 V
VDGR Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ -55 V
VGS Gate-source voltage - ± 15 V
VGSM Pulsed gate-source voltage Tj ≤ 150˚C - ± 20 V Continuous drain current Tmb = 25 ˚C - 19 A
Tmb = 100 ˚C - 13 A
IDM Pulsed drain current Tmb = 25 ˚C - 76 A Total power dissipation Tmb = 25 ˚C - 56 W
Tj, Tstg Operating junction and - 55 175 ˚C
storage temperature3
tab
tab
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT
Logic level FET PHD21N06LT
AVALANCHE ENERGY LIMITING VALUESLimiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNITEAS Non-repetitive avalanche Unclamped inductive load, IAS = 9.7 A; - 34 mJ
energy tp = 100 μs; Tj prior to avalanche = 25˚C;
VDD ≤ 25 V; RGS = 50 Ω; VGS = 5 V; refer to
fig:15
IAS Peak non-repetitive - 19 A
avalanche current
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT th j-mb Thermal resistance junction - 2.7 K/W
to mounting base
Rth j-a Thermal resistance junction SOT78 package, in free air 60 - K/W
to ambient SOT428 and SOT404 package, pcb 50 - K/W
mounted, minimum footprint
ELECTRICAL CHARACTERISTICSTj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITV(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 1.0 1.5 2.0 V
Tj = 175˚C 0.5 - - V
Tj = -55˚C - - 2.3 V
RDS(ON) Drain-source on-state VGS = 10 V; ID = 10 A - 55 70 mΩ
resistance VGS = 5 V; ID = 10 A - 60 75 mΩ
Tj = 175˚C - - 158 mΩ
gfs Forward transconductance VDS = 25 V; ID = 10 A 5 13 - S
IGSS Gate source leakage current VGS = ±5 V; VDS = 0 V - 10 100 nA
IDSS Zero gate voltage drain VDS = 55 V; VGS = 0 V; - 0.05 10 μA
current Tj = 175˚C - - 500 μA
Qg(tot) Total gate charge ID = 20 A; VDD = 44 V; VGS = 5 V - 9.4 - nC
Qgs Gate-source charge - 2.2 - nC
Qgd Gate-drain (Miller) charge - 5.4 - nCd on Turn-on delay time VDD = 30 V; RD = 1.2 Ω;- 7 15 ns Turn-on rise time RG = 10 Ω; VGS = 5 V - 88 120 ns
td off Turn-off delay time Resistive load - 25 40 ns Turn-off fall time - 25 45 ns Internal drain inductance Measured from tab to centre of die - 3.5 - nH Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH
(SOT78 package only) Internal source inductance Measured from source lead to source - 7.5 - nH
bond pad
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 466 650 pF
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT
Logic level FET PHD21N06LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICSTj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Continuous source current - - 19 A
(body diode)
ISM Pulsed source current (body - - 76 A
diode)
VSD Diode forward voltage IF = 20 A; VGS = 0 V - 1.2 1.5 V
trr Reverse recovery time IF = 20 A; -dIF/dt = 100 A/μs; - 43 - ns
Qrr Reverse recovery charge VGS = 0 V; VR = 30 V - 94 - nC
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Power Derating, PD (%)
100 25 50 75 100 125 150 175
Mounting Base temperature, Tmb (C)
Normalised Current Derating, ID (%)
100 25 50 75 100 125 150 175
Mounting Base temperature, Tmb (C)
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00
Pulse width, tp (s)
Transient thermal impedance, Zth j-mb (K/W)
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT
Logic level FET PHD21N06LT
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS)
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID)
Fig.7. Typical transfer characteristics.
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
Fig.9. Normalised drain-source on-state resistance.
RDS(ON)/RDS(ON)25 ˚C = f(Tj)
Fig.10. Gate threshold voltage.
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Drain-Source Voltage, VDS (V)
Drain Current, ID (A) 2 4 6 8 10 12 14 16 18 20
Drain current, ID (A)
Transconductance, gfs (S)
0.3 5 10 15 20 25 30 35
Drain Current, ID (A)
Normalised On-state Resistance
-60 -40 -200 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C) 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Gate-source voltage, VGS (V)
Drain current, ID (A)
Threshold Voltage, VGS(TO) (V)
-60 -40 -200 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT
Logic level FET PHD21N06LT
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics.
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tAV);
unclamped inductive load
Drain current, ID (A)
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01 0.5 1 1.5 2 2.5 3
Gate-source voltage, VGS (V) 0.10.20.30.40.50.60.70.80.91 1.11.21.31.41.5
Source-Drain Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
0.1 1 10 100
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
0.001 0.01 0.1 1 10
Avalanche time, tAV (ms)
Maximum Avalanche Current, IAS (A)
02468 10 12 14 16 18 20
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT
Logic level FET PHD21N06LT
MECHANICAL DATAFig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)
Notes1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to mounting instructions for SOT78 (TO220AB) package.
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 SOT78
