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PHKD13N03LT
Dual TrenchMOS⑩ logic level FET
PHKD13N03LTDual T renchMOS™ logic level FET
Rev. 01 — 23 June 2003 Product dataM3D315
Product profile
1.1 DescriptionDual N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PHKD13N03LT in SOT96-1 (SO8).
1.2 Features
1.3 Applications
1.4 Quick reference data Pinning information Low gate charge � Surface mount package Low on-state resistance � Fast switching. Portable appliances � Notebook computers Lithium-ion battery chargers � DC-to-DC converters. VDS≤30V � ID≤ 10.4A Ptot≤ 3.57W � RDSon≤20 mΩ
Table 1: Pinning - SOT96-1 (SO8), simplified outline and symbol source1 (s1)
SOT96-1 (SO8) gate1 (g1) source2 (s2) gate2 (g2)
5,6 drain2 (d2)
7,8 drain1 (d1)
Top view MBK187
MBK725s11 ds22
Philips Semiconductors PHKD13N03LT
Dual TrenchMOS™ logic level FET Limiting values[1] Single device conducting.
Table 2: Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDS drain-source voltage (DC) 25°C≤Tj≤ 150°C - 30 V
VDGR drain-gate voltage (DC) 25°C≤Tj≤ 150 °C; RGS =20kΩ -30 V
VGS gate-source voltage (DC) - ±20 V drain current (DC) Tsp =25 °C; VGS =10V; Figure2 and3 [1]- 10.4 A
Tsp= 100 °C; VGS =10V; Figure2 [1]- 6.6 A
IDM peak drain current Tsp =25 °C; pulsed; tp≤10 μs; Figure3 [1] -42 A
Ptot total power dissipation Tsp =25 °C; Figure1 - 3.57 W
Tstg storage temperature −55 +150 °C junction temperature −55 +150 °C
Source-drain diode source (diode forward) current (DC) Tsp =25°C [1]- 3.2 A
ISM peak source (diode forward) current Tsp =25 °C; pulsed; tp≤10μs [1] -42 A
Philips Semiconductors PHKD13N03LT
Dual TrenchMOS™ logic level FET
Philips Semiconductors PHKD13N03LT
Dual TrenchMOS™ logic level FET Thermal characteristics
4.1 Transient thermal impedance
Table 3: Thermal characteristicsRth(j-sp) thermal resistance from junction to solder
point
Figure4 --35 K/W
Rth(j-a) thermal resistance from junction to ambient minimum footprint;
mountedona printed-circuit board 70 - K/W
Philips Semiconductors PHKD13N03LT
Dual TrenchMOS™ logic level FET Characteristics
Table 4: Characteristics =25 °C unless otherwise specified.
Static characteristicsV(BR)DSS drain-source breakdown voltage ID= 250 μA; VGS =0V =25°C 30 --V= −55°C 27 --V
VGS(th) gate-source threshold voltage ID= 250 μA; VDS =VGS; Figure9 V =25°C 1 1.5 2 V= 150°C 0.5 - - V= −55°C - - 2.2 V
IDSS drain-source leakage current VDS =24V; VGS =0V =25°C --1 μA= 100°C --5 μA
IGSS gate-source leakage current VGS= ±20 V; VDS=0V - - 100 nA
RDSon drain-source on-state resistance VGS=10 V; ID =8A; Figure7 and8 =25°C - 17 20 mΩ= 150°C --34 mΩ
VGS= 4.5 V; ID =7A; Figure7 - 2126mΩ
Dynamic characteristicsQg(tot) total gate charge ID=5 A; VDD =15V; VGS =5V; Figure13 - 10.7- nC
Qgs gate-source charge - 2.7 - nC
Qgd gate-drain (Miller) charge - 3.9 - nC
Ciss input capacitance VGS =0V; VDS=15 V; f=1 MHz; Figure11 - 752 - pF
Coss output capacitance - 200 - pF
Crss reverse transfer capacitance - 130 - pF
td(on) turn-on delay time VDD =15V; ID= 1.5 A; VGS =10V; RG =6Ω -6 -ns rise time -7 -ns
td(off) turn-off delay time - 23 - ns fall time -11 - ns
Source-drain diodeVSD source-drain (diode forward) voltageIS=7 A; VGS =0V; Figure12 - 0.86 1.1 V
trr reverse recovery time IS=7 A; dIS/dt= −100 A/μs; VR =30V;
VGS =0V
-25 - ns recovered charge - 5 - nC
Philips Semiconductors PHKD13N03LT
Dual TrenchMOS™ logic level FET
