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Partno	Mfg	Dc	Qty	Available	Descript
PHKD6N02LT	NXP/PH	N/a	10000	avai	Dual N-channel TrenchMOS logic level FET

PHKD6N02LT ,Dual N-channel TrenchMOS logic level FETGeneral descriptionDual logic level N-channel enhancement mode Field-Effect Transistor (FET) in a p ..
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PHKD6N02LT
Dual N-channel TrenchMOS logic level FET
PHKD6N02LT
Dual N-channel TrenchMOS logic level FET
Rev. 04 — 27 April 2010 Product data sheet Product profile
1.1 General description
Dual logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits Low conduction losses due to low
on-state resistance Suitable for logic level gate drive
sources
1.3 Applications Battery chargers DC-to-DC convertors Notebook computers Portable equipment
1.4 Quick reference data Table 1. Quick reference data
VDS drain-source voltage Tj≥25 °C; Tj≤ 150°C --20 V drain current Tsp=25 °C; Single device
conducting; see Figure 1;
see Figure 3
--10.9 A
Ptot total power
dissipation
Tsp =25°C; see Figure 2 --4.17 W
Static characteristics
RDSon drain-source on-state
resistance
VGS =2.5 V; ID =3A; Tj=25°C - 25 35 mΩ
Dynamic characteristics
QGD gate-drain charge VGS =5V; ID =6A; VDS =16V; =25°C; see Figure 11 -nC
NXP Semiconductors PHKD6N02LT
Dual N-channel TrenchMOS logic level FET Pinning information Ordering information Limiting values
Table 2. Pinning information
1S1 source1
SOT96-1 (SO8) G1 gate1
3S2 source2 G2 gate2
5D2 drain2
6D2 drain2
7D1 drain1
8D1 drain1
Table 3. Ordering information
PHKD6N02LT SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VDS drain-source voltage Tj≥25 °C; Tj≤ 150°C --20 V
VDGR drain-gate voltage Tj≤ 150 °C; Tj≥25 °C; RGS =20kΩ --20 V
VGS gate-source voltage -12 - 12 V drain current Tsp= 100 °C; Single device conducting;
see Figure 1
--6.8 A
Tsp=25 °C; Single device conducting;
see Figure 1; see Figure 3 - 10.9 A
IDM peak drain current Tsp =25 °C; tp≤ 100 µs; pulsed; Single
device conducting; see Figure 3
--44 A
Ptot total power dissipation Tsp =25 °C; see Figure 2 --4.17 W
Tstg storage temperature -55 - 150 °C junction temperature -55 - 150 °C
Source-drain diode source current Tsp=25°C --3.5 A
ISM peak source current Tsp =25 °C; tp≤10 µs; pulsed - - 44 A
NXP Semiconductors PHKD6N02LT
Dual N-channel TrenchMOS logic level FET
NXP Semiconductors PHKD6N02LT
Dual N-channel TrenchMOS logic level FET Thermal characteristics
Table 5. Thermal characteristics
Rth(j-sp) thermal resistance from
junction to solder point
see Figure 4 --30 K/W
Rth(j-a) thermal resistance from
junction to ambient
minimum footprint; mounted on
printed-circuit board
-70 - K/W
NXP Semiconductors PHKD6N02LT
Dual N-channel TrenchMOS logic level FET Characteristics
Table 6. Characteristics
Static characteristics
V(BR)DSS drain-source
breakdown voltage =250 µA; VGS =0V; Tj=25°C 20 --V
VGS(th) gate-source threshold
voltage =250 µA; VDS =10V; Tj =25°C;
see Figure 8
0.5 - 1.5 V
IDSS drain leakage current VDS =20V; VGS =0V; Tj=25°C - 0.05 10 µA
VDS =20V; VGS =0V; Tj= 150°C - - 500 µA
IGSS gate leakage current VGS =12V; VDS =0V; Tj=25°C - - 100 nA
VGS =-12 V; VDS =0V; Tj=25°C - - 100 nA
RDSon drain-source on-state
resistance
VGS =2.5 V; ID =3A; Tj=25°C - 25 35 mΩ
VGS =5V; ID =3A; Tj =150 °C;
see Figure 9; see Figure 10
--35 mΩ
VGS =5V; ID =3A; Tj =25°C; see Figure 9;
see Figure 10 1620mΩ
Dynamic characteristics
QG(tot) total gate charge ID =6A; VDS =16V; VGS =5V; Tj =25°C;
see Figure 11 15.3 - nC
QGS gate-source charge - 2.2 - nC
QGD gate-drain charge - 6 - nC
Ciss input capacitance VDS =10V; VGS =0V; f=1MHz; Tj =25°C;
see Figure 12 950 - pF
Coss output capacitance - 355 - pF
Crss reverse transfer
capacitance 256 - pF
td(on) turn-on delay time VDS =10V; RL =3.3 Ω; VGS =5V;
RG(ext) =4.7 Ω; Tj =25°C
-15 - ns rise time - 49 - ns
td(off) turn-off delay time - 50 - ns fall time - 23 - ns
Source-drain diode
VSD source-drain voltage IS =6A; VGS =0V; Tj=25 °C; see Figure 13 --1.2 V
trr reverse recovery time IS =6A; dIS/dt= -100 A/µs; VGS =0V;
VDS =20V; Tj =25°C
-40 - ns recovered charge - 7 - nC
NXP Semiconductors PHKD6N02LT
Dual N-channel TrenchMOS logic level FET
NXP Semiconductors PHKD6N02LT
Dual N-channel TrenchMOS logic level FET

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