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PHN203
Dual N-channel TrenchMOS logic level FET
PHN203
Dual N-channel TrenchMOS logic level FET
Rev. 05 — 27 April 2010 Product data sheet Product profile
1.1 General descriptionDual logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits Suitable for high frequency
applications due to fast switching
characteristics Suitable for logic level gate drive
sources
1.3 Applications DC-to-DC converters Lithium-ion battery applications
1.4 Quick reference data[1] Single device conducting.
Table 1. Quick reference dataVDS drain-source
voltage≥25 °C; Tj≤ 150°C --30 V drain current Tamb=25 °C; pulsed;
see Figure 1; see Figure 3
[1] --6.3 A
Ptot total power
dissipation
Tamb=25 °C; pulsed;
see Figure 2
[1] --2 W
Static characteristicsRDSon drain-source
on-state
resistance
VGS =10V; ID =7A; Tj =25°C;
see Figure 9; see Figure 10 2430mΩ
Dynamic characteristicsQGD gate-drain charge VGS =10V; ID =7A; VDS =15V; =25°C; see Figure 11 -nC
NXP Semiconductors PHN203
Dual N-channel TrenchMOS logic level FET Pinning information Ordering information Limiting values[1] Single device conducting.
Table 2. Pinning information1S1 source1
SOT96-1 (SO8) G1 gate1
3S2 source2 G2 gate2
5D2 drain2
6D2 drain2
7D1 drain1
8D1 drain1
Table 3. Ordering informationPHN203 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDS drain-source voltage Tj≥25 °C; Tj≤ 150°C --30 V
VDGR drain-gate voltage Tj≤ 150 °C; Tj≥25 °C; RGS =20kΩ --30 V
VGS gate-source voltage -20 - 20 V drain current Tamb=70 °C; pulsed; see Figure 1 [1] --5 A
Tamb=25 °C; pulsed; see Figure 1;
see Figure 3
[1] --6.3 A
IDM peak drain current tp≤10 µs; pulsed; Tamb =25°C;
see Figure 3
[1] --18 A
Ptot total power dissipation Tamb=25 °C; pulsed; see Figure 2 [1] --2 W
Tstg storage temperature -55 - 150 °C junction temperature -55 - 150 °C
Source-drain diode source current Tamb=25 °C; pulsed [1] --2 A
ISM peak source current tp≤10 µs; pulsed; Tamb =25°C [1] --4.1 A
Avalanche ruggednessEDS(AL)S non-repetitive
drain-source
avalanche energy
VGS =10V; Tj(init) =25°C; ID =8.7A;
Vsup≤30 V; unclamped; tp= 0.2 ms;
RGS =50Ω - 37.8 mJ
NXP Semiconductors PHN203
Dual N-channel TrenchMOS logic level FETNXP Semiconductors PHN203
Dual N-channel TrenchMOS logic level FET Thermal characteristics
Table 5. Thermal characteristicsRth(j-sp) thermal resistance from
junction to solder point
---K/W
Rth(j-a) thermal resistance from
junction to ambient
mounted on a printed-circuit board;
minimum footprint; see Figure 4 - 62.5 K/W
NXP Semiconductors PHN203
Dual N-channel TrenchMOS logic level FET Characteristics
Table 6. Characteristics
Static characteristicsV(BR)DSS drain-source
breakdown voltage =250 µA; VGS =0V; Tj= -55°C 27 - - V =250 µA; VGS =0V; Tj=25°C 30 --V
VGS(th) gate-source threshold
voltage =1mA; VDS =VGS; Tj =-55 °C;
see Figure 8
--2.2 V =1mA; VDS =VGS; Tj= 150 °C;
see Figure 8
0.6 --V =1mA; VDS =VGS; Tj =25°C;
see Figure 8
11.5 2V
IDSS drain leakage current VDS =24V; VGS =0V; Tj=25°C --1 µA
VDS =24V; VGS =0V; Tj= 150°C --10 µA
IGSS gate leakage current VGS =20V; VDS =0V; Tj=25°C - 10 100 nA
VGS =-20 V; VDS =0V; Tj=25°C - 10 100 nA
RDSon drain-source on-state
resistance
VGS =10V; ID =7A; Tj =25 °C;
see Figure 9; see Figure 10 2430mΩ
VGS =4.5 V; ID= 3.5 A; Tj =25°C;
see Figure 9; see Figure 10 3055mΩ
VGS =10V; ID =7A; Tj= 150 °C;
see Figure 9; see Figure 10 40.8 51 mΩ
Dynamic characteristicsQG(tot) total gate charge ID =7A; VDS =15V; VGS =10V; =25°C; see Figure 11 14.6 - nC
QGS gate-source charge - 2 - nC
QGD gate-drain charge - 3 - nC
Ciss input capacitance VDS =20V; VGS=0 V; f=1 MHz; =25°C; see Figure 12 560 - pF
Coss output capacitance - 125 - pF
Crss reverse transfer
capacitance
VDS 20 V; VGS =0V; f=1MHz; Tj =25°C;
see Figure 12
-85 - pF
td(on) turn-on delay time VDS =25V; RL =25 Ω; VGS =10V;
RG(ext) =6 Ω; Tj =25°C -ns rise time - 6 - ns
td(off) turn-off delay time - 21 - ns fall time - 11 - ns
Source-drain diodeVSD source-drain voltage IS= 1.25 A; VGS =0V; Tj =25 °C;
see Figure 13
-0.75 1 V
trr reverse recovery time IS =2A; dIS/dt= -100 A/µs; VGS =0V;
VDS =25V; Tj =25°C
-30 - ns
NXP Semiconductors PHN203
Dual N-channel TrenchMOS logic level FET
NXP Semiconductors PHN203
Dual N-channel TrenchMOS logic level FET
