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PM8834STN/a5200avai4 A dual low side MOSFET driver


PM8834 ,4 A dual low side MOSFET driverfeatures TTL/CMOS-compatible thresholds.PWM input signal for Driver 1 featuring TTL/CMOS-compatible ..
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PM8834
4 A dual low side MOSFET driver
October 2014 DocID15086 Rev 4 1/21
October 2014 DocID15086 Rev 4 1/21
PM8834

4 A dual low-side MOSFET driver
Datasheet - production data
Features
Dual independent low-side MOSFET driver
with 4 A sink and source capability Independent enable for each driver Driver output parallelability to support higher
driving capability Matched propagation delays CMOS/TTL-compatible input levels Wide input supply voltage range: 5 V to 18 V Embedded drivers with anti cross conduction
protection Low bias switching current Short propagation delays Wide operative temperature range:
-40 °C to 105 °C Industry standard SO8 package and MSOP8
with exposed pad
Applications
SMPS DC/DC converters Motor controllers Line drivers Class-D switching amplifiers
Description

The PM8834 is a flexible, high-frequency dual
low-side driver specifically designed to work with
high capacitive MOSFETs and IGBTs.
Both PM8834 outputs can sink and source 4 A
independently. A higher driving current can be
obtained by connecting the two PWM outputs in
parallel.
The PM8834 provides two enable pins which can
be used to enable the operation of one or both of
the output lines.
The PM8834 works with a CMOS/TTL-compatible
PWM signal.
The device is available in an SO8 or an MSOP8
package with an exposed pad.






Table 1. Device summary
Contents PM8834
2/21 DocID15086 Rev 4
Contents PM8834

2/21 DocID15086 Rev 4
Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1.1 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1.2 Enable pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Parallel output operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.4 Gate driver voltage flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 Output series resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DocID15086 Rev 4 3/21
PM8834 List of figures

DocID15086 Rev 4 3/21
PM8834 List of figures
List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Single high-current (up to 8 A) low-side driver configuration . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Minimal output series resistance for safe operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Equivalent circuit for MOSFET driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Power dissipation with load of 10 nF and 2.2 gate resistor. . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Power dissipation for capacitive load of 10 nF with 4.7  gate resistor . . . . . . . . . . . . . . . 14
Figure 9. Driver turn-on and turn-off paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Example of placement of external components - SO8 package. . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Example of placement of external components - MSOP8 package . . . . . . . . . . . . . . . . . . 16
Figure 12. SO-8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. MSOP-8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Block diagram PM8834
4/21 DocID15086 Rev 4
Block diagram PM8834

4/21 DocID15086 Rev 4
1 Block diagram
Figure 1. Block diagram
DocID15086 Rev 4 5/21
PM8834 Pin description and connections

DocID15086 Rev 4 5/21
PM8834 Pin description and connections Pin description and connections
Figure 2. Pin connections (top view)
2.1 Pin description


Table 2. Pin description
Pin description and connections PM8834
6/21 DocID15086 Rev 4
Pin description and connections PM8834

6/21 DocID15086 Rev 4
2.2 Thermal data


Note: Maximum power dissipation and derating factor are estimated assuming 125 °C as
maximum operating junction temperature.
Table 3. Thermal data
DocID15086 Rev 4 7/21
PM8834 Electrical specifications

DocID15086 Rev 4 7/21
PM8834 Electrical specifications
3 Electrical specifications
3.1 Absolute maximum ratings


3.2 Electrical characteristics


Table 4. Absolute maximum ratings
Table 5. Electrical characteristics [VCC = 5 V to 18 V, Tj = -40 °C to 105 °C unless otherwise

specified(1)]
Electrical specifications PM8834
8/21 DocID15086 Rev 4
Electrical specifications PM8834

8/21 DocID15086 Rev 4 Limits guaranteed by design and statistical analysis, not production tested. Production test is done at T = 25 °C. Parameter guaranteed by designed, not fully tested in production.
Table 5. Electrical characteristics (continued) [VCC = 5 V to 18 V, Tj = -40 °C to 105 °C unless

otherwise specified(1)]
DocID15086 Rev 4 9/21
PM8834 Device description and operation

DocID15086 Rev 4 9/21
PM8834 Device description and operation Device description and operation

The PM8834 is a dual low-side driver suitable for charging and discharging large capacitive
loads like MOSFETs or IGBTs used in power supplies and DC/DC modules. The PM8834
can sink and source 4 A on both low-side driver branches but a higher driving current can be
obtained by paralleling its outputs.
Even though this device has been designed to function with loads requiring high peak
current and fast switching time, the ultimate driving capability depends on the power
dissipation in the device which must be kept below the power dissipation capability of the
package. This aspect will be discussed in Section 5.2 on page 13.
For enhanced control of operations the PM8834 has been designed with dual independent
active-high enable pins (ENABLE_1 and ENABLE_2). Connecting these pins to the GND
pin will disable the corresponding low-side driver.
The PM8834 uses the VCC pin for supply and the GND pin for return.
The dual low-side driver has been designed to work with supply voltage in the range of 5 to V.
For VCC voltages greater than the UVLO threshold (UVLOVCC), the PWM input keeps the
control of the driver operations, provided that the corresponding enable pin is active. Both
PWM_1 and PWM_2 are internally pulled down so, if left floating, the corresponding output
pins are discharged.
The PM8834, during VCC startup, keeps both low-side MOSFETs in an OFF state until the
UVLO threshold is reached.
The input pins (PWM_1, PWM_2, ENABLE_1 and ENABLE_2) are CMOS/TTL-compatible
and can also operate with voltages up to VCC.
The voltage level of the input pins is not allowed to be higher than VCC under any operating
condition.
4.1 Input stage
4.1.1 PWM inputs

The inputs of the PM8834 dual low-side driver are compatible to CMOS/TTL levels with the
capability to be pulled up to VCC.
The relationship between the input pins (PWM_1, PWM_2) and the corresponding PWM
output pins (OUT_1, OUT_2) is depicted in Figure 3. In the worst case, input levels above
2.5 V are recognized as high voltage and values below 0.8 V are recognized as low logic
values. Propagation delays for high-low (tD_HL) and low-high (tD_LH) and rise (tR) and fall
(tR) times have been designed to ensure operation in a fast-switching environment.
Matched propagation delay in the two branches of the PM8834 ensures symmetry in
operation and allows parallel output functionality.
Each PWM input features a 10 µA pull-down to turn off (default state) the external MOSFET
/ IGBT.
Device description and operation PM8834
10/21 DocID15086 Rev 4
Device description and operation PM8834

10/21 DocID15086 Rev 4
Figure 3. Timing diagram
4.1.2 Enable pins

The PM8834 features two independent enable signals, ENABLE_1 and ENABLE_2, to
control the operation of each low-side driver. Both enable pins are internally pulled up to
VCC with a typ. 100 k resistance and are active high. In applications where ENABLE_1
and ENABLE_2 are not in use, it is strongly recommended to connect these pins to VCC
directly or with a pull-up resistor. ENABLE_1 and ENABLE_2 are compatible to CMOS/TTL
levels and can be directly pulled up to VCC. By default, because of the internal pull-up, both
drivers are enabled. It is possible to disable one or both low-side drivers, connecting the
corresponding enable signal to GND.
The enable pins cannot be used as input driving pins, but only as device control pins; they
must be set before to apply the PWM signals; high to low transition on enable pins cannot
be simultaneous with transition edges on the PWM inputs.
The enable pins are not designed and tested in terms of matched propagation delay time
and maximum operating frequency.
4.2 Output stage

The output stage of the PM8834 makes use of ST’s proprietary lateral DMOS. Both
N-DMOS and P-DMOS have been sized to exhibit high driving peak current as well as low
ON-resistance. Typical peak current is 4 A while output resistances are 1  and 0.7  for
P-DMOS and N-DMOS resistance respectively. The device features adaptive anti cross
conduction protection. The PM8834 continuously monitors the status of the internal N-
DMOS and P-DMOS. During a PWM transition, before switching on the desired DMOS, the
device waits until the other DMOS is completely turned off. No static current will then flow
from VCC to GND. During VCC startup, the internal N-DMOS is kept in an OFF state: with
typical VCC rise time, with slope >2 V/ms, the OUT pins are maintained at low level under
any operating condition. For VCC startup with very smooth rising edge, with slope < 2 V/ms,
the OUT pins can track the VCC rising edge until the UVLO threshold is reached, but the
voltage reached is maintained under 1.5 V under any operating condition.
DocID15086 Rev 4 11/21
PM8834 Device description and operation

DocID15086 Rev 4 11/21
PM8834 Device description and operation
4.3 Parallel output operation

For applications demanding high driving current capability (in excess of the 4 A provided by
the single section), the PM8834 allows paralleling the operation of the two drivers in order to
reach higher current, up to 8 A. This configuration is depicted in Figure 4 where both
PWM_1 and PWM_2 and OUT_1 and OUT_2 are tied together. The matching of internal
propagation delays guarantees that the two drivers are switched on and off simultaneously.
Figure 4. Single high-current (up to 8 A) low-side driver configuration
4.4 Gate driver voltage flexibility

The PM8834 allows the user to freely select the gate drive voltage in order to optimize the
efficiency of the application. The low-side MOSFET driving voltage depends on the voltage
applied to VCC and can range between 5 V to 18 V.
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