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PMB2306T ,PLL-Frequency SynthesizerBlock Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 &L ..
PMB2306T ,PLL-Frequency Synthesizercharacteristics.Terms of delivery and rights to change design reserved.For questions on technology, ..
PMB2314 ,Prescaler Circuit 2.1 GHzData Sheet, Version 1.2, December 2003Prescaler Circuit 2.1 GHzPMB 2314TVersion 1.5Wireless Infrast ..
PMB2330T ,2 GHz-MixerFeatures● Few external components● Low noise● Low spurious signal content● High conversion transcon ..
PSD813F2-A-70J ,Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5VPSD813F2, PSD833F2PSD834F2, PSD853F2, PSD854F2Flash In-System Programmable (ISP)Peripherals for 8-b ..
PSD813F2A-70J ,Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5VFEATURES SUMMARY■ FLASH IN-SYSTEM PROGRAMMABLE (ISP) Figure 1. PackagesPERIPHERAL FOR 8-BIT MCUS■ D ..
PSD813F2-A-90J ,Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5VFEATURES SUMMARY . . . . . 1SUMMARY DESCRIPTION . . . 6PIN DESCRIPTION 10PSD A ..
PSD813F2-A-90J ,Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5VFEATURES SUMMARY . . . . . 1SUMMARY DESCRIPTION . . . 6PIN DESCRIPTION 10PSD A ..
PSD813F2A-90J ,Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs, 5VPSD813F2, PSD833F2PSD834F2, PSD853F2, PSD854F2Flash In-System Programmable (ISP)Peripherals for 8-b ..
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PMB2306T
PLL-Frequency Synthesizer
ICs for Communications
PLL-Frequency Synthesizer
PMB2306R/PMB2306T Version 2.2
Data Sheet02.97
T2306-0V22-D1-7600
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As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for
applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or
the Siemens Companies and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
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1.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
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3.2Typical Supply Current ,DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.3AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193DFNDJH�2XWOLQHV�. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
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The PMB 2306T PLL is a high speed CMOS IC, especially designed for use in battery powered
radio equipment and mobile telephones. The primary applications will be in digital systems e.g.
GSM, PCN, ADC, JDC and DECT systems. The wide range of dividing ratios also allows application
in modern analog systemsSerial control (3-wire bus: data, clock, enable) for fast programming (Imax ~ 10 MHz)Switchablepolarityandphasedetectorcurrent programmable2 Multifunction outputsDigital phase detector output signals (e.g. for external charge pump)Irn, Ivn outputs of the R and N scalersPort 1 output (e.g. for standby of the prescaler)External current setting for PD outputLock detect output with gated anti-backlash pulse (quasi digital lock detect) 2YHUYLHZ
���)HDWXUHVLow operating current consumption
(typically 3.5 mA)High input sensitivity, high input frequencies
(220 MHz)Extremely fast phase detector without dead zoneLinearization of the phase detector output by current
sourcesSynchronous programming of the counters
(n-, n/a-, r-counters) and system parametersFast modulus switchover for 65-MHz operationSwitchable modulus trigger edgeLarge dividing ratios for small channel spacing
A scaler 0 to 127
N scaler 3 to 16.380
R scaler 3 to 65.535
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The circuit consists of a reference-, a- and n-counter, a dual modulus control logic, a
phase detector with charge pump output and a serial control logic. The setting of the
operating mode and the selection of the counter ratios is done serially at the ports CLK,
DA and EN.
The operating modes allow the selection of single or dual operation, asynchronous or
synchronous data acquisition, 4 different antibacklash-impulse times, 8 different PD-
output current modes, polarity setting of the PD-output signal, adjustment of the trigger-
edge of the MOD-output signal, 2 standby modes and the control of the multifunction
outputs MFO1 and MFO2.
The reference frequency is applied at the RI-input and scaled down by the r-counter. It’s
maximum value is 100 MHz. The VCO-frequency is applied at the FI-input and scaled
down by the n- or n/a-counter according to single or dual mode operation. The maximum
value at FI is 220 MHz at single-, and 65 MHz at dual mode operation.
The phase and frequency sensitive phase detector produces an output signal with
adjustable anti-backlash impulses in order to prevent a dead zone for very small phase
deviations. Phase differences of less than 100 ps can be resolved. In general the
shortest anti-backlash pulse gives the best system performance.
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Programming of the IC is done by a serial data control. The contents of the message are
assigned to the functional units according to the address.�6LQJOH�RU�GXDO�PRGH
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The PMB 2306T offers the possibility of synchronous data acquisition to avoid error
signals at the phase detector due to non-corresponding dividing factors in the counters
produced by asynchronous loading.
Synchronous programming guarantees control during changes of frequency or channel.
That means that the state of the phase detector or the phase difference is kept
maintained, and in case of “lock in”, the control process starts with the phase difference
“zero”.
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This is done as follows:
1.Setting of synchronous data acquisition by status 2.
2.Programming of the r-counter, status 1 (optional)-data is being loaded into shadow
registers.
3.Programming of the n- or n/a-counter-data is being loaded into shadow registers, the
EN-signal starts the synchronous loading procedure.
4.Synchronous programming – which means data transfer of all data from the shadow
registers to the data registers – takes place at that point in time when the respective
counter reaches “zero + 1”, the maximum repetition rate for channel change is
therefore IFI:N.
5.Transfer of status 1 information into the corresponding data register is tied to the n-
counter loading, but follows the loading of the n-data register in the distance of one n-
counter dividing ratio, this guarantees that for example a new PD-current value
becomes valid at the same time when the counters are loaded with the new data.
Synchronous avoids additional phase error caused by programming. Synchronous data
acquisition is of especial advantage, when large steps in frequency are to be made in a
short time. For this purpose a high reference frequency can be programmed in order to
achieve rapid – “rough” – transient response. This method increases the fundamental
frequency nearly by the square route of the reference frequency relation. When rough
lock is achieved, another synchronous data transfer is needed to switch back to the
original channel spacing. A “fine” lock in will finish the total step response. It may not be
necessary to change reference frequency, but it make sense to perform synchronous
data acquisition in any case. Especially for GSM, PCN, DECT, DAMPS, JDC, PHP
systems the synchronous mode should be used to get best performance of the PMB
2306T.
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The PMB 2306T has two standby modes (standby 1, 2) to reduce the current
consumption.
Standby 1 switches off the whole circuit, the current consumption is reduced below 1 μA.
Standby 2 switches off the counters, the charge pump and the outputs, only the
preamplifiers stay active.
The standby modes do not affect the port output signal. For the influence on the other
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3URJUDPPLQJ�7DEOHV�(cont’d) In general the shortest anti-backlash pulse gives the best system performance.No ABL (Anti-Backlash-Pulse) gating performed. This means, that at the LD output the anti-backlash pulse
will appear. In the other cases the anti-backlash pulse will be surpressed at the LD output.
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PD-current 2
PD-current 3Address0
Anti-backlash pulse width 1
Anti-backlash pulse width 2
Preamplifier select
Single / dual mode
Port 1
PD-current 1
Data acquisition mode
Mode 1
Mode 2
PD-polarity
Standby 1
Standby 2
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singledual
lowhigh
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negativepositive
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7A = –40 to 85°C
All pins are protected against ESD. Unused inputs without pullup resistors must be connected to either 9DD or 9SS.
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