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PRTR5V0U2AX
Ultra low capacitance double rail-to-rail ESD protection diode
1. Product profile
1.1 General descriptionUltra low capacitance double rail-to-rail ElectroStatic Discharge (ESD) protection diode in
a small SOT143B Surface-Mounted Device (SMD) plastic package.
The device is designed to protect two high-speed data lines or high-frequency signal lines
from the damage caused by ESD and other transients.
PRTR5V0U2AX integrates two ultra low capacitance rail-to-rail diodes and one additional
ESD protection diode to ensure signal line protection even if no supply voltage is
available.
1.2 Features and benefits ESD protection of two high-speed data lines or high-frequency signal lines Ultra low input/output to ground capacitance: C(I/O-GND) =1.8pF ESD protection up to 12kV IEC 61000-4-2, level 4 (ESD) Very low clamping voltage due to an integrated additional ESD protection diode Very low reverse current AEC-Q101 qualified Small SMD plastic package
1.3 Applications
1.4 Quick reference data
PRTR5V0U2AX
Ultra low capacitance double rail-to-rail ESD protection diode
Rev. 3 — 15 May 2012 Product data sheet USB 2.0 ports Digital cameras Digital Video Interface (DVI) WAN/LAN systems High-Definition Multimedia
Interface (HDMI) PC, notebooks, printers and other PC
peripherals Mobile phones
Table 1. Quick reference data
Per channelC(I/O-GND) input/output to ground
capacitance
f=1MHz;
V(I/O-GND) =0V
[1] -1.8 -pF
NXP Semiconductors PRTR5V0U2AX
Ultra low capacitance double rail-to-rail ESD protection diode[1] Measured from pin 2 and 3 to ground.
[2] Measured from pin 4 to ground.
2. Pinning information
3. Ordering information
4. Marking[1] * = placeholder for manufacturing site code.
Zener diodeVRWM reverse standoff voltage - - 5.5 V
Csup supply pin to ground
capacitance
f=1MHz;
VCC =0V
[2] -16 -pF
Table 1. Quick reference data …continued
Table 2. Pinning
Table 3. Ordering informationPRTR5V0U2AX - plastic surface-mounted package; 4 leads SOT143B
Table 4. Marking codesPRTR5V0U2AX *AE
NXP Semiconductors PRTR5V0U2AX
Ultra low capacitance double rail-to-rail ESD protection diode
5. Limiting values
Table 5. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
Tamb ambient temperature 40 +85 C
Tstg storage temperature 55 +125 C
Table 6. ESD standards complianceIEC 61000-4-2; level 4 (ESD) > 12 kV (contact)
NXP Semiconductors PRTR5V0U2AX
Ultra low capacitance double rail-to-rail ESD protection diode
6. Characteristics[1] Measured from pin 2, 3 and 4 to ground
[2] Measured from pin 4 to ground
[3] Measured from pin 2 and 3 to ground
Table 7. CharacteristicsTamb =25 C unless otherwise specified.
Per channel reverse current VR =3V [1]- <1 100 nA
C(I/O-GND) input/output to ground
capacitance
f=1MHz;
V(I/O-GND) =0V
[3] -1.8 -pF forward voltage IF=1 mA -0.7 -V
Zener diodeVRWM reverse standoff voltage - - 5.5 V
VBR breakdown voltage [2] 6- 9V
Csup supply pin to ground
capacitance
f=1MHz;
VCC =0V
[2] -16 -pF
NXP Semiconductors PRTR5V0U2AX
Ultra low capacitance double rail-to-rail ESD protection diode
NXP Semiconductors PRTR5V0U2AX
Ultra low capacitance double rail-to-rail ESD protection diode
7. Application informationHandling data rates up to 480 Mbit/s, USB 2.0 interfaces require ESD protection devices
with an extremely low line capacitance in order to avoid signal distortion.
With a capacitance of only 1.8 pF, the NXP PRTR5V0U2AX offers IEC 61000-4-2, level4
compliant ESD protection.
The PRTR5V0U2AX integrates two ultra-low capacitance rail-to-rail ESD protection
diodes and an additional ESD protection diode in a small 4-lead SOT143B package.
The additional ESD protection diode connected between ground and VCC prevents
charging of the supply.
To achieve the maximum ESD protection level, no additional external capacitors are
required.
Circuit board layout and protection device placementCircuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)
and surge transients. The following guidelines are recommended: Place the device as close to the input terminal or connector as possible. Minimize the path length between the device and the protected line. Keep parallel signal paths to a minimum. Avoid running protected conductors in parallel with unprotected conductors. Minimize all Printed-Circuit Board (PCB) conductive loops including power and
ground loops. Minimize the length of the transient return path to ground. Avoid using shared transient return paths to a common ground point. Use ground planes whenever possible. For multilayer PCBs, use ground vias.
