SN74ABT541BPWR ,Octal Buffers/Drivers With 3-State OutputsSN54ABT541, SN74ABT541BOCTAL BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
SN74ABT543ADB , OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABT543ADBR ,Octal Registered Transceivers With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ABT543ADBRG4 ,Octal Registered Transceivers With 3-State Outputs 24-SSOP -40 to 85 SN54ABT543A, SN74ABT543A OCTAL REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS157F – JANUARY 1991 ..
SN74ABT543ADWR ,Octal Registered Transceivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ABT543APW ,Octal Registered Transceivers With 3-State Outputslogic diagram (positive logic)2OEBA23CEBA1LEBA13OEAB11CEAB14LEABC13A1221D B1C11DTo Seven Other Chan ..
SN74LS151 ,LOW POWER SCHOTTKYLOGIC DIAGRAMI I I I I I I I0 1 2 3 4 5 6 74 3 2 1 15 14 13 129S210S111S07EV = PIN 16CCGND = PIN 8 ..
SN74LS151D ,8-INPUT MULTIPLEXERLOGIC DIAGRAM* * * * * * * ** * * * * * * ** * * * ** ** ** * * ** * * * * ** *
SN74LS151MEL ,8-Input Multiplexer• Schottky Process for High Speed• Multifunction CapabilityLOW• On-Chip Select Logic DecodingPOWER• ..
SN74LS151MR1 ,8-Input Multiplexer3SN74LS151DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)LimitsSym ..
SN74LS151MR1 ,8-Input MultiplexerFUNCTIONAL DESCRIPTIONThe LS151 is a logical implementation of a single pole, Z = E ⋅ (I ⋅ S ⋅ S ⋅ ..
SN74LS151N ,8-INPUT MULTIPLEXERLOGIC DIAGRAM* * * * * * * ** * * * * * * ** * * * ** ** ** * * ** * * * * ** *
SN74ABT541B-SN74ABT541BDBR-SN74ABT541BDBRG4-SN74ABT541BDW-SN74ABT541BDWR-SN74ABT541BN-SN74ABT541BNSR-SN74ABT541BNSRG4-SN74ABT541BPW-SN74ABT541BPWR
Octal Buffers/Drivers With 3-State Outputs
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FEATURES
SN54ABT541...J OR W PACKAGE
SN74ABT541B...DB, DW, N, OR PW PACKAGE
(TOP VIEW)OE1 VCC1 20 OE22 19 Y13 18 Y24 17
DESCRIPTION/ORDERING
SN54ABT541, SN74ABT541B
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS093L–DECEMBER 1993–REVISED DECEMBER 2006 State-of-the-Art EPIC-IIB™ BiCMOS Design
Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17 TypicalV OLP (Output Ground Bounce)<1VatCC=5V,TA= 25°CThe SN54ABT541 and
memory address registers.
printed circuit board layout.
PDIPSOIC
–40°Cto 85°CSSOPTSSOP
CDIP
–55°Cto 125°C CFP
LCCC drawings, standard
