SN74ABT651DWR ,Octal Bus Transceivers And Registers With 3-State Outputs
SN74ABT652ADBR ,Octal Registered Transceivers With 3-State Outputs
SN74ABT652ADWR ,Octal Registered Transceivers With 3-State Outputs
SN74ABT657ADBR ,Octal Transceivers With Parity Generators/Checkers And 3-State Outputs SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERSAND 3-STATE OUTPUTSSCBS ..
SN74ABT657ADWR ,Octal Transceivers With Parity Generators/Checkers And 3-State Outputs SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERSAND 3-STATE OUTPUTSSCBS ..
SN74ABT821A ,10-Bit Bus Interface Flip-Flops With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74LS158D ,QUAD 2-INPUT MULTIPLEXER
SN74LS158DR ,Quadruple 2-Line To 1-Line Data Selectors/Multiplexers
SN74LS158N ,QUAD 2-INPUT MULTIPLEXERSN54/74LS158QUAD 2-INPUT MULTIPLEXERThe LSTTL/MSI SN54L/ 74LS158 is a high speed Quad 2-input Multi ..
SN74LS158NSR ,Quadruple 2-Line To 1-Line Data Selectors/Multiplexers
SN74LS158NSR ,Quadruple 2-Line To 1-Line Data Selectors/Multiplexers
SN74LS15N ,TRIPLE 3-INPUT AND GATE
SN74ABT651DWR
Octal Bus Transceivers And Registers With 3-State Outputs
Latch-Up Performance Exceeds 500 mA PerJESD 17 Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C High-Drive Outputs (–32-mA IOH,
64-mA IOL) Multiplexed Real-Time and Stored Data Inverting Data Paths Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Plastic (NT) and Ceramic (JT) DIPs
descriptionThese devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions. The
select-control (SAB and SBA) inputs are provided
to select whether real-time or stored data is
transferred. A low input level selects real-time
data, and a high input level selects stored data.
Figure 1 illustrates the four fundamental
bus-management functions that can be
performed with the ’ABT651 devices.
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all
the other data sources to the two sets of bus lines are at high impedance, each set remains at its last state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ABT651... FK PACKAGE
(TOP VIEW)OEAB
GND
SBA
OEBA
OEBA
GNDB7B6
OEABSABCLKABNC
CLKBASAB
NC – No internal connection
