SN74ABT657ADBR ,Octal Transceivers With Parity Generators/Checkers And 3-State Outputs SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERSAND 3-STATE OUTPUTSSCBS ..
SN74ABT657ADWR ,Octal Transceivers With Parity Generators/Checkers And 3-State Outputs SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERSAND 3-STATE OUTPUTSSCBS ..
SN74ABT821A ,10-Bit Bus Interface Flip-Flops With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74ABT821ADBR ,10-Bit Bus Interface Flip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74ABT821ADW ,10-Bit Bus Interface Flip-Flops With 3-State Outputslogic diagram (positive logic)1OE13CLKC1231Q21D 1DTo Nine Other ChannelsPin numbers shown are for t ..
SN74ABT821ADWR ,10-Bit Bus Interface Flip-Flops With 3-State Outputs SN54ABT821, SN74ABT821A 10-BIT BUS-INTERFACE FLIP-FLOPSWITH 3-STATE OUTPUTSSCBS193E – FEBRUARY 199 ..
SN74LS158DR ,Quadruple 2-Line To 1-Line Data Selectors/Multiplexers
SN74LS158N ,QUAD 2-INPUT MULTIPLEXERSN54/74LS158QUAD 2-INPUT MULTIPLEXERThe LSTTL/MSI SN54L/ 74LS158 is a high speed Quad 2-input Multi ..
SN74LS158NSR ,Quadruple 2-Line To 1-Line Data Selectors/Multiplexers
SN74LS158NSR ,Quadruple 2-Line To 1-Line Data Selectors/Multiplexers
SN74LS15N ,TRIPLE 3-INPUT AND GATE
SN74LS15N ,TRIPLE 3-INPUT AND GATE
SN74ABT657ADBR-SN74ABT657ADWR
Octal Transceivers With Parity Generators/Checkers And 3-State Outputs
Latch-Up Performance Exceeds 500 mA PerJEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C High-Impedance State During Power Up
and Power Down Flow-Through Architecture Optimizes PCB
Layout High-Drive Outputs (–32-mA IOH, 64-mA IOL) Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Plastic (NT) and
Ceramic (JT) DIPs
description ABT657A transceivers have eight
noninverting buffers with parity-generator/
checker circuits and control signals. The
transmit/receive (T/R) input determines the
direction of data flow. When T/R is high, data flows
from the A port to the B port (transmit mode); when
T/R is low, data flows from the B port to the A port
(receive mode). When the output-enable (OE)
input is high, both the A and B ports are in the
high-impedance state.
Odd or even parity is selected by a logic high or
low level on the ODD/EVEN input. PARITY carries
the parity-bit value; it is an output from the parity
generator/checker in the transmit mode and an
input to the parity generator/checker in the receive
mode.
In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic
level that maintains the parity sense selected by the level at ODD/EVEN. For example, if ODD/EVEN is low
(even parity selected) and there are five high bits on the A bus, PARITY is set to the logic high level so that an
even number of the nine total bits (eight A-bus bits plus parity bit) are high.
In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic
level indicates whether or not the data to be received exhibits the correct parity sense. For example, if
ODD/EVEN is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, ERR is
low, indicating a parity error.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VCC
ODD/EVEN
ERR
GND
GND
PARITY
T/R
ODD/EVEN
ERR
PARITY
GNDGNDB3B2A7A6NC A5A4
SN54ABT657A... FK PACKAGE
(TOP VIEW) NC – No internal connection
