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SN74ABT8996-SN74ABT8996PW-SN74ABT8996PWLE
10-Bit Addressable Scan Ports Multidrop-Addressable IEEE STD 1194.1 (JTAG) TAP Transceivers
Higher Levels of System Integration Promote Reuse of Lower-Level
(Chip/Board) Tests in System Environment Switch-Based Architecture Allows Direct
Connect of Primary TAP to Secondary TAP Primary TAP Is Multidrop for Minimal Use of
Backplane Wiring Channels Simple Addressing (Shadow) Protocol Is
Received/Acknowledged on Primary TAP Shadow Protocols Can Occur in Any of
Test-Logic-Reset, Run-Test/Idle, Pause-DR,
and Pause-IR TAP States to Provide for
Board-to-Board Test and Built-In Self-Test 10-Bit Address Space Provides for Up to
1021 User-Specified Board Addresses Bypass (BYP) Pin Forces
Primary-to-Secondary Connection Without
Use of Shadow Protocols Connect (CON) Pin Provides Indication of
Primary-to-Secondary Connection High-Drive Outputs (–32-mA IOH, 64-mA IOL)
Support Backplane Interface at Primary and
High Fanout at Secondary Package Options Include Plastic Small-
Outline (DW) and Thin Shrink Small-
Outline (PW) Packages, Ceramic Chip
Carriers (FK), and Ceramic DIPs (JT)
descriptionThe ’ABT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments (TI) SCOPE
testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan
to facilitate testing of complex circuit assemblies. Unlike most SCOPE devices, the ASP is not a
boundary-scannable device, rather, it applies TI’s addressable-shadow-port technology to the IEEE Standard
1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level.
Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP
signals to a set of secondary TAP signals – for example, to interface backplane TAP signals to a board-level
TAP. The ASP provides all signal buffering that might be required at these two interfaces. When primary and
secondary TAPs are connected, only a moderate propagation delay is introduced – no storage/retiming
elements are inserted. This minimizes the need for reformatting board-level test vectors for in-system use.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.CC
CON
STDI
STCK
BYP
GND
PTDO
PTCK
SN54ABT8996... FK PACKAGE
(TOP VIEW)A3A4
STRST
STDO
PTDI
PTRST A6A7A5
PTMS STMS
BYP
GND
PTDO
PTCK
PTMS
PTDI
PTRST
VCC
CON
STDI
STCK
STMS
STDO
STRST
NC – No internal connection
