SN74AC563N ,Octal D-Type Transparent Latches With 3-State Outputs SCAS552C − NOVEMBER 1995 − REV ..
SN74AC564N ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74AC564PWR ,Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs SCAS551D− NOVEMBER 1995 − R ..
SN74AC573DBRG4 ,Octal D-Type Transparent Latches With 3-State Outputs 20-SSOP -40 to 85maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
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SN74LS193D ,PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER
SN74LS193J ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear
SN74LS193J ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear
SN74LS193J ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear
SN74LS193J ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear
SN74LS193N ,PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERSN54/74LS192SN54/74LS193PRESETTABLE BCD/DECADEUP/DOWN COUNTERPRESETTABLE 4-BIT BINARYPRESETTABLE BC ..
SN74AC563N
Octal D-Type Transparent Latches With 3-State Outputs
Directly Full Parallel Access for Loading Flow-Through Architecture to Optimize
PCB Layout
description/ordering informationThe ’AC563 devices are octal D-type transparent
latches with 3-state outputs. When the
latch-enable (LE) input is high, the Q outputs
follow the complements of the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the inverse logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
OE does not affect internal operations of the
latches. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
