SN74ACT7814-20DL ,64 x 18 asynchronous FIFO memory SN74ACT7814 64 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS209C – APRIL 1992 – REVISED APRIL 1998D ..
SN74ACT7814-20DLR , 64 x 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7814-25DL , 64 x 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7814-40DL ,64 x 18 asynchronous FIFO memory SN74ACT7814 64 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS209C – APRIL 1992 – REVISED APRIL 1998D ..
SN74ACT7881-20FN ,1024 x 18 synchronous FIFO memory
SN74ACT7881-20FN ,1024 x 18 synchronous FIFO memory
SN74LS28 ,QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS
SN74LS280J ,9-bit odd/even parity generators / checkers
SN74LS280J ,9-bit odd/even parity generators / checkers
SN74LS280J ,9-bit odd/even parity generators / checkers
SN74LS280N ,9-BIT ODD/EVEN PARITY GENERATORS/CHECKERSSN54/74LS2809-BIT ODD/EVEN PARITYGENERATORS/CHECKERSThe SN54/74LS280 is a Universal 9-Bit Parity Ge ..
SN74LS280NE4 , 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS
SN74ACT7814-20DL-SN74ACT7814-40DL
64 x 18 asynchronous FIFO memory
Low-Power Advanced CMOS Technology Full, Empty, and Half-Full Flags Programmable Almost-Full/Almost-EmptyFlag Fast Access Times of 15 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously Data Rates up to 50 MHz 3-State Outputs Pin-to-Pin Compatible With SN74ACT7804
and SN74ACT7806 Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Spacing
descriptionA FIFO memory is a storage device that allows
data to be written into and read from its array at
independent data rates. The SN74ACT7814 is a
64-word by 18-bit FIFO for high speed and fast
access times. It processes data at rates up to
50 MHz and access times of 15 ns in a bit-parallel
format.
Data is written into memory on a low-to-high
transition at the load clock (LDCK) input and is
read out on a low-to-high transition at the unload
clock (UNCK) input. The memory is full when the
number of words clocked in exceeds the number
of words clocked out by 64. When the memory is
full, LDCK signals have no effect on the data
residing in memory. When the memory is empty,
UNCK signals have no effect.
Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and
almost-full/almost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the
memory is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF
output is high when the FIFO contains 32 or more words and is low when it contains 31 or fewer words. The
AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are
used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN)
is low. The AF/AE flag is high when the FIFO contains X or fewer words or (64 – Y) or more words. The AF/AE
flag is low when the FIFO contains between (X + 1) and (63 – Y) words.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D16
D15
D14
D13
D12
D11
D10
VCC
GND
PEN
AF/AE
LDCK
FULL
Q16
Q15
GND
Q14
VCC
Q13
Q12
Q11
Q10
GND
VCC
GND
UNCK
EMPTY
