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SN74HCT139D-SN74HCT139DR-SN74HCT139N
Dual 2-Line To 4-Line Decoders/Demultiplexers
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatible Designed Specifically for High-SpeedMemory Decoders and Data-Transmission
Systems Incorporate Two Enable Inputs to Simplify
Cascading and/or Data Reception
description/ordering informationThe ’HCT139 devices are designed for
high-performance memory-decoding or
data-routing applications requiring very short
propagation delay times. In high-performance
memory systems, these decoders can minimize
the effects of system decoding. When employed
with high-speed memories utilizing a fast enable
circuit, the delay time of these decoders and the
enable time of the memory usually are less than
the typical access time of the memory. This means
that the effective system delay introduced by the
decoders is negligible.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
2Y0
2Y1
1Y0
1Y1
1Y21GNC
2Y32Y22G
1Y3
GND
SN54HCT139... FK PACKAGE
(TOP VIEW)NC − No internal connection
1Y0
1Y1
1Y2
1Y3
GND
2Y0
2Y1
2Y2
2Y3
